2 * i.MX drm driver - Television Encoder (TVEv2)
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
23 #include <linux/component.h>
24 #include <linux/module.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/spinlock.h>
29 #include <linux/videodev2.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <video/imx-ipu-v3.h>
37 #define TVE_COM_CONF_REG 0x00
38 #define TVE_TVDAC0_CONT_REG 0x28
39 #define TVE_TVDAC1_CONT_REG 0x2c
40 #define TVE_TVDAC2_CONT_REG 0x30
41 #define TVE_CD_CONT_REG 0x34
42 #define TVE_INT_CONT_REG 0x64
43 #define TVE_STAT_REG 0x68
44 #define TVE_TST_MODE_REG 0x6c
45 #define TVE_MV_CONT_REG 0xdc
47 /* TVE_COM_CONF_REG */
48 #define TVE_SYNC_CH_2_EN BIT(22)
49 #define TVE_SYNC_CH_1_EN BIT(21)
50 #define TVE_SYNC_CH_0_EN BIT(20)
51 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
52 #define TVE_TV_OUT_DISABLE (0x0 << 12)
53 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
54 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
55 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
56 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
57 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
58 #define TVE_TV_OUT_YPBPR (0x6 << 12)
59 #define TVE_TV_OUT_RGB (0x7 << 12)
60 #define TVE_TV_STAND_MASK (0xf << 8)
61 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
62 #define TVE_P2I_CONV_EN BIT(7)
63 #define TVE_INP_VIDEO_FORM BIT(6)
64 #define TVE_INP_YCBCR_422 (0x0 << 6)
65 #define TVE_INP_YCBCR_444 (0x1 << 6)
66 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
67 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
68 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
69 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
70 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
71 #define TVE_IPU_CLK_EN_OFS 3
72 #define TVE_IPU_CLK_EN BIT(3)
73 #define TVE_DAC_SAMP_RATE_OFS 1
74 #define TVE_DAC_SAMP_RATE_WIDTH 2
75 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
76 #define TVE_DAC_FULL_RATE (0x0 << 1)
77 #define TVE_DAC_DIV2_RATE (0x1 << 1)
78 #define TVE_DAC_DIV4_RATE (0x2 << 1)
81 /* TVE_TVDACx_CONT_REG */
82 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
85 #define TVE_CD_CH_2_SM_EN BIT(22)
86 #define TVE_CD_CH_1_SM_EN BIT(21)
87 #define TVE_CD_CH_0_SM_EN BIT(20)
88 #define TVE_CD_CH_2_LM_EN BIT(18)
89 #define TVE_CD_CH_1_LM_EN BIT(17)
90 #define TVE_CD_CH_0_LM_EN BIT(16)
91 #define TVE_CD_CH_2_REF_LVL BIT(10)
92 #define TVE_CD_CH_1_REF_LVL BIT(9)
93 #define TVE_CD_CH_0_REF_LVL BIT(8)
94 #define TVE_CD_EN BIT(0)
96 /* TVE_INT_CONT_REG */
97 #define TVE_FRAME_END_IEN BIT(13)
98 #define TVE_CD_MON_END_IEN BIT(2)
99 #define TVE_CD_SM_IEN BIT(1)
100 #define TVE_CD_LM_IEN BIT(0)
102 /* TVE_TST_MODE_REG */
103 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
105 #define con_to_tve(x) container_of(x, struct imx_tve, connector)
106 #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
114 struct drm_connector connector;
115 struct drm_encoder encoder;
117 spinlock_t lock; /* register lock */
121 struct regmap *regmap;
122 struct regulator *dac_reg;
123 struct i2c_adapter *ddc;
125 struct clk *di_sel_clk;
126 struct clk_hw clk_hw_di;
132 static void tve_lock(void *__tve)
133 __acquires(&tve->lock)
135 struct imx_tve *tve = __tve;
137 spin_lock(&tve->lock);
140 static void tve_unlock(void *__tve)
141 __releases(&tve->lock)
143 struct imx_tve *tve = __tve;
145 spin_unlock(&tve->lock);
148 static void tve_enable(struct imx_tve *tve)
154 clk_prepare_enable(tve->clk);
155 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
156 TVE_IPU_CLK_EN | TVE_EN,
157 TVE_IPU_CLK_EN | TVE_EN);
160 /* clear interrupt status register */
161 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
163 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
164 if (tve->mode == TVE_MODE_VGA)
165 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
167 regmap_write(tve->regmap, TVE_INT_CONT_REG,
173 static void tve_disable(struct imx_tve *tve)
178 tve->enabled = false;
179 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
180 TVE_IPU_CLK_EN | TVE_EN, 0);
181 clk_disable_unprepare(tve->clk);
185 static int tve_setup_tvout(struct imx_tve *tve)
190 static int tve_setup_vga(struct imx_tve *tve)
196 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
197 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
198 TVE_TVDAC_GAIN_MASK, 0x0a);
199 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
200 TVE_TVDAC_GAIN_MASK, 0x0a);
201 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
202 TVE_TVDAC_GAIN_MASK, 0x0a);
204 /* set configuration register */
205 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
206 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
207 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
208 val |= TVE_TV_STAND_HD_1080P30 | 0;
209 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
210 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
211 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
213 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
217 /* set test mode (as documented) */
218 ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
219 TVE_TVDAC_TEST_MODE_MASK, 1);
224 static enum drm_connector_status imx_tve_connector_detect(
225 struct drm_connector *connector, bool force)
227 return connector_status_connected;
230 static int imx_tve_connector_get_modes(struct drm_connector *connector)
232 struct imx_tve *tve = con_to_tve(connector);
239 edid = drm_get_edid(connector, tve->ddc);
241 drm_mode_connector_update_edid_property(connector, edid);
242 ret = drm_add_edid_modes(connector, edid);
249 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
250 struct drm_display_mode *mode)
252 struct imx_tve *tve = con_to_tve(connector);
255 /* pixel clock with 2x oversampling */
256 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
257 if (rate == mode->clock)
260 /* pixel clock without oversampling */
261 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
262 if (rate == mode->clock)
265 dev_warn(tve->dev, "ignoring mode %dx%d\n",
266 mode->hdisplay, mode->vdisplay);
271 static struct drm_encoder *imx_tve_connector_best_encoder(
272 struct drm_connector *connector)
274 struct imx_tve *tve = con_to_tve(connector);
276 return &tve->encoder;
279 static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
281 struct imx_tve *tve = enc_to_tve(encoder);
284 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
285 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
287 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
290 static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
291 const struct drm_display_mode *mode,
292 struct drm_display_mode *adjusted_mode)
297 static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
299 struct imx_tve *tve = enc_to_tve(encoder);
305 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
306 tve->hsync_pin, tve->vsync_pin);
309 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
314 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
315 struct drm_display_mode *mode,
316 struct drm_display_mode *adjusted_mode)
318 struct imx_tve *tve = enc_to_tve(encoder);
319 unsigned long rounded_rate;
326 * we should try 4k * mode->clock first,
327 * and enable 4x oversampling for lower resolutions
329 rate = 2000UL * mode->clock;
330 clk_set_rate(tve->clk, rate);
331 rounded_rate = clk_get_rate(tve->clk);
332 if (rounded_rate >= rate)
334 clk_set_rate(tve->di_clk, rounded_rate / div);
336 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
338 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
342 if (tve->mode == TVE_MODE_VGA)
345 tve_setup_tvout(tve);
348 static void imx_tve_encoder_commit(struct drm_encoder *encoder)
350 struct imx_tve *tve = enc_to_tve(encoder);
355 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
357 struct imx_tve *tve = enc_to_tve(encoder);
362 static struct drm_connector_funcs imx_tve_connector_funcs = {
363 .dpms = drm_helper_connector_dpms,
364 .fill_modes = drm_helper_probe_single_connector_modes,
365 .detect = imx_tve_connector_detect,
366 .destroy = imx_drm_connector_destroy,
369 static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
370 .get_modes = imx_tve_connector_get_modes,
371 .best_encoder = imx_tve_connector_best_encoder,
372 .mode_valid = imx_tve_connector_mode_valid,
375 static struct drm_encoder_funcs imx_tve_encoder_funcs = {
376 .destroy = imx_drm_encoder_destroy,
379 static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
380 .dpms = imx_tve_encoder_dpms,
381 .mode_fixup = imx_tve_encoder_mode_fixup,
382 .prepare = imx_tve_encoder_prepare,
383 .mode_set = imx_tve_encoder_mode_set,
384 .commit = imx_tve_encoder_commit,
385 .disable = imx_tve_encoder_disable,
388 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
390 struct imx_tve *tve = data;
393 regmap_read(tve->regmap, TVE_STAT_REG, &val);
395 /* clear interrupt status register */
396 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
401 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
402 unsigned long parent_rate)
404 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
408 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
412 switch (val & TVE_DAC_SAMP_RATE_MASK) {
413 case TVE_DAC_DIV4_RATE:
414 return parent_rate / 4;
415 case TVE_DAC_DIV2_RATE:
416 return parent_rate / 2;
417 case TVE_DAC_FULL_RATE:
425 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
426 unsigned long *prate)
438 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
439 unsigned long parent_rate)
441 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
446 div = parent_rate / rate;
448 val = TVE_DAC_DIV4_RATE;
450 val = TVE_DAC_DIV2_RATE;
452 val = TVE_DAC_FULL_RATE;
454 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
455 TVE_DAC_SAMP_RATE_MASK, val);
458 dev_err(tve->dev, "failed to set divider: %d\n", ret);
465 static struct clk_ops clk_tve_di_ops = {
466 .round_rate = clk_tve_di_round_rate,
467 .set_rate = clk_tve_di_set_rate,
468 .recalc_rate = clk_tve_di_recalc_rate,
471 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
473 const char *tve_di_parent[1];
474 struct clk_init_data init = {
476 .ops = &clk_tve_di_ops,
481 tve_di_parent[0] = __clk_get_name(tve->clk);
482 init.parent_names = (const char **)&tve_di_parent;
484 tve->clk_hw_di.init = &init;
485 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
486 if (IS_ERR(tve->di_clk)) {
487 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
488 PTR_ERR(tve->di_clk));
489 return PTR_ERR(tve->di_clk);
495 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
500 encoder_type = tve->mode == TVE_MODE_VGA ?
501 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
503 ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
508 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
509 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
512 drm_connector_helper_add(&tve->connector,
513 &imx_tve_connector_helper_funcs);
514 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
515 DRM_MODE_CONNECTOR_VGA);
517 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
522 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
524 return (reg % 4 == 0) && (reg <= 0xdc);
527 static struct regmap_config tve_regmap_config = {
532 .readable_reg = imx_tve_readable_reg,
535 .unlock = tve_unlock,
537 .max_register = 0xdc,
540 static const char * const imx_tve_modes[] = {
541 [TVE_MODE_TVOUT] = "tvout",
542 [TVE_MODE_VGA] = "vga",
545 static const int of_get_tve_mode(struct device_node *np)
550 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
554 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
555 if (!strcasecmp(bm, imx_tve_modes[i]))
561 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
563 struct platform_device *pdev = to_platform_device(dev);
564 struct drm_device *drm = data;
565 struct device_node *np = dev->of_node;
566 struct device_node *ddc_node;
568 struct resource *res;
574 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
579 spin_lock_init(&tve->lock);
581 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
583 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
584 of_node_put(ddc_node);
587 tve->mode = of_get_tve_mode(np);
588 if (tve->mode != TVE_MODE_VGA) {
589 dev_err(dev, "only VGA mode supported, currently\n");
593 if (tve->mode == TVE_MODE_VGA) {
594 ret = of_property_read_u32(np, "fsl,hsync-pin",
598 dev_err(dev, "failed to get vsync pin\n");
602 ret |= of_property_read_u32(np, "fsl,vsync-pin",
606 dev_err(dev, "failed to get vsync pin\n");
611 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
612 base = devm_ioremap_resource(dev, res);
614 return PTR_ERR(base);
616 tve_regmap_config.lock_arg = tve;
617 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
619 if (IS_ERR(tve->regmap)) {
620 dev_err(dev, "failed to init regmap: %ld\n",
621 PTR_ERR(tve->regmap));
622 return PTR_ERR(tve->regmap);
625 irq = platform_get_irq(pdev, 0);
627 dev_err(dev, "failed to get irq\n");
631 ret = devm_request_threaded_irq(dev, irq, NULL,
632 imx_tve_irq_handler, IRQF_ONESHOT,
635 dev_err(dev, "failed to request irq: %d\n", ret);
639 tve->dac_reg = devm_regulator_get(dev, "dac");
640 if (!IS_ERR(tve->dac_reg)) {
641 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
642 ret = regulator_enable(tve->dac_reg);
647 tve->clk = devm_clk_get(dev, "tve");
648 if (IS_ERR(tve->clk)) {
649 dev_err(dev, "failed to get high speed tve clock: %ld\n",
651 return PTR_ERR(tve->clk);
654 /* this is the IPU DI clock input selector, can be parented to tve_di */
655 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
656 if (IS_ERR(tve->di_sel_clk)) {
657 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
658 PTR_ERR(tve->di_sel_clk));
659 return PTR_ERR(tve->di_sel_clk);
662 ret = tve_clk_init(tve, base);
666 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
668 dev_err(dev, "failed to read configuration register: %d\n", ret);
671 if (val != 0x00100000) {
672 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
676 /* disable cable detection for VGA mode */
677 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
679 ret = imx_tve_register(drm, tve);
683 dev_set_drvdata(dev, tve);
688 static void imx_tve_unbind(struct device *dev, struct device *master,
691 struct imx_tve *tve = dev_get_drvdata(dev);
693 tve->connector.funcs->destroy(&tve->connector);
694 tve->encoder.funcs->destroy(&tve->encoder);
696 if (!IS_ERR(tve->dac_reg))
697 regulator_disable(tve->dac_reg);
700 static const struct component_ops imx_tve_ops = {
701 .bind = imx_tve_bind,
702 .unbind = imx_tve_unbind,
705 static int imx_tve_probe(struct platform_device *pdev)
707 return component_add(&pdev->dev, &imx_tve_ops);
710 static int imx_tve_remove(struct platform_device *pdev)
712 component_del(&pdev->dev, &imx_tve_ops);
716 static const struct of_device_id imx_tve_dt_ids[] = {
717 { .compatible = "fsl,imx53-tve", },
721 static struct platform_driver imx_tve_driver = {
722 .probe = imx_tve_probe,
723 .remove = imx_tve_remove,
725 .of_match_table = imx_tve_dt_ids,
730 module_platform_driver(imx_tve_driver);
732 MODULE_DESCRIPTION("i.MX Television Encoder driver");
733 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
734 MODULE_LICENSE("GPL");
735 MODULE_ALIAS("platform:imx-tve");