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[cascardo/linux.git] / drivers / gpu / drm / msm / mdp / mdp4 / mdp4_crtc.c
1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published by
7  * the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 #include "mdp4_kms.h"
19
20 #include <drm/drm_mode.h>
21 #include "drm_crtc.h"
22 #include "drm_crtc_helper.h"
23 #include "drm_flip_work.h"
24
25 struct mdp4_crtc {
26         struct drm_crtc base;
27         char name[8];
28         int id;
29         int ovlp;
30         enum mdp4_dma dma;
31         bool enabled;
32
33         /* which mixer/encoder we route output to: */
34         int mixer;
35
36         struct {
37                 spinlock_t lock;
38                 bool stale;
39                 uint32_t width, height;
40                 uint32_t x, y;
41
42                 /* next cursor to scan-out: */
43                 uint32_t next_iova;
44                 struct drm_gem_object *next_bo;
45
46                 /* current cursor being scanned out: */
47                 struct drm_gem_object *scanout_bo;
48         } cursor;
49
50
51         /* if there is a pending flip, these will be non-null: */
52         struct drm_pending_vblank_event *event;
53
54 #define PENDING_CURSOR 0x1
55 #define PENDING_FLIP   0x2
56         atomic_t pending;
57
58         /* for unref'ing cursor bo's after scanout completes: */
59         struct drm_flip_work unref_cursor_work;
60
61         struct mdp_irq vblank;
62         struct mdp_irq err;
63 };
64 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
65
66 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
67 {
68         struct msm_drm_private *priv = crtc->dev->dev_private;
69         return to_mdp4_kms(to_mdp_kms(priv->kms));
70 }
71
72 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
73 {
74         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
75
76         atomic_or(pending, &mdp4_crtc->pending);
77         mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
78 }
79
80 static void crtc_flush(struct drm_crtc *crtc)
81 {
82         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
83         struct mdp4_kms *mdp4_kms = get_kms(crtc);
84         struct drm_plane *plane;
85         uint32_t flush = 0;
86
87         drm_atomic_crtc_for_each_plane(plane, crtc) {
88                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
89                 flush |= pipe2flush(pipe_id);
90         }
91
92         flush |= ovlp2flush(mdp4_crtc->ovlp);
93
94         DBG("%s: flush=%08x", mdp4_crtc->name, flush);
95
96         mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
97 }
98
99 /* if file!=NULL, this is preclose potential cancel-flip path */
100 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
101 {
102         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
103         struct drm_device *dev = crtc->dev;
104         struct drm_pending_vblank_event *event;
105         unsigned long flags;
106
107         spin_lock_irqsave(&dev->event_lock, flags);
108         event = mdp4_crtc->event;
109         if (event) {
110                 /* if regular vblank case (!file) or if cancel-flip from
111                  * preclose on file that requested flip, then send the
112                  * event:
113                  */
114                 if (!file || (event->base.file_priv == file)) {
115                         mdp4_crtc->event = NULL;
116                         DBG("%s: send event: %p", mdp4_crtc->name, event);
117                         drm_send_vblank_event(dev, mdp4_crtc->id, event);
118                 }
119         }
120         spin_unlock_irqrestore(&dev->event_lock, flags);
121 }
122
123 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
124 {
125         struct mdp4_crtc *mdp4_crtc =
126                 container_of(work, struct mdp4_crtc, unref_cursor_work);
127         struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
128
129         msm_gem_put_iova(val, mdp4_kms->id);
130         drm_gem_object_unreference_unlocked(val);
131 }
132
133 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
134 {
135         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
136
137         drm_crtc_cleanup(crtc);
138         drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
139
140         kfree(mdp4_crtc);
141 }
142
143 static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
144 {
145         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
146         struct mdp4_kms *mdp4_kms = get_kms(crtc);
147         bool enabled = (mode == DRM_MODE_DPMS_ON);
148
149         DBG("%s: mode=%d", mdp4_crtc->name, mode);
150
151         if (enabled != mdp4_crtc->enabled) {
152                 if (enabled) {
153                         mdp4_enable(mdp4_kms);
154                         mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
155                 } else {
156                         mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
157                         mdp4_disable(mdp4_kms);
158                 }
159                 mdp4_crtc->enabled = enabled;
160         }
161 }
162
163 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
164                 const struct drm_display_mode *mode,
165                 struct drm_display_mode *adjusted_mode)
166 {
167         return true;
168 }
169
170 /* statically (for now) map planes to mixer stage (z-order): */
171 static const int idxs[] = {
172                 [VG1]  = 1,
173                 [VG2]  = 2,
174                 [RGB1] = 0,
175                 [RGB2] = 0,
176                 [RGB3] = 0,
177                 [VG3]  = 3,
178                 [VG4]  = 4,
179
180 };
181
182 /* setup mixer config, for which we need to consider all crtc's and
183  * the planes attached to them
184  *
185  * TODO may possibly need some extra locking here
186  */
187 static void setup_mixer(struct mdp4_kms *mdp4_kms)
188 {
189         struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
190         struct drm_crtc *crtc;
191         uint32_t mixer_cfg = 0;
192         static const enum mdp_mixer_stage_id stages[] = {
193                         STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
194         };
195
196         list_for_each_entry(crtc, &config->crtc_list, head) {
197                 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
198                 struct drm_plane *plane;
199
200                 drm_atomic_crtc_for_each_plane(plane, crtc) {
201                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
202                         int idx = idxs[pipe_id];
203                         mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
204                                         pipe_id, stages[idx]);
205                 }
206         }
207
208         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
209 }
210
211 static void blend_setup(struct drm_crtc *crtc)
212 {
213         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
214         struct mdp4_kms *mdp4_kms = get_kms(crtc);
215         struct drm_plane *plane;
216         int i, ovlp = mdp4_crtc->ovlp;
217         bool alpha[4]= { false, false, false, false };
218
219         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
220         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
221         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
222         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
223
224         drm_atomic_crtc_for_each_plane(plane, crtc) {
225                 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
226                 int idx = idxs[pipe_id];
227                 if (idx > 0) {
228                         const struct mdp_format *format =
229                                         to_mdp_format(msm_framebuffer_format(plane->fb));
230                         alpha[idx-1] = format->alpha_enable;
231                 }
232         }
233
234         for (i = 0; i < 4; i++) {
235                 uint32_t op;
236
237                 if (alpha[i]) {
238                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
239                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
240                                         MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
241                 } else {
242                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
243                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
244                 }
245
246                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
247                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
248                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
249                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
250                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
251                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
252                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
253                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
254         }
255
256         setup_mixer(mdp4_kms);
257 }
258
259 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
260 {
261         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
262         struct mdp4_kms *mdp4_kms = get_kms(crtc);
263         enum mdp4_dma dma = mdp4_crtc->dma;
264         int ovlp = mdp4_crtc->ovlp;
265         struct drm_display_mode *mode;
266
267         if (WARN_ON(!crtc->state))
268                 return;
269
270         mode = &crtc->state->adjusted_mode;
271
272         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
273                         mdp4_crtc->name, mode->base.id, mode->name,
274                         mode->vrefresh, mode->clock,
275                         mode->hdisplay, mode->hsync_start,
276                         mode->hsync_end, mode->htotal,
277                         mode->vdisplay, mode->vsync_start,
278                         mode->vsync_end, mode->vtotal,
279                         mode->type, mode->flags);
280
281         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
282                         MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
283                         MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
284
285         /* take data from pipe: */
286         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
287         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
288         mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
289                         MDP4_DMA_DST_SIZE_WIDTH(0) |
290                         MDP4_DMA_DST_SIZE_HEIGHT(0));
291
292         mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
293         mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
294                         MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
295                         MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
296         mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
297
298         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
299
300         if (dma == DMA_E) {
301                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
302                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
303                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
304         }
305 }
306
307 static void mdp4_crtc_prepare(struct drm_crtc *crtc)
308 {
309         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
310         DBG("%s", mdp4_crtc->name);
311         /* make sure we hold a ref to mdp clks while setting up mode: */
312         drm_crtc_vblank_get(crtc);
313         mdp4_enable(get_kms(crtc));
314         mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
315 }
316
317 static void mdp4_crtc_commit(struct drm_crtc *crtc)
318 {
319         mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
320         crtc_flush(crtc);
321         /* drop the ref to mdp clk's that we got in prepare: */
322         mdp4_disable(get_kms(crtc));
323         drm_crtc_vblank_put(crtc);
324 }
325
326 static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
327 {
328 }
329
330 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
331                 struct drm_crtc_state *state)
332 {
333         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
334         DBG("%s: check", mdp4_crtc->name);
335         // TODO anything else to check?
336         return 0;
337 }
338
339 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc)
340 {
341         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
342         DBG("%s: begin", mdp4_crtc->name);
343 }
344
345 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc)
346 {
347         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
348         struct drm_device *dev = crtc->dev;
349         unsigned long flags;
350
351         DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
352
353         WARN_ON(mdp4_crtc->event);
354
355         spin_lock_irqsave(&dev->event_lock, flags);
356         mdp4_crtc->event = crtc->state->event;
357         spin_unlock_irqrestore(&dev->event_lock, flags);
358
359         blend_setup(crtc);
360         crtc_flush(crtc);
361         request_pending(crtc, PENDING_FLIP);
362 }
363
364 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
365                 struct drm_property *property, uint64_t val)
366 {
367         // XXX
368         return -EINVAL;
369 }
370
371 #define CURSOR_WIDTH 64
372 #define CURSOR_HEIGHT 64
373
374 /* called from IRQ to update cursor related registers (if needed).  The
375  * cursor registers, other than x/y position, appear not to be double
376  * buffered, and changing them other than from vblank seems to trigger
377  * underflow.
378  */
379 static void update_cursor(struct drm_crtc *crtc)
380 {
381         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
382         struct mdp4_kms *mdp4_kms = get_kms(crtc);
383         enum mdp4_dma dma = mdp4_crtc->dma;
384         unsigned long flags;
385
386         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
387         if (mdp4_crtc->cursor.stale) {
388                 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
389                 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
390                 uint32_t iova = mdp4_crtc->cursor.next_iova;
391
392                 if (next_bo) {
393                         /* take a obj ref + iova ref when we start scanning out: */
394                         drm_gem_object_reference(next_bo);
395                         msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
396
397                         /* enable cursor: */
398                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
399                                         MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
400                                         MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
401                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
402                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
403                                         MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
404                                         MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
405                 } else {
406                         /* disable cursor: */
407                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
408                                         mdp4_kms->blank_cursor_iova);
409                 }
410
411                 /* and drop the iova ref + obj rev when done scanning out: */
412                 if (prev_bo)
413                         drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
414
415                 mdp4_crtc->cursor.scanout_bo = next_bo;
416                 mdp4_crtc->cursor.stale = false;
417         }
418
419         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
420                         MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
421                         MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
422
423         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
424 }
425
426 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
427                 struct drm_file *file_priv, uint32_t handle,
428                 uint32_t width, uint32_t height)
429 {
430         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
431         struct mdp4_kms *mdp4_kms = get_kms(crtc);
432         struct drm_device *dev = crtc->dev;
433         struct drm_gem_object *cursor_bo, *old_bo;
434         unsigned long flags;
435         uint32_t iova;
436         int ret;
437
438         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
439                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
440                 return -EINVAL;
441         }
442
443         if (handle) {
444                 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
445                 if (!cursor_bo)
446                         return -ENOENT;
447         } else {
448                 cursor_bo = NULL;
449         }
450
451         if (cursor_bo) {
452                 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
453                 if (ret)
454                         goto fail;
455         } else {
456                 iova = 0;
457         }
458
459         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
460         old_bo = mdp4_crtc->cursor.next_bo;
461         mdp4_crtc->cursor.next_bo   = cursor_bo;
462         mdp4_crtc->cursor.next_iova = iova;
463         mdp4_crtc->cursor.width     = width;
464         mdp4_crtc->cursor.height    = height;
465         mdp4_crtc->cursor.stale     = true;
466         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
467
468         if (old_bo) {
469                 /* drop our previous reference: */
470                 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
471         }
472
473         request_pending(crtc, PENDING_CURSOR);
474
475         return 0;
476
477 fail:
478         drm_gem_object_unreference_unlocked(cursor_bo);
479         return ret;
480 }
481
482 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
483 {
484         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
485         unsigned long flags;
486
487         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
488         mdp4_crtc->cursor.x = x;
489         mdp4_crtc->cursor.y = y;
490         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
491
492         crtc_flush(crtc);
493         request_pending(crtc, PENDING_CURSOR);
494
495         return 0;
496 }
497
498 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
499         .set_config = drm_atomic_helper_set_config,
500         .destroy = mdp4_crtc_destroy,
501         .page_flip = drm_atomic_helper_page_flip,
502         .set_property = mdp4_crtc_set_property,
503         .cursor_set = mdp4_crtc_cursor_set,
504         .cursor_move = mdp4_crtc_cursor_move,
505         .reset = drm_atomic_helper_crtc_reset,
506         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
507         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
508 };
509
510 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
511         .dpms = mdp4_crtc_dpms,
512         .mode_fixup = mdp4_crtc_mode_fixup,
513         .mode_set_nofb = mdp4_crtc_mode_set_nofb,
514         .mode_set = drm_helper_crtc_mode_set,
515         .mode_set_base = drm_helper_crtc_mode_set_base,
516         .prepare = mdp4_crtc_prepare,
517         .commit = mdp4_crtc_commit,
518         .load_lut = mdp4_crtc_load_lut,
519         .atomic_check = mdp4_crtc_atomic_check,
520         .atomic_begin = mdp4_crtc_atomic_begin,
521         .atomic_flush = mdp4_crtc_atomic_flush,
522 };
523
524 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
525 {
526         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
527         struct drm_crtc *crtc = &mdp4_crtc->base;
528         struct msm_drm_private *priv = crtc->dev->dev_private;
529         unsigned pending;
530
531         mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
532
533         pending = atomic_xchg(&mdp4_crtc->pending, 0);
534
535         if (pending & PENDING_FLIP) {
536                 complete_flip(crtc, NULL);
537         }
538
539         if (pending & PENDING_CURSOR) {
540                 update_cursor(crtc);
541                 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
542         }
543 }
544
545 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
546 {
547         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
548         struct drm_crtc *crtc = &mdp4_crtc->base;
549         DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
550         crtc_flush(crtc);
551 }
552
553 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
554 {
555         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
556         return mdp4_crtc->vblank.irqmask;
557 }
558
559 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
560 {
561         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
562         DBG("%s: cancel: %p", mdp4_crtc->name, file);
563         complete_flip(crtc, file);
564 }
565
566 /* set dma config, ie. the format the encoder wants. */
567 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
568 {
569         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
570         struct mdp4_kms *mdp4_kms = get_kms(crtc);
571
572         mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
573 }
574
575 /* set interface for routing crtc->encoder: */
576 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
577 {
578         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
579         struct mdp4_kms *mdp4_kms = get_kms(crtc);
580         uint32_t intf_sel;
581
582         intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
583
584         switch (mdp4_crtc->dma) {
585         case DMA_P:
586                 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
587                 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
588                 break;
589         case DMA_S:
590                 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
591                 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
592                 break;
593         case DMA_E:
594                 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
595                 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
596                 break;
597         }
598
599         if (intf == INTF_DSI_VIDEO) {
600                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
601                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
602         } else if (intf == INTF_DSI_CMD) {
603                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
604                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
605         }
606
607         mdp4_crtc->mixer = mixer;
608
609         blend_setup(crtc);
610
611         DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
612
613         mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
614 }
615
616 static const char *dma_names[] = {
617                 "DMA_P", "DMA_S", "DMA_E",
618 };
619
620 /* initialize crtc */
621 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
622                 struct drm_plane *plane, int id, int ovlp_id,
623                 enum mdp4_dma dma_id)
624 {
625         struct drm_crtc *crtc = NULL;
626         struct mdp4_crtc *mdp4_crtc;
627
628         mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
629         if (!mdp4_crtc)
630                 return ERR_PTR(-ENOMEM);
631
632         crtc = &mdp4_crtc->base;
633
634         mdp4_crtc->id = id;
635
636         mdp4_crtc->ovlp = ovlp_id;
637         mdp4_crtc->dma = dma_id;
638
639         mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
640         mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
641
642         mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
643         mdp4_crtc->err.irq = mdp4_crtc_err_irq;
644
645         snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
646                         dma_names[dma_id], ovlp_id);
647
648         spin_lock_init(&mdp4_crtc->cursor.lock);
649
650         drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
651                         "unref cursor", unref_cursor_worker);
652
653         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
654         drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
655         plane->crtc = crtc;
656
657         mdp4_plane_install_properties(plane, &crtc->base);
658
659         return crtc;
660 }