drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18
  19 #include "msm_drv.h"
  20 #include "msm_mmu.h"
  21 #include "mdp4_kms.h"
  22
  23 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  24
  25 static int mdp4_hw_init(struct msm_kms *kms)
  26 {
  27         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  28         struct drm_device *dev = mdp4_kms->dev;
  29         uint32_t version, major, minor, dmap_cfg, vg_cfg;
  30         unsigned long clk;
  31         int ret = 0;
  32
  33         pm_runtime_get_sync(dev->dev);
  34
  35         mdp4_enable(mdp4_kms);
  36         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  37         mdp4_disable(mdp4_kms);
  38
  39         major = FIELD(version, MDP4_VERSION_MAJOR);
  40         minor = FIELD(version, MDP4_VERSION_MINOR);
  41
  42         DBG("found MDP4 version v%d.%d", major, minor);
  43
  44         if (major != 4) {
  45                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  46                                 major, minor);
  47                 ret = -ENXIO;
  48                 goto out;
  49         }
  50
  51         mdp4_kms->rev = minor;
  52
  53         if (mdp4_kms->dsi_pll_vdda) {
  54                 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  55                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  56                                         1200000, 1200000);
  57                         if (ret) {
  58                                 dev_err(dev->dev,
  59                                         "failed to set dsi_pll_vdda voltage: %d\n", ret);
  60                                 goto out;
  61                         }
  62                 }
  63         }
  64
  65         if (mdp4_kms->dsi_pll_vddio) {
  66                 if (mdp4_kms->rev == 2) {
  67                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  68                                         1800000, 1800000);
  69                         if (ret) {
  70                                 dev_err(dev->dev,
  71                                         "failed to set dsi_pll_vddio voltage: %d\n", ret);
  72                                 goto out;
  73                         }
  74                 }
  75         }
  76
  77         if (mdp4_kms->rev > 1) {
  78                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  79                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  80         }
  81
  82         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  83
  84         /* max read pending cmd config, 3 pending requests: */
  85         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  86
  87         clk = clk_get_rate(mdp4_kms->clk);
  88
  89         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  90                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  91                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  92         } else {
  93                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  94                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  95         }
  96
  97         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  98
  99         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
 100         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
 101
 102         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
 103         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
 104         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
 105         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
 106
 107         if (mdp4_kms->rev >= 2)
 108                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
 109
 110         /* disable CSC matrix / YUV by default: */
 111         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
 112         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
 113         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
 114         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
 115         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
 116         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
 117
 118         if (mdp4_kms->rev > 1)
 119                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
 120
 121 out:
 122         pm_runtime_put_sync(dev->dev);
 123
 124         return ret;
 125 }
 126
 127 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 128                 struct drm_encoder *encoder)
 129 {
 130         /* if we had >1 encoder, we'd need something more clever: */
 131         return mdp4_dtv_round_pixclk(encoder, rate);
 132 }
 133
 134 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 135 {
 136         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 137         struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
 138         unsigned i;
 139
 140         for (i = 0; i < priv->num_crtcs; i++)
 141                 mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file);
 142 }
 143
 144 static void mdp4_destroy(struct msm_kms *kms)
 145 {
 146         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 147         if (mdp4_kms->blank_cursor_iova)
 148                 msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
 149         if (mdp4_kms->blank_cursor_bo)
 150                 drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
 151         kfree(mdp4_kms);
 152 }
 153
 154 static const struct mdp_kms_funcs kms_funcs = {
 155         .base = {
 156                 .hw_init         = mdp4_hw_init,
 157                 .irq_preinstall  = mdp4_irq_preinstall,
 158                 .irq_postinstall = mdp4_irq_postinstall,
 159                 .irq_uninstall   = mdp4_irq_uninstall,
 160                 .irq             = mdp4_irq,
 161                 .enable_vblank   = mdp4_enable_vblank,
 162                 .disable_vblank  = mdp4_disable_vblank,
 163                 .get_format      = mdp_get_format,
 164                 .round_pixclk    = mdp4_round_pixclk,
 165                 .preclose        = mdp4_preclose,
 166                 .destroy         = mdp4_destroy,
 167         },
 168         .set_irqmask         = mdp4_set_irqmask,
 169 };
 170
 171 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 172 {
 173         DBG("");
 174
 175         clk_disable_unprepare(mdp4_kms->clk);
 176         if (mdp4_kms->pclk)
 177                 clk_disable_unprepare(mdp4_kms->pclk);
 178         clk_disable_unprepare(mdp4_kms->lut_clk);
 179         if (mdp4_kms->axi_clk)
 180                 clk_disable_unprepare(mdp4_kms->axi_clk);
 181
 182         return 0;
 183 }
 184
 185 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 186 {
 187         DBG("");
 188
 189         clk_prepare_enable(mdp4_kms->clk);
 190         if (mdp4_kms->pclk)
 191                 clk_prepare_enable(mdp4_kms->pclk);
 192         clk_prepare_enable(mdp4_kms->lut_clk);
 193         if (mdp4_kms->axi_clk)
 194                 clk_prepare_enable(mdp4_kms->axi_clk);
 195
 196         return 0;
 197 }
 198
 199 static int modeset_init(struct mdp4_kms *mdp4_kms)
 200 {
 201         struct drm_device *dev = mdp4_kms->dev;
 202         struct msm_drm_private *priv = dev->dev_private;
 203         struct drm_plane *plane;
 204         struct drm_crtc *crtc;
 205         struct drm_encoder *encoder;
 206         struct hdmi *hdmi;
 207         int ret;
 208
 209         /*
 210          *  NOTE: this is a bit simplistic until we add support
 211          * for more than just RGB1->DMA_E->DTV->HDMI
 212          */
 213
 214         /* construct non-private planes: */
 215         plane = mdp4_plane_init(dev, VG1, false);
 216         if (IS_ERR(plane)) {
 217                 dev_err(dev->dev, "failed to construct plane for VG1\n");
 218                 ret = PTR_ERR(plane);
 219                 goto fail;
 220         }
 221         priv->planes[priv->num_planes++] = plane;
 222
 223         plane = mdp4_plane_init(dev, VG2, false);
 224         if (IS_ERR(plane)) {
 225                 dev_err(dev->dev, "failed to construct plane for VG2\n");
 226                 ret = PTR_ERR(plane);
 227                 goto fail;
 228         }
 229         priv->planes[priv->num_planes++] = plane;
 230
 231         /* the CRTCs get constructed with a private plane: */
 232         plane = mdp4_plane_init(dev, RGB1, true);
 233         if (IS_ERR(plane)) {
 234                 dev_err(dev->dev, "failed to construct plane for RGB1\n");
 235                 ret = PTR_ERR(plane);
 236                 goto fail;
 237         }
 238
 239         crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
 240         if (IS_ERR(crtc)) {
 241                 dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
 242                 ret = PTR_ERR(crtc);
 243                 goto fail;
 244         }
 245         priv->crtcs[priv->num_crtcs++] = crtc;
 246
 247         encoder = mdp4_dtv_encoder_init(dev);
 248         if (IS_ERR(encoder)) {
 249                 dev_err(dev->dev, "failed to construct DTV encoder\n");
 250                 ret = PTR_ERR(encoder);
 251                 goto fail;
 252         }
 253         encoder->possible_crtcs = 0x1;     /* DTV can be hooked to DMA_E */
 254         priv->encoders[priv->num_encoders++] = encoder;
 255
 256         hdmi = hdmi_init(dev, encoder);
 257         if (IS_ERR(hdmi)) {
 258                 ret = PTR_ERR(hdmi);
 259                 dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
 260                 goto fail;
 261         }
 262
 263         return 0;
 264
 265 fail:
 266         return ret;
 267 }
 268
 269 static const char *iommu_ports[] = {
 270                 "mdp_port0_cb0", "mdp_port1_cb0",
 271 };
 272
 273 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 274 {
 275         struct platform_device *pdev = dev->platformdev;
 276         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 277         struct mdp4_kms *mdp4_kms;
 278         struct msm_kms *kms = NULL;
 279         struct msm_mmu *mmu;
 280         int ret;
 281
 282         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 283         if (!mdp4_kms) {
 284                 dev_err(dev->dev, "failed to allocate kms\n");
 285                 ret = -ENOMEM;
 286                 goto fail;
 287         }
 288
 289         mdp_kms_init(&mdp4_kms->base, &kms_funcs);
 290
 291         kms = &mdp4_kms->base.base;
 292
 293         mdp4_kms->dev = dev;
 294
 295         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 296         if (IS_ERR(mdp4_kms->mmio)) {
 297                 ret = PTR_ERR(mdp4_kms->mmio);
 298                 goto fail;
 299         }
 300
 301         mdp4_kms->dsi_pll_vdda =
 302                         devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda");
 303         if (IS_ERR(mdp4_kms->dsi_pll_vdda))
 304                 mdp4_kms->dsi_pll_vdda = NULL;
 305
 306         mdp4_kms->dsi_pll_vddio =
 307                         devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio");
 308         if (IS_ERR(mdp4_kms->dsi_pll_vddio))
 309                 mdp4_kms->dsi_pll_vddio = NULL;
 310
 311         mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
 312         if (IS_ERR(mdp4_kms->vdd))
 313                 mdp4_kms->vdd = NULL;
 314
 315         if (mdp4_kms->vdd) {
 316                 ret = regulator_enable(mdp4_kms->vdd);
 317                 if (ret) {
 318                         dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 319                         goto fail;
 320                 }
 321         }
 322
 323         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 324         if (IS_ERR(mdp4_kms->clk)) {
 325                 dev_err(dev->dev, "failed to get core_clk\n");
 326                 ret = PTR_ERR(mdp4_kms->clk);
 327                 goto fail;
 328         }
 329
 330         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 331         if (IS_ERR(mdp4_kms->pclk))
 332                 mdp4_kms->pclk = NULL;
 333
 334         // XXX if (rev >= MDP_REV_42) { ???
 335         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 336         if (IS_ERR(mdp4_kms->lut_clk)) {
 337                 dev_err(dev->dev, "failed to get lut_clk\n");
 338                 ret = PTR_ERR(mdp4_kms->lut_clk);
 339                 goto fail;
 340         }
 341
 342         mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk");
 343         if (IS_ERR(mdp4_kms->axi_clk)) {
 344                 dev_err(dev->dev, "failed to get axi_clk\n");
 345                 ret = PTR_ERR(mdp4_kms->axi_clk);
 346                 goto fail;
 347         }
 348
 349         clk_set_rate(mdp4_kms->clk, config->max_clk);
 350         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 351
 352         /* make sure things are off before attaching iommu (bootloader could
 353          * have left things on, in which case we'll start getting faults if
 354          * we don't disable):
 355          */
 356         mdp4_enable(mdp4_kms);
 357         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 358         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 359         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 360         mdp4_disable(mdp4_kms);
 361         mdelay(16);
 362
 363         if (config->iommu) {
 364                 mmu = msm_iommu_new(&pdev->dev, config->iommu);
 365                 if (IS_ERR(mmu)) {
 366                         ret = PTR_ERR(mmu);
 367                         goto fail;
 368                 }
 369                 ret = mmu->funcs->attach(mmu, iommu_ports,
 370                                 ARRAY_SIZE(iommu_ports));
 371                 if (ret)
 372                         goto fail;
 373         } else {
 374                 dev_info(dev->dev, "no iommu, fallback to phys "
 375                                 "contig buffers for scanout\n");
 376                 mmu = NULL;
 377         }
 378
 379         mdp4_kms->id = msm_register_mmu(dev, mmu);
 380         if (mdp4_kms->id < 0) {
 381                 ret = mdp4_kms->id;
 382                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
 383                 goto fail;
 384         }
 385
 386         ret = modeset_init(mdp4_kms);
 387         if (ret) {
 388                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 389                 goto fail;
 390         }
 391
 392         mutex_lock(&dev->struct_mutex);
 393         mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
 394         mutex_unlock(&dev->struct_mutex);
 395         if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
 396                 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
 397                 dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
 398                 mdp4_kms->blank_cursor_bo = NULL;
 399                 goto fail;
 400         }
 401
 402         ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
 403                         &mdp4_kms->blank_cursor_iova);
 404         if (ret) {
 405                 dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
 406                 goto fail;
 407         }
 408
 409         return kms;
 410
 411 fail:
 412         if (kms)
 413                 mdp4_destroy(kms);
 414         return ERR_PTR(ret);
 415 }
 416
 417 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 418 {
 419         static struct mdp4_platform_config config = {};
 420 #ifdef CONFIG_OF
 421         /* TODO */
 422         config.max_clk = 266667000;
 423         config.iommu = iommu_domain_alloc(&platform_bus_type);
 424 #else
 425         if (cpu_is_apq8064())
 426                 config.max_clk = 266667000;
 427         else
 428                 config.max_clk = 200000000;
 429
 430         config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
 431 #endif
 432         return &config;
 433 }