drivers/gpu/drm/nouveau/core/engine/disp/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 #include <nvif/class.h>
  29
  30 #include "nv50.h"
  31
  32 /*******************************************************************************
  33  * EVO master channel object
  34  ******************************************************************************/
  35
  36 static const struct nv50_disp_mthd_list
  37 nve0_disp_mast_mthd_head = {
  38         .mthd = 0x0300,
  39         .addr = 0x000300,
  40         .data = {
  41                 { 0x0400, 0x660400 },
  42                 { 0x0404, 0x660404 },
  43                 { 0x0408, 0x660408 },
  44                 { 0x040c, 0x66040c },
  45                 { 0x0410, 0x660410 },
  46                 { 0x0414, 0x660414 },
  47                 { 0x0418, 0x660418 },
  48                 { 0x041c, 0x66041c },
  49                 { 0x0420, 0x660420 },
  50                 { 0x0424, 0x660424 },
  51                 { 0x0428, 0x660428 },
  52                 { 0x042c, 0x66042c },
  53                 { 0x0430, 0x660430 },
  54                 { 0x0434, 0x660434 },
  55                 { 0x0438, 0x660438 },
  56                 { 0x0440, 0x660440 },
  57                 { 0x0444, 0x660444 },
  58                 { 0x0448, 0x660448 },
  59                 { 0x044c, 0x66044c },
  60                 { 0x0450, 0x660450 },
  61                 { 0x0454, 0x660454 },
  62                 { 0x0458, 0x660458 },
  63                 { 0x045c, 0x66045c },
  64                 { 0x0460, 0x660460 },
  65                 { 0x0468, 0x660468 },
  66                 { 0x046c, 0x66046c },
  67                 { 0x0470, 0x660470 },
  68                 { 0x0474, 0x660474 },
  69                 { 0x047c, 0x66047c },
  70                 { 0x0480, 0x660480 },
  71                 { 0x0484, 0x660484 },
  72                 { 0x0488, 0x660488 },
  73                 { 0x048c, 0x66048c },
  74                 { 0x0490, 0x660490 },
  75                 { 0x0494, 0x660494 },
  76                 { 0x0498, 0x660498 },
  77                 { 0x04a0, 0x6604a0 },
  78                 { 0x04b0, 0x6604b0 },
  79                 { 0x04b8, 0x6604b8 },
  80                 { 0x04bc, 0x6604bc },
  81                 { 0x04c0, 0x6604c0 },
  82                 { 0x04c4, 0x6604c4 },
  83                 { 0x04c8, 0x6604c8 },
  84                 { 0x04d0, 0x6604d0 },
  85                 { 0x04d4, 0x6604d4 },
  86                 { 0x04e0, 0x6604e0 },
  87                 { 0x04e4, 0x6604e4 },
  88                 { 0x04e8, 0x6604e8 },
  89                 { 0x04ec, 0x6604ec },
  90                 { 0x04f0, 0x6604f0 },
  91                 { 0x04f4, 0x6604f4 },
  92                 { 0x04f8, 0x6604f8 },
  93                 { 0x04fc, 0x6604fc },
  94                 { 0x0500, 0x660500 },
  95                 { 0x0504, 0x660504 },
  96                 { 0x0508, 0x660508 },
  97                 { 0x050c, 0x66050c },
  98                 { 0x0510, 0x660510 },
  99                 { 0x0514, 0x660514 },
 100                 { 0x0518, 0x660518 },
 101                 { 0x051c, 0x66051c },
 102                 { 0x0520, 0x660520 },
 103                 { 0x0524, 0x660524 },
 104                 { 0x052c, 0x66052c },
 105                 { 0x0530, 0x660530 },
 106                 { 0x054c, 0x66054c },
 107                 { 0x0550, 0x660550 },
 108                 { 0x0554, 0x660554 },
 109                 { 0x0558, 0x660558 },
 110                 { 0x055c, 0x66055c },
 111                 {}
 112         }
 113 };
 114
 115 const struct nv50_disp_mthd_chan
 116 nve0_disp_mast_mthd_chan = {
 117         .name = "Core",
 118         .addr = 0x000000,
 119         .data = {
 120                 { "Global", 1, &nvd0_disp_mast_mthd_base },
 121                 {    "DAC", 3, &nvd0_disp_mast_mthd_dac  },
 122                 {    "SOR", 8, &nvd0_disp_mast_mthd_sor  },
 123                 {   "PIOR", 4, &nvd0_disp_mast_mthd_pior },
 124                 {   "HEAD", 4, &nve0_disp_mast_mthd_head },
 125                 {}
 126         }
 127 };
 128
 129 /*******************************************************************************
 130  * EVO overlay channel objects
 131  ******************************************************************************/
 132
 133 static const struct nv50_disp_mthd_list
 134 nve0_disp_ovly_mthd_base = {
 135         .mthd = 0x0000,
 136         .data = {
 137                 { 0x0080, 0x665080 },
 138                 { 0x0084, 0x665084 },
 139                 { 0x0088, 0x665088 },
 140                 { 0x008c, 0x66508c },
 141                 { 0x0090, 0x665090 },
 142                 { 0x0094, 0x665094 },
 143                 { 0x00a0, 0x6650a0 },
 144                 { 0x00a4, 0x6650a4 },
 145                 { 0x00b0, 0x6650b0 },
 146                 { 0x00b4, 0x6650b4 },
 147                 { 0x00b8, 0x6650b8 },
 148                 { 0x00c0, 0x6650c0 },
 149                 { 0x00c4, 0x6650c4 },
 150                 { 0x00e0, 0x6650e0 },
 151                 { 0x00e4, 0x6650e4 },
 152                 { 0x00e8, 0x6650e8 },
 153                 { 0x0100, 0x665100 },
 154                 { 0x0104, 0x665104 },
 155                 { 0x0108, 0x665108 },
 156                 { 0x010c, 0x66510c },
 157                 { 0x0110, 0x665110 },
 158                 { 0x0118, 0x665118 },
 159                 { 0x011c, 0x66511c },
 160                 { 0x0120, 0x665120 },
 161                 { 0x0124, 0x665124 },
 162                 { 0x0130, 0x665130 },
 163                 { 0x0134, 0x665134 },
 164                 { 0x0138, 0x665138 },
 165                 { 0x013c, 0x66513c },
 166                 { 0x0140, 0x665140 },
 167                 { 0x0144, 0x665144 },
 168                 { 0x0148, 0x665148 },
 169                 { 0x014c, 0x66514c },
 170                 { 0x0150, 0x665150 },
 171                 { 0x0154, 0x665154 },
 172                 { 0x0158, 0x665158 },
 173                 { 0x015c, 0x66515c },
 174                 { 0x0160, 0x665160 },
 175                 { 0x0164, 0x665164 },
 176                 { 0x0168, 0x665168 },
 177                 { 0x016c, 0x66516c },
 178                 { 0x0400, 0x665400 },
 179                 { 0x0404, 0x665404 },
 180                 { 0x0408, 0x665408 },
 181                 { 0x040c, 0x66540c },
 182                 { 0x0410, 0x665410 },
 183                 {}
 184         }
 185 };
 186
 187 const struct nv50_disp_mthd_chan
 188 nve0_disp_ovly_mthd_chan = {
 189         .name = "Overlay",
 190         .addr = 0x001000,
 191         .data = {
 192                 { "Global", 1, &nve0_disp_ovly_mthd_base },
 193                 {}
 194         }
 195 };
 196
 197 /*******************************************************************************
 198  * Base display object
 199  ******************************************************************************/
 200
 201 static struct nouveau_oclass
 202 nve0_disp_sclass[] = {
 203         { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
 204         { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
 205         { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
 206         { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
 207         { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
 208         {}
 209 };
 210
 211 static struct nouveau_oclass
 212 nve0_disp_base_oclass[] = {
 213         { GK104_DISP, &nvd0_disp_base_ofuncs },
 214         {}
 215 };
 216
 217 /*******************************************************************************
 218  * Display engine implementation
 219  ******************************************************************************/
 220
 221 static int
 222 nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 223                struct nouveau_oclass *oclass, void *data, u32 size,
 224                struct nouveau_object **pobject)
 225 {
 226         struct nv50_disp_priv *priv;
 227         int heads = nv_rd32(parent, 0x022448);
 228         int ret;
 229
 230         ret = nouveau_disp_create(parent, engine, oclass, heads,
 231                                   "PDISP", "display", &priv);
 232         *pobject = nv_object(priv);
 233         if (ret)
 234                 return ret;
 235
 236         ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
 237         if (ret)
 238                 return ret;
 239
 240         nv_engine(priv)->sclass = nve0_disp_base_oclass;
 241         nv_engine(priv)->cclass = &nv50_disp_cclass;
 242         nv_subdev(priv)->intr = nvd0_disp_intr;
 243         INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
 244         priv->sclass = nve0_disp_sclass;
 245         priv->head.nr = heads;
 246         priv->dac.nr = 3;
 247         priv->sor.nr = 4;
 248         priv->dac.power = nv50_dac_power;
 249         priv->dac.sense = nv50_dac_sense;
 250         priv->sor.power = nv50_sor_power;
 251         priv->sor.hda_eld = nvd0_hda_eld;
 252         priv->sor.hdmi = nve0_hdmi_ctrl;
 253         return 0;
 254 }
 255
 256 struct nouveau_oclass *
 257 nve0_disp_oclass = &(struct nv50_disp_impl) {
 258         .base.base.handle = NV_ENGINE(DISP, 0x91),
 259         .base.base.ofuncs = &(struct nouveau_ofuncs) {
 260                 .ctor = nve0_disp_ctor,
 261                 .dtor = _nouveau_disp_dtor,
 262                 .init = _nouveau_disp_init,
 263                 .fini = _nouveau_disp_fini,
 264         },
 265         .base.vblank = &nvd0_disp_vblank_func,
 266         .base.outp =  nvd0_disp_outp_sclass,
 267         .mthd.core = &nve0_disp_mast_mthd_chan,
 268         .mthd.base = &nvd0_disp_sync_mthd_chan,
 269         .mthd.ovly = &nve0_disp_ovly_mthd_chan,
 270         .mthd.prev = -0x020000,
 271         .head.scanoutpos = nvd0_disp_base_scanoutpos,
 272 }.base.base;