2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
33 #define NV_PGRAPH_FECS_INTR_ACK 0x409004
34 #define NV_PGRAPH_FECS_INTR 0x409008
35 #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400
36 #define NV_PGRAPH_FECS_INTR_CHSW 0x00000100
37 #define NV_PGRAPH_FECS_INTR_FIFO 0x00000004
38 #define NV_PGRAPH_FECS_INTR_MODE 0x40900c
39 #define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004
40 #define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004
41 #define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000
42 #define NV_PGRAPH_FECS_INTR_EN_SET 0x409010
43 #define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004
44 #define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c
45 #define NV_PGRAPH_FECS_ACCESS 0x409048
46 #define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002
47 #define NV_PGRAPH_FECS_FIFO_DATA 0x409064
48 #define NV_PGRAPH_FECS_FIFO_CMD 0x409068
49 #define NV_PGRAPH_FECS_FIFO_ACK 0x409074
50 #define NV_PGRAPH_FECS_CAPS 0x409108
51 #define NV_PGRAPH_FECS_SIGNAL 0x409400
52 #define NV_PGRAPH_FECS_IROUTE 0x409404
53 #define NV_PGRAPH_FECS_BAR_MASK0 0x40940c
54 #define NV_PGRAPH_FECS_BAR_MASK1 0x409410
55 #define NV_PGRAPH_FECS_BAR 0x409414
56 #define NV_PGRAPH_FECS_BAR_SET 0x409418
57 #define NV_PGRAPH_FECS_RED_SWITCH 0x409614
58 #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400
59 #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200
60 #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100
61 #define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040
62 #define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020
63 #define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010
64 #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002
65 #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001
66 #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
67 #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
68 #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
69 #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700
70 #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704
71 #define NV_PGRAPH_FECS_MMCTX_BASE 0x409710
72 #define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714
73 #define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718
74 #define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c
75 #define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720
76 #define NV_PGRAPH_FECS_MMIO_CTRL 0x409728
77 #define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c
78 #define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730
79 #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
81 #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
82 #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820)
83 #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
84 #define NV_PGRAPH_FECS_UNK86C 0x40986c
86 #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800)
87 #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840)
88 #define NV_PGRAPH_FECS_UNK86C 0x40988c
89 #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0)
91 #define NV_PGRAPH_FECS_STRANDS_CNT 0x409880
92 #define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908
93 #define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c
94 #define NV_PGRAPH_FECS_STRAND_WORDS 0x409910
95 #define NV_PGRAPH_FECS_STRAND_DATA 0x409918
96 #define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c
97 #define NV_PGRAPH_FECS_STRAND_CMD 0x409928
98 #define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001
99 #define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002
100 #define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003
101 #define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004
102 #define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a
103 #define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b
104 #define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c
105 #define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d
106 #define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c
107 #define NV_PGRAPH_FECS_MEM_BASE 0x409a04
108 #define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c
109 #define NV_PGRAPH_FECS_MEM_CMD 0x409a10
110 #define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007
111 #define NV_PGRAPH_FECS_MEM_TARGET 0x409a20
112 #define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000
113 #define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f
114 #define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001
115 #define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002
116 #define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00
117 #define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04
118 #define NV_PGRAPH_FECS_CHSW 0x409b0c
119 #define NV_PGRAPH_FECS_CHSW_ACK 0x00000001
120 #define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c
121 #define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24
123 #define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004
124 #define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008
125 #define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004
126 #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010
127 #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004
128 #define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c
129 #define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048
130 #define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002
131 #define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064
132 #define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068
133 #define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074
134 #define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608
135 #define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108
136 #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614
137 #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800
138 #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200
139 #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020
140 #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002
141 #define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618
142 #define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700
143 #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704
144 #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c
146 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
147 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820)
148 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
149 #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c
151 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
152 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840)
153 #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c
154 #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0)
156 #define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c
157 #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928
158 #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003
159 #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004
160 #define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04
162 #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
163 #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
177 #define imm32(reg,val) /*
178 */ movw reg ((val) & 0x0000ffff) /*
179 */ sethi reg ((val) & 0xffff0000)
181 #define imm32(reg,val) /*
185 #define nv_mkio(rv,r,i) /*
186 */ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2))
191 #define call(a) call fn(hash)a
193 #define call(a) lcall fn(hash)a
196 #define nv_iord(rv,r,i) /*
197 */ nv_mkio(rv,r,i) /*
200 #define nv_iowr(r,i,rv) /*
201 */ nv_mkio($r0,r,i) /*
205 #define nv_rd32(reg,addr) /*
206 */ imm32($r14, addr) /*
210 #define nv_wr32(addr,reg) /*
211 */ mov b32 $r15 reg /*
212 */ imm32($r14, addr) /*
215 #define trace_set(bit) /*
218 */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
220 #define trace_clr(bit) /*
223 */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9)