drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31
  32 #include <nvif/class.h>
  33
  34 #include "nouveau_drm.h"
  35 #include "nouveau_dma.h"
  36 #include "nouveau_gem.h"
  37 #include "nouveau_connector.h"
  38 #include "nouveau_encoder.h"
  39 #include "nouveau_crtc.h"
  40 #include "nouveau_fence.h"
  41 #include "nv50_display.h"
  42
  43 #define EVO_DMA_NR 9
  44
  45 #define EVO_MASTER  (0x00)
  46 #define EVO_FLIP(c) (0x01 + (c))
  47 #define EVO_OVLY(c) (0x05 + (c))
  48 #define EVO_OIMM(c) (0x09 + (c))
  49 #define EVO_CURS(c) (0x0d + (c))
  50
  51 /* offsets in shared sync bo of various structures */
  52 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  53 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  54 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  55 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  56
  57 /******************************************************************************
  58  * EVO channel
  59  *****************************************************************************/
  60
  61 struct nv50_chan {
  62         struct nvif_object user;
  63 };
  64
  65 static int
  66 nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
  67                  void *data, u32 size, struct nv50_chan *chan)
  68 {
  69         const u32 handle = (oclass[0] << 16) | head;
  70         u32 sclass[8];
  71         int ret, i;
  72
  73         ret = nvif_object_sclass(disp, sclass, ARRAY_SIZE(sclass));
  74         WARN_ON(ret > ARRAY_SIZE(sclass));
  75         if (ret < 0)
  76                 return ret;
  77
  78         while (oclass[0]) {
  79                 for (i = 0; i < ARRAY_SIZE(sclass); i++) {
  80                         if (sclass[i] == oclass[0]) {
  81                                 ret = nvif_object_init(disp, NULL, handle,
  82                                                        oclass[0], data, size,
  83                                                        &chan->user);
  84                                 if (ret == 0)
  85                                         nvif_object_map(&chan->user);
  86                                 return ret;
  87                         }
  88                 }
  89                 oclass++;
  90         }
  91
  92         return -ENOSYS;
  93 }
  94
  95 static void
  96 nv50_chan_destroy(struct nv50_chan *chan)
  97 {
  98         nvif_object_fini(&chan->user);
  99 }
 100
 101 /******************************************************************************
 102  * PIO EVO channel
 103  *****************************************************************************/
 104
 105 struct nv50_pioc {
 106         struct nv50_chan base;
 107 };
 108
 109 static void
 110 nv50_pioc_destroy(struct nv50_pioc *pioc)
 111 {
 112         nv50_chan_destroy(&pioc->base);
 113 }
 114
 115 static int
 116 nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
 117                  void *data, u32 size, struct nv50_pioc *pioc)
 118 {
 119         return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
 120 }
 121
 122 /******************************************************************************
 123  * Cursor Immediate
 124  *****************************************************************************/
 125
 126 struct nv50_curs {
 127         struct nv50_pioc base;
 128         struct nouveau_bo *image;
 129 };
 130
 131 static int
 132 nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
 133 {
 134         struct nv50_disp_cursor_v0 args = {
 135                 .head = head,
 136         };
 137         static const u32 oclass[] = {
 138                 GK104_DISP_CURSOR,
 139                 GF110_DISP_CURSOR,
 140                 GT214_DISP_CURSOR,
 141                 G82_DISP_CURSOR,
 142                 NV50_DISP_CURSOR,
 143                 0
 144         };
 145
 146         return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
 147                                &curs->base);
 148 }
 149
 150 /******************************************************************************
 151  * Overlay Immediate
 152  *****************************************************************************/
 153
 154 struct nv50_oimm {
 155         struct nv50_pioc base;
 156 };
 157
 158 static int
 159 nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
 160 {
 161         struct nv50_disp_cursor_v0 args = {
 162                 .head = head,
 163         };
 164         static const u32 oclass[] = {
 165                 GK104_DISP_OVERLAY,
 166                 GF110_DISP_OVERLAY,
 167                 GT214_DISP_OVERLAY,
 168                 G82_DISP_OVERLAY,
 169                 NV50_DISP_OVERLAY,
 170                 0
 171         };
 172
 173         return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
 174                                &oimm->base);
 175 }
 176
 177 /******************************************************************************
 178  * DMA EVO channel
 179  *****************************************************************************/
 180
 181 struct nv50_dmac {
 182         struct nv50_chan base;
 183         dma_addr_t handle;
 184         u32 *ptr;
 185
 186         struct nvif_object sync;
 187         struct nvif_object vram;
 188
 189         /* Protects against concurrent pushbuf access to this channel, lock is
 190          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 191          * dropped again by evo_kick. */
 192         struct mutex lock;
 193 };
 194
 195 static void
 196 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 197 {
 198         nvif_object_fini(&dmac->vram);
 199         nvif_object_fini(&dmac->sync);
 200
 201         nv50_chan_destroy(&dmac->base);
 202
 203         if (dmac->ptr) {
 204                 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
 205                 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 206         }
 207 }
 208
 209 static int
 210 nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
 211                  void *data, u32 size, u64 syncbuf,
 212                  struct nv50_dmac *dmac)
 213 {
 214         struct nvif_device *device = nvif_device(disp);
 215         struct nv50_disp_core_channel_dma_v0 *args = data;
 216         struct nvif_object pushbuf;
 217         int ret;
 218
 219         mutex_init(&dmac->lock);
 220
 221         dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
 222                                          PAGE_SIZE, &dmac->handle);
 223         if (!dmac->ptr)
 224                 return -ENOMEM;
 225
 226         ret = nvif_object_init(nvif_object(device), NULL,
 227                                args->pushbuf, NV_DMA_FROM_MEMORY,
 228                                &(struct nv_dma_v0) {
 229                                         .target = NV_DMA_V0_TARGET_PCI_US,
 230                                         .access = NV_DMA_V0_ACCESS_RD,
 231                                         .start = dmac->handle + 0x0000,
 232                                         .limit = dmac->handle + 0x0fff,
 233                                }, sizeof(struct nv_dma_v0), &pushbuf);
 234         if (ret)
 235                 return ret;
 236
 237         ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
 238         nvif_object_fini(&pushbuf);
 239         if (ret)
 240                 return ret;
 241
 242         ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
 243                                NV_DMA_IN_MEMORY,
 244                                &(struct nv_dma_v0) {
 245                                         .target = NV_DMA_V0_TARGET_VRAM,
 246                                         .access = NV_DMA_V0_ACCESS_RDWR,
 247                                         .start = syncbuf + 0x0000,
 248                                         .limit = syncbuf + 0x0fff,
 249                                }, sizeof(struct nv_dma_v0),
 250                                &dmac->sync);
 251         if (ret)
 252                 return ret;
 253
 254         ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
 255                                NV_DMA_IN_MEMORY,
 256                                &(struct nv_dma_v0) {
 257                                         .target = NV_DMA_V0_TARGET_VRAM,
 258                                         .access = NV_DMA_V0_ACCESS_RDWR,
 259                                         .start = 0,
 260                                         .limit = device->info.ram_user - 1,
 261                                }, sizeof(struct nv_dma_v0),
 262                                &dmac->vram);
 263         if (ret)
 264                 return ret;
 265
 266         return ret;
 267 }
 268
 269 /******************************************************************************
 270  * Core
 271  *****************************************************************************/
 272
 273 struct nv50_mast {
 274         struct nv50_dmac base;
 275 };
 276
 277 static int
 278 nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
 279 {
 280         struct nv50_disp_core_channel_dma_v0 args = {
 281                 .pushbuf = 0xb0007d00,
 282         };
 283         static const u32 oclass[] = {
 284                 GM204_DISP_CORE_CHANNEL_DMA,
 285                 GM107_DISP_CORE_CHANNEL_DMA,
 286                 GK110_DISP_CORE_CHANNEL_DMA,
 287                 GK104_DISP_CORE_CHANNEL_DMA,
 288                 GF110_DISP_CORE_CHANNEL_DMA,
 289                 GT214_DISP_CORE_CHANNEL_DMA,
 290                 GT206_DISP_CORE_CHANNEL_DMA,
 291                 GT200_DISP_CORE_CHANNEL_DMA,
 292                 G82_DISP_CORE_CHANNEL_DMA,
 293                 NV50_DISP_CORE_CHANNEL_DMA,
 294                 0
 295         };
 296
 297         return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
 298                                &core->base);
 299 }
 300
 301 /******************************************************************************
 302  * Base
 303  *****************************************************************************/
 304
 305 struct nv50_sync {
 306         struct nv50_dmac base;
 307         u32 addr;
 308         u32 data;
 309 };
 310
 311 static int
 312 nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
 313                  struct nv50_sync *base)
 314 {
 315         struct nv50_disp_base_channel_dma_v0 args = {
 316                 .pushbuf = 0xb0007c00 | head,
 317                 .head = head,
 318         };
 319         static const u32 oclass[] = {
 320                 GK110_DISP_BASE_CHANNEL_DMA,
 321                 GK104_DISP_BASE_CHANNEL_DMA,
 322                 GF110_DISP_BASE_CHANNEL_DMA,
 323                 GT214_DISP_BASE_CHANNEL_DMA,
 324                 GT200_DISP_BASE_CHANNEL_DMA,
 325                 G82_DISP_BASE_CHANNEL_DMA,
 326                 NV50_DISP_BASE_CHANNEL_DMA,
 327                 0
 328         };
 329
 330         return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
 331                                 syncbuf, &base->base);
 332 }
 333
 334 /******************************************************************************
 335  * Overlay
 336  *****************************************************************************/
 337
 338 struct nv50_ovly {
 339         struct nv50_dmac base;
 340 };
 341
 342 static int
 343 nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
 344                  struct nv50_ovly *ovly)
 345 {
 346         struct nv50_disp_overlay_channel_dma_v0 args = {
 347                 .pushbuf = 0xb0007e00 | head,
 348                 .head = head,
 349         };
 350         static const u32 oclass[] = {
 351                 GK104_DISP_OVERLAY_CONTROL_DMA,
 352                 GF110_DISP_OVERLAY_CONTROL_DMA,
 353                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 354                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 355                 G82_DISP_OVERLAY_CHANNEL_DMA,
 356                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 357                 0
 358         };
 359
 360         return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
 361                                 syncbuf, &ovly->base);
 362 }
 363
 364 struct nv50_head {
 365         struct nouveau_crtc base;
 366         struct nouveau_bo *image;
 367         struct nv50_curs curs;
 368         struct nv50_sync sync;
 369         struct nv50_ovly ovly;
 370         struct nv50_oimm oimm;
 371 };
 372
 373 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 374 #define nv50_curs(c) (&nv50_head(c)->curs)
 375 #define nv50_sync(c) (&nv50_head(c)->sync)
 376 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 377 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 378 #define nv50_chan(c) (&(c)->base.base)
 379 #define nv50_vers(c) nv50_chan(c)->user.oclass
 380
 381 struct nv50_fbdma {
 382         struct list_head head;
 383         struct nvif_object core;
 384         struct nvif_object base[4];
 385 };
 386
 387 struct nv50_disp {
 388         struct nvif_object *disp;
 389         struct nv50_mast mast;
 390
 391         struct list_head fbdma;
 392
 393         struct nouveau_bo *sync;
 394 };
 395
 396 static struct nv50_disp *
 397 nv50_disp(struct drm_device *dev)
 398 {
 399         return nouveau_display(dev)->priv;
 400 }
 401
 402 #define nv50_mast(d) (&nv50_disp(d)->mast)
 403
 404 static struct drm_crtc *
 405 nv50_display_crtc_get(struct drm_encoder *encoder)
 406 {
 407         return nouveau_encoder(encoder)->crtc;
 408 }
 409
 410 /******************************************************************************
 411  * EVO channel helpers
 412  *****************************************************************************/
 413 static u32 *
 414 evo_wait(void *evoc, int nr)
 415 {
 416         struct nv50_dmac *dmac = evoc;
 417         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 418
 419         mutex_lock(&dmac->lock);
 420         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 421                 dmac->ptr[put] = 0x20000000;
 422
 423                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 424                 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
 425                         mutex_unlock(&dmac->lock);
 426                         nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
 427                         return NULL;
 428                 }
 429
 430                 put = 0;
 431         }
 432
 433         return dmac->ptr + put;
 434 }
 435
 436 static void
 437 evo_kick(u32 *push, void *evoc)
 438 {
 439         struct nv50_dmac *dmac = evoc;
 440         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 441         mutex_unlock(&dmac->lock);
 442 }
 443
 444 #if 1
 445 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 446 #define evo_data(p,d)   *((p)++) = (d)
 447 #else
 448 #define evo_mthd(p,m,s) do {                                                   \
 449         const u32 _m = (m), _s = (s);                                          \
 450         printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);                     \
 451         *((p)++) = ((_s << 18) | _m);                                          \
 452 } while(0)
 453 #define evo_data(p,d) do {                                                     \
 454         const u32 _d = (d);                                                    \
 455         printk(KERN_ERR "\t%08x\n", _d);                                       \
 456         *((p)++) = _d;                                                         \
 457 } while(0)
 458 #endif
 459
 460 static bool
 461 evo_sync_wait(void *data)
 462 {
 463         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 464                 return true;
 465         usleep_range(1, 2);
 466         return false;
 467 }
 468
 469 static int
 470 evo_sync(struct drm_device *dev)
 471 {
 472         struct nvif_device *device = &nouveau_drm(dev)->device;
 473         struct nv50_disp *disp = nv50_disp(dev);
 474         struct nv50_mast *mast = nv50_mast(dev);
 475         u32 *push = evo_wait(mast, 8);
 476         if (push) {
 477                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 478                 evo_mthd(push, 0x0084, 1);
 479                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 480                 evo_mthd(push, 0x0080, 2);
 481                 evo_data(push, 0x00000000);
 482                 evo_data(push, 0x00000000);
 483                 evo_kick(push, mast);
 484                 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
 485                         return 0;
 486         }
 487
 488         return -EBUSY;
 489 }
 490
 491 /******************************************************************************
 492  * Page flipping channel
 493  *****************************************************************************/
 494 struct nouveau_bo *
 495 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 496 {
 497         return nv50_disp(dev)->sync;
 498 }
 499
 500 struct nv50_display_flip {
 501         struct nv50_disp *disp;
 502         struct nv50_sync *chan;
 503 };
 504
 505 static bool
 506 nv50_display_flip_wait(void *data)
 507 {
 508         struct nv50_display_flip *flip = data;
 509         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 510                                               flip->chan->data)
 511                 return true;
 512         usleep_range(1, 2);
 513         return false;
 514 }
 515
 516 void
 517 nv50_display_flip_stop(struct drm_crtc *crtc)
 518 {
 519         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 520         struct nv50_display_flip flip = {
 521                 .disp = nv50_disp(crtc->dev),
 522                 .chan = nv50_sync(crtc),
 523         };
 524         u32 *push;
 525
 526         push = evo_wait(flip.chan, 8);
 527         if (push) {
 528                 evo_mthd(push, 0x0084, 1);
 529                 evo_data(push, 0x00000000);
 530                 evo_mthd(push, 0x0094, 1);
 531                 evo_data(push, 0x00000000);
 532                 evo_mthd(push, 0x00c0, 1);
 533                 evo_data(push, 0x00000000);
 534                 evo_mthd(push, 0x0080, 1);
 535                 evo_data(push, 0x00000000);
 536                 evo_kick(push, flip.chan);
 537         }
 538
 539         nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
 540 }
 541
 542 int
 543 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 544                        struct nouveau_channel *chan, u32 swap_interval)
 545 {
 546         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 547         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 548         struct nv50_head *head = nv50_head(crtc);
 549         struct nv50_sync *sync = nv50_sync(crtc);
 550         u32 *push;
 551         int ret;
 552
 553         swap_interval <<= 4;
 554         if (swap_interval == 0)
 555                 swap_interval |= 0x100;
 556         if (chan == NULL)
 557                 evo_sync(crtc->dev);
 558
 559         push = evo_wait(sync, 128);
 560         if (unlikely(push == NULL))
 561                 return -EBUSY;
 562
 563         if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
 564                 ret = RING_SPACE(chan, 8);
 565                 if (ret)
 566                         return ret;
 567
 568                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 569                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 570                 OUT_RING  (chan, sync->addr ^ 0x10);
 571                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 572                 OUT_RING  (chan, sync->data + 1);
 573                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 574                 OUT_RING  (chan, sync->addr);
 575                 OUT_RING  (chan, sync->data);
 576         } else
 577         if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
 578                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 579                 ret = RING_SPACE(chan, 12);
 580                 if (ret)
 581                         return ret;
 582
 583                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 584                 OUT_RING  (chan, chan->vram.handle);
 585                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 586                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 587                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 588                 OUT_RING  (chan, sync->data + 1);
 589                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 590                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 591                 OUT_RING  (chan, upper_32_bits(addr));
 592                 OUT_RING  (chan, lower_32_bits(addr));
 593                 OUT_RING  (chan, sync->data);
 594                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 595         } else
 596         if (chan) {
 597                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 598                 ret = RING_SPACE(chan, 10);
 599                 if (ret)
 600                         return ret;
 601
 602                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 603                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 604                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 605                 OUT_RING  (chan, sync->data + 1);
 606                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 607                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 608                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 609                 OUT_RING  (chan, upper_32_bits(addr));
 610                 OUT_RING  (chan, lower_32_bits(addr));
 611                 OUT_RING  (chan, sync->data);
 612                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 613                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 614         }
 615
 616         if (chan) {
 617                 sync->addr ^= 0x10;
 618                 sync->data++;
 619                 FIRE_RING (chan);
 620         }
 621
 622         /* queue the flip */
 623         evo_mthd(push, 0x0100, 1);
 624         evo_data(push, 0xfffe0000);
 625         evo_mthd(push, 0x0084, 1);
 626         evo_data(push, swap_interval);
 627         if (!(swap_interval & 0x00000100)) {
 628                 evo_mthd(push, 0x00e0, 1);
 629                 evo_data(push, 0x40000000);
 630         }
 631         evo_mthd(push, 0x0088, 4);
 632         evo_data(push, sync->addr);
 633         evo_data(push, sync->data++);
 634         evo_data(push, sync->data);
 635         evo_data(push, sync->base.sync.handle);
 636         evo_mthd(push, 0x00a0, 2);
 637         evo_data(push, 0x00000000);
 638         evo_data(push, 0x00000000);
 639         evo_mthd(push, 0x00c0, 1);
 640         evo_data(push, nv_fb->r_handle);
 641         evo_mthd(push, 0x0110, 2);
 642         evo_data(push, 0x00000000);
 643         evo_data(push, 0x00000000);
 644         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 645                 evo_mthd(push, 0x0800, 5);
 646                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 647                 evo_data(push, 0);
 648                 evo_data(push, (fb->height << 16) | fb->width);
 649                 evo_data(push, nv_fb->r_pitch);
 650                 evo_data(push, nv_fb->r_format);
 651         } else {
 652                 evo_mthd(push, 0x0400, 5);
 653                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 654                 evo_data(push, 0);
 655                 evo_data(push, (fb->height << 16) | fb->width);
 656                 evo_data(push, nv_fb->r_pitch);
 657                 evo_data(push, nv_fb->r_format);
 658         }
 659         evo_mthd(push, 0x0080, 1);
 660         evo_data(push, 0x00000000);
 661         evo_kick(push, sync);
 662
 663         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 664         return 0;
 665 }
 666
 667 /******************************************************************************
 668  * CRTC
 669  *****************************************************************************/
 670 static int
 671 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 672 {
 673         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 674         struct nouveau_connector *nv_connector;
 675         struct drm_connector *connector;
 676         u32 *push, mode = 0x00;
 677
 678         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 679         connector = &nv_connector->base;
 680         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 681                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 682                         mode = DITHERING_MODE_DYNAMIC2X2;
 683         } else {
 684                 mode = nv_connector->dithering_mode;
 685         }
 686
 687         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 688                 if (connector->display_info.bpc >= 8)
 689                         mode |= DITHERING_DEPTH_8BPC;
 690         } else {
 691                 mode |= nv_connector->dithering_depth;
 692         }
 693
 694         push = evo_wait(mast, 4);
 695         if (push) {
 696                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 697                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 698                         evo_data(push, mode);
 699                 } else
 700                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 701                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 702                         evo_data(push, mode);
 703                 } else {
 704                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 705                         evo_data(push, mode);
 706                 }
 707
 708                 if (update) {
 709                         evo_mthd(push, 0x0080, 1);
 710                         evo_data(push, 0x00000000);
 711                 }
 712                 evo_kick(push, mast);
 713         }
 714
 715         return 0;
 716 }
 717
 718 static int
 719 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 720 {
 721         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 722         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 723         struct drm_crtc *crtc = &nv_crtc->base;
 724         struct nouveau_connector *nv_connector;
 725         int mode = DRM_MODE_SCALE_NONE;
 726         u32 oX, oY, *push;
 727
 728         /* start off at the resolution we programmed the crtc for, this
 729          * effectively handles NONE/FULL scaling
 730          */
 731         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 732         if (nv_connector && nv_connector->native_mode)
 733                 mode = nv_connector->scaling_mode;
 734
 735         if (mode != DRM_MODE_SCALE_NONE)
 736                 omode = nv_connector->native_mode;
 737         else
 738                 omode = umode;
 739
 740         oX = omode->hdisplay;
 741         oY = omode->vdisplay;
 742         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 743                 oY *= 2;
 744
 745         /* add overscan compensation if necessary, will keep the aspect
 746          * ratio the same as the backend mode unless overridden by the
 747          * user setting both hborder and vborder properties.
 748          */
 749         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 750                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 751                               nv_connector->edid &&
 752                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 753                 u32 bX = nv_connector->underscan_hborder;
 754                 u32 bY = nv_connector->underscan_vborder;
 755                 u32 aspect = (oY << 19) / oX;
 756
 757                 if (bX) {
 758                         oX -= (bX * 2);
 759                         if (bY) oY -= (bY * 2);
 760                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 761                 } else {
 762                         oX -= (oX >> 4) + 32;
 763                         if (bY) oY -= (bY * 2);
 764                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 765                 }
 766         }
 767
 768         /* handle CENTER/ASPECT scaling, taking into account the areas
 769          * removed already for overscan compensation
 770          */
 771         switch (mode) {
 772         case DRM_MODE_SCALE_CENTER:
 773                 oX = min((u32)umode->hdisplay, oX);
 774                 oY = min((u32)umode->vdisplay, oY);
 775                 /* fall-through */
 776         case DRM_MODE_SCALE_ASPECT:
 777                 if (oY < oX) {
 778                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 779                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 780                 } else {
 781                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 782                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 783                 }
 784                 break;
 785         default:
 786                 break;
 787         }
 788
 789         push = evo_wait(mast, 8);
 790         if (push) {
 791                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 792                         /*XXX: SCALE_CTRL_ACTIVE??? */
 793                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 794                         evo_data(push, (oY << 16) | oX);
 795                         evo_data(push, (oY << 16) | oX);
 796                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 797                         evo_data(push, 0x00000000);
 798                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 799                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 800                 } else {
 801                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 802                         evo_data(push, (oY << 16) | oX);
 803                         evo_data(push, (oY << 16) | oX);
 804                         evo_data(push, (oY << 16) | oX);
 805                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 806                         evo_data(push, 0x00000000);
 807                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 808                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 809                 }
 810
 811                 evo_kick(push, mast);
 812
 813                 if (update) {
 814                         nv50_display_flip_stop(crtc);
 815                         nv50_display_flip_next(crtc, crtc->primary->fb,
 816                                                NULL, 1);
 817                 }
 818         }
 819
 820         return 0;
 821 }
 822
 823 static int
 824 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
 825 {
 826         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 827         u32 *push;
 828
 829         push = evo_wait(mast, 8);
 830         if (!push)
 831                 return -ENOMEM;
 832
 833         evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
 834         evo_data(push, usec);
 835         evo_kick(push, mast);
 836         return 0;
 837 }
 838
 839 static int
 840 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 841 {
 842         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 843         u32 *push, hue, vib;
 844         int adj;
 845
 846         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 847         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 848         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 849
 850         push = evo_wait(mast, 16);
 851         if (push) {
 852                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 853                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 854                         evo_data(push, (hue << 20) | (vib << 8));
 855                 } else {
 856                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 857                         evo_data(push, (hue << 20) | (vib << 8));
 858                 }
 859
 860                 if (update) {
 861                         evo_mthd(push, 0x0080, 1);
 862                         evo_data(push, 0x00000000);
 863                 }
 864                 evo_kick(push, mast);
 865         }
 866
 867         return 0;
 868 }
 869
 870 static int
 871 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 872                     int x, int y, bool update)
 873 {
 874         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 875         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 876         u32 *push;
 877
 878         push = evo_wait(mast, 16);
 879         if (push) {
 880                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 881                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 882                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 883                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 884                         evo_data(push, (fb->height << 16) | fb->width);
 885                         evo_data(push, nvfb->r_pitch);
 886                         evo_data(push, nvfb->r_format);
 887                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 888                         evo_data(push, (y << 16) | x);
 889                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 890                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 891                                 evo_data(push, nvfb->r_handle);
 892                         }
 893                 } else {
 894                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 895                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 896                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 897                         evo_data(push, (fb->height << 16) | fb->width);
 898                         evo_data(push, nvfb->r_pitch);
 899                         evo_data(push, nvfb->r_format);
 900                         evo_data(push, nvfb->r_handle);
 901                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 902                         evo_data(push, (y << 16) | x);
 903                 }
 904
 905                 if (update) {
 906                         evo_mthd(push, 0x0080, 1);
 907                         evo_data(push, 0x00000000);
 908                 }
 909                 evo_kick(push, mast);
 910         }
 911
 912         nv_crtc->fb.handle = nvfb->r_handle;
 913         return 0;
 914 }
 915
 916 static void
 917 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 918 {
 919         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 920         struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
 921         u32 *push = evo_wait(mast, 16);
 922         if (push) {
 923                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 924                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 925                         evo_data(push, 0x85000000);
 926                         evo_data(push, curs->image->bo.offset >> 8);
 927                 } else
 928                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 929                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 930                         evo_data(push, 0x85000000);
 931                         evo_data(push, curs->image->bo.offset >> 8);
 932                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 933                         evo_data(push, mast->base.vram.handle);
 934                 } else {
 935                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 936                         evo_data(push, 0x85000000);
 937                         evo_data(push, curs->image->bo.offset >> 8);
 938                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 939                         evo_data(push, mast->base.vram.handle);
 940                 }
 941                 evo_kick(push, mast);
 942         }
 943 }
 944
 945 static void
 946 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 947 {
 948         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 949         u32 *push = evo_wait(mast, 16);
 950         if (push) {
 951                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 952                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 953                         evo_data(push, 0x05000000);
 954                 } else
 955                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 956                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 957                         evo_data(push, 0x05000000);
 958                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 959                         evo_data(push, 0x00000000);
 960                 } else {
 961                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 962                         evo_data(push, 0x05000000);
 963                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 964                         evo_data(push, 0x00000000);
 965                 }
 966                 evo_kick(push, mast);
 967         }
 968 }
 969
 970 static void
 971 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 972 {
 973         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 974         struct nv50_curs *curs = nv50_curs(&nv_crtc->base);
 975
 976         if (show && curs->image)
 977                 nv50_crtc_cursor_show(nv_crtc);
 978         else
 979                 nv50_crtc_cursor_hide(nv_crtc);
 980
 981         if (update) {
 982                 u32 *push = evo_wait(mast, 2);
 983                 if (push) {
 984                         evo_mthd(push, 0x0080, 1);
 985                         evo_data(push, 0x00000000);
 986                         evo_kick(push, mast);
 987                 }
 988         }
 989 }
 990
 991 static void
 992 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 993 {
 994 }
 995
 996 static void
 997 nv50_crtc_prepare(struct drm_crtc *crtc)
 998 {
 999         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1000         struct nv50_mast *mast = nv50_mast(crtc->dev);
1001         u32 *push;
1002
1003         nv50_display_flip_stop(crtc);
1004
1005         push = evo_wait(mast, 6);
1006         if (push) {
1007                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1008                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1009                         evo_data(push, 0x00000000);
1010                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1011                         evo_data(push, 0x40000000);
1012                 } else
1013                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
1014                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1015                         evo_data(push, 0x00000000);
1016                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1017                         evo_data(push, 0x40000000);
1018                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1019                         evo_data(push, 0x00000000);
1020                 } else {
1021                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1022                         evo_data(push, 0x00000000);
1023                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1024                         evo_data(push, 0x03000000);
1025                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1026                         evo_data(push, 0x00000000);
1027                 }
1028
1029                 evo_kick(push, mast);
1030         }
1031
1032         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1033 }
1034
1035 static void
1036 nv50_crtc_commit(struct drm_crtc *crtc)
1037 {
1038         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1039         struct nv50_mast *mast = nv50_mast(crtc->dev);
1040         u32 *push;
1041
1042         push = evo_wait(mast, 32);
1043         if (push) {
1044                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1045                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1046                         evo_data(push, nv_crtc->fb.handle);
1047                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1048                         evo_data(push, 0xc0000000);
1049                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1050                 } else
1051                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1052                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1053                         evo_data(push, nv_crtc->fb.handle);
1054                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1055                         evo_data(push, 0xc0000000);
1056                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1057                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1058                         evo_data(push, mast->base.vram.handle);
1059                 } else {
1060                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1061                         evo_data(push, nv_crtc->fb.handle);
1062                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1063                         evo_data(push, 0x83000000);
1064                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1065                         evo_data(push, 0x00000000);
1066                         evo_data(push, 0x00000000);
1067                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1068                         evo_data(push, mast->base.vram.handle);
1069                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1070                         evo_data(push, 0xffffff00);
1071                 }
1072
1073                 evo_kick(push, mast);
1074         }
1075
1076         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1077         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1078 }
1079
1080 static bool
1081 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1082                      struct drm_display_mode *adjusted_mode)
1083 {
1084         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1085         return true;
1086 }
1087
1088 static int
1089 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1090 {
1091         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1092         struct nv50_head *head = nv50_head(crtc);
1093         int ret;
1094
1095         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1096         if (ret == 0) {
1097                 if (head->image)
1098                         nouveau_bo_unpin(head->image);
1099                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1100         }
1101
1102         return ret;
1103 }
1104
1105 static int
1106 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1107                    struct drm_display_mode *mode, int x, int y,
1108                    struct drm_framebuffer *old_fb)
1109 {
1110         struct nv50_mast *mast = nv50_mast(crtc->dev);
1111         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1112         struct nouveau_connector *nv_connector;
1113         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1114         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1115         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1116         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1117         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1118         u32 *push;
1119         int ret;
1120
1121         hactive = mode->htotal;
1122         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1123         hbackp  = mode->htotal - mode->hsync_end;
1124         hblanke = hsynce + hbackp;
1125         hfrontp = mode->hsync_start - mode->hdisplay;
1126         hblanks = mode->htotal - hfrontp - 1;
1127
1128         vactive = mode->vtotal * vscan / ilace;
1129         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1130         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1131         vblanke = vsynce + vbackp;
1132         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1133         vblanks = vactive - vfrontp - 1;
1134         /* XXX: Safe underestimate, even "0" works */
1135         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1136         vblankus *= 1000;
1137         vblankus /= mode->clock;
1138
1139         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1140                 vblan2e = vactive + vsynce + vbackp;
1141                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1142                 vactive = (vactive * 2) + 1;
1143         }
1144
1145         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1146         if (ret)
1147                 return ret;
1148
1149         push = evo_wait(mast, 64);
1150         if (push) {
1151                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1152                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1153                         evo_data(push, 0x00800000 | mode->clock);
1154                         evo_data(push, (ilace == 2) ? 2 : 0);
1155                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1156                         evo_data(push, 0x00000000);
1157                         evo_data(push, (vactive << 16) | hactive);
1158                         evo_data(push, ( vsynce << 16) | hsynce);
1159                         evo_data(push, (vblanke << 16) | hblanke);
1160                         evo_data(push, (vblanks << 16) | hblanks);
1161                         evo_data(push, (vblan2e << 16) | vblan2s);
1162                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1163                         evo_data(push, 0x00000000);
1164                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1165                         evo_data(push, 0x00000311);
1166                         evo_data(push, 0x00000100);
1167                 } else {
1168                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1169                         evo_data(push, 0x00000000);
1170                         evo_data(push, (vactive << 16) | hactive);
1171                         evo_data(push, ( vsynce << 16) | hsynce);
1172                         evo_data(push, (vblanke << 16) | hblanke);
1173                         evo_data(push, (vblanks << 16) | hblanks);
1174                         evo_data(push, (vblan2e << 16) | vblan2s);
1175                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1176                         evo_data(push, 0x00000000); /* ??? */
1177                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1178                         evo_data(push, mode->clock * 1000);
1179                         evo_data(push, 0x00200000); /* ??? */
1180                         evo_data(push, mode->clock * 1000);
1181                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1182                         evo_data(push, 0x00000311);
1183                         evo_data(push, 0x00000100);
1184                 }
1185
1186                 evo_kick(push, mast);
1187         }
1188
1189         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1190         nv50_crtc_set_dither(nv_crtc, false);
1191         nv50_crtc_set_scale(nv_crtc, false);
1192
1193         /* G94 only accepts this after setting scale */
1194         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1195                 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1196
1197         nv50_crtc_set_color_vibrance(nv_crtc, false);
1198         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1199         return 0;
1200 }
1201
1202 static int
1203 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1204                         struct drm_framebuffer *old_fb)
1205 {
1206         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1207         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1208         int ret;
1209
1210         if (!crtc->primary->fb) {
1211                 NV_DEBUG(drm, "No FB bound\n");
1212                 return 0;
1213         }
1214
1215         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1216         if (ret)
1217                 return ret;
1218
1219         nv50_display_flip_stop(crtc);
1220         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1221         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1222         return 0;
1223 }
1224
1225 static int
1226 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1227                                struct drm_framebuffer *fb, int x, int y,
1228                                enum mode_set_atomic state)
1229 {
1230         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1231         nv50_display_flip_stop(crtc);
1232         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1233         return 0;
1234 }
1235
1236 static void
1237 nv50_crtc_lut_load(struct drm_crtc *crtc)
1238 {
1239         struct nv50_disp *disp = nv50_disp(crtc->dev);
1240         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1241         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1242         int i;
1243
1244         for (i = 0; i < 256; i++) {
1245                 u16 r = nv_crtc->lut.r[i] >> 2;
1246                 u16 g = nv_crtc->lut.g[i] >> 2;
1247                 u16 b = nv_crtc->lut.b[i] >> 2;
1248
1249                 if (disp->disp->oclass < GF110_DISP) {
1250                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1251                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1252                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1253                 } else {
1254                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1255                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1256                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1257                 }
1258         }
1259 }
1260
1261 static void
1262 nv50_crtc_disable(struct drm_crtc *crtc)
1263 {
1264         struct nv50_head *head = nv50_head(crtc);
1265         evo_sync(crtc->dev);
1266         if (head->image)
1267                 nouveau_bo_unpin(head->image);
1268         nouveau_bo_ref(NULL, &head->image);
1269 }
1270
1271 static int
1272 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1273                      uint32_t handle, uint32_t width, uint32_t height)
1274 {
1275         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1276         struct nv50_curs *curs = nv50_curs(crtc);
1277         struct drm_device *dev = crtc->dev;
1278         struct drm_gem_object *gem = NULL;
1279         struct nouveau_bo *nvbo = NULL;
1280         int ret = 0;
1281
1282         if (handle) {
1283                 if (width != 64 || height != 64)
1284                         return -EINVAL;
1285
1286                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1287                 if (unlikely(!gem))
1288                         return -ENOENT;
1289                 nvbo = nouveau_gem_object(gem);
1290
1291                 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1292         }
1293
1294         if (ret == 0) {
1295                 if (curs->image)
1296                         nouveau_bo_unpin(curs->image);
1297                 nouveau_bo_ref(nvbo, &curs->image);
1298         }
1299         drm_gem_object_unreference_unlocked(gem);
1300
1301         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1302         return ret;
1303 }
1304
1305 static int
1306 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1307 {
1308         struct nv50_curs *curs = nv50_curs(crtc);
1309         struct nv50_chan *chan = nv50_chan(curs);
1310         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1311         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1312         return 0;
1313 }
1314
1315 static void
1316 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1317                     uint32_t start, uint32_t size)
1318 {
1319         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1320         u32 end = min_t(u32, start + size, 256);
1321         u32 i;
1322
1323         for (i = start; i < end; i++) {
1324                 nv_crtc->lut.r[i] = r[i];
1325                 nv_crtc->lut.g[i] = g[i];
1326                 nv_crtc->lut.b[i] = b[i];
1327         }
1328
1329         nv50_crtc_lut_load(crtc);
1330 }
1331
1332 static void
1333 nv50_crtc_destroy(struct drm_crtc *crtc)
1334 {
1335         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1336         struct nv50_disp *disp = nv50_disp(crtc->dev);
1337         struct nv50_head *head = nv50_head(crtc);
1338         struct nv50_fbdma *fbdma;
1339
1340         list_for_each_entry(fbdma, &disp->fbdma, head) {
1341                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1342         }
1343
1344         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1345         nv50_pioc_destroy(&head->oimm.base);
1346         nv50_dmac_destroy(&head->sync.base, disp->disp);
1347         nv50_pioc_destroy(&head->curs.base);
1348
1349         /*XXX: this shouldn't be necessary, but the core doesn't call
1350          *     disconnect() during the cleanup paths
1351          */
1352         if (head->image)
1353                 nouveau_bo_unpin(head->image);
1354         nouveau_bo_ref(NULL, &head->image);
1355
1356         /*XXX: ditto */
1357         if (head->curs.image)
1358                 nouveau_bo_unpin(head->curs.image);
1359         nouveau_bo_ref(NULL, &head->curs.image);
1360
1361         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1362         if (nv_crtc->lut.nvbo)
1363                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1364         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1365
1366         drm_crtc_cleanup(crtc);
1367         kfree(crtc);
1368 }
1369
1370 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1371         .dpms = nv50_crtc_dpms,
1372         .prepare = nv50_crtc_prepare,
1373         .commit = nv50_crtc_commit,
1374         .mode_fixup = nv50_crtc_mode_fixup,
1375         .mode_set = nv50_crtc_mode_set,
1376         .mode_set_base = nv50_crtc_mode_set_base,
1377         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1378         .load_lut = nv50_crtc_lut_load,
1379         .disable = nv50_crtc_disable,
1380 };
1381
1382 static const struct drm_crtc_funcs nv50_crtc_func = {
1383         .cursor_set = nv50_crtc_cursor_set,
1384         .cursor_move = nv50_crtc_cursor_move,
1385         .gamma_set = nv50_crtc_gamma_set,
1386         .set_config = nouveau_crtc_set_config,
1387         .destroy = nv50_crtc_destroy,
1388         .page_flip = nouveau_crtc_page_flip,
1389 };
1390
1391 static int
1392 nv50_crtc_create(struct drm_device *dev, int index)
1393 {
1394         struct nv50_disp *disp = nv50_disp(dev);
1395         struct nv50_head *head;
1396         struct drm_crtc *crtc;
1397         int ret, i;
1398
1399         head = kzalloc(sizeof(*head), GFP_KERNEL);
1400         if (!head)
1401                 return -ENOMEM;
1402
1403         head->base.index = index;
1404         head->base.set_dither = nv50_crtc_set_dither;
1405         head->base.set_scale = nv50_crtc_set_scale;
1406         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1407         head->base.color_vibrance = 50;
1408         head->base.vibrant_hue = 0;
1409         for (i = 0; i < 256; i++) {
1410                 head->base.lut.r[i] = i << 8;
1411                 head->base.lut.g[i] = i << 8;
1412                 head->base.lut.b[i] = i << 8;
1413         }
1414
1415         crtc = &head->base.base;
1416         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1417         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1418         drm_mode_crtc_set_gamma_size(crtc, 256);
1419
1420         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1421                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1422         if (!ret) {
1423                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1424                 if (!ret) {
1425                         ret = nouveau_bo_map(head->base.lut.nvbo);
1426                         if (ret)
1427                                 nouveau_bo_unpin(head->base.lut.nvbo);
1428                 }
1429                 if (ret)
1430                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1431         }
1432
1433         if (ret)
1434                 goto out;
1435
1436         nv50_crtc_lut_load(crtc);
1437
1438         /* allocate cursor resources */
1439         ret = nv50_curs_create(disp->disp, index, &head->curs);
1440         if (ret)
1441                 goto out;
1442
1443         /* allocate page flip / sync resources */
1444         ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1445                               &head->sync);
1446         if (ret)
1447                 goto out;
1448
1449         head->sync.addr = EVO_FLIP_SEM0(index);
1450         head->sync.data = 0x00000000;
1451
1452         /* allocate overlay resources */
1453         ret = nv50_oimm_create(disp->disp, index, &head->oimm);
1454         if (ret)
1455                 goto out;
1456
1457         ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1458                               &head->ovly);
1459         if (ret)
1460                 goto out;
1461
1462 out:
1463         if (ret)
1464                 nv50_crtc_destroy(crtc);
1465         return ret;
1466 }
1467
1468 /******************************************************************************
1469  * DAC
1470  *****************************************************************************/
1471 static void
1472 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1473 {
1474         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1475         struct nv50_disp *disp = nv50_disp(encoder->dev);
1476         struct {
1477                 struct nv50_disp_mthd_v1 base;
1478                 struct nv50_disp_dac_pwr_v0 pwr;
1479         } args = {
1480                 .base.version = 1,
1481                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1482                 .base.hasht  = nv_encoder->dcb->hasht,
1483                 .base.hashm  = nv_encoder->dcb->hashm,
1484                 .pwr.state = 1,
1485                 .pwr.data  = 1,
1486                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1487                               mode != DRM_MODE_DPMS_OFF),
1488                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1489                               mode != DRM_MODE_DPMS_OFF),
1490         };
1491
1492         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1493 }
1494
1495 static bool
1496 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1497                     const struct drm_display_mode *mode,
1498                     struct drm_display_mode *adjusted_mode)
1499 {
1500         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1501         struct nouveau_connector *nv_connector;
1502
1503         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1504         if (nv_connector && nv_connector->native_mode) {
1505                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1506                         int id = adjusted_mode->base.id;
1507                         *adjusted_mode = *nv_connector->native_mode;
1508                         adjusted_mode->base.id = id;
1509                 }
1510         }
1511
1512         return true;
1513 }
1514
1515 static void
1516 nv50_dac_commit(struct drm_encoder *encoder)
1517 {
1518 }
1519
1520 static void
1521 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1522                   struct drm_display_mode *adjusted_mode)
1523 {
1524         struct nv50_mast *mast = nv50_mast(encoder->dev);
1525         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1526         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1527         u32 *push;
1528
1529         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1530
1531         push = evo_wait(mast, 8);
1532         if (push) {
1533                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1534                         u32 syncs = 0x00000000;
1535
1536                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1537                                 syncs |= 0x00000001;
1538                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1539                                 syncs |= 0x00000002;
1540
1541                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1542                         evo_data(push, 1 << nv_crtc->index);
1543                         evo_data(push, syncs);
1544                 } else {
1545                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1546                         u32 syncs = 0x00000001;
1547
1548                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1549                                 syncs |= 0x00000008;
1550                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1551                                 syncs |= 0x00000010;
1552
1553                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1554                                 magic |= 0x00000001;
1555
1556                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1557                         evo_data(push, syncs);
1558                         evo_data(push, magic);
1559                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1560                         evo_data(push, 1 << nv_crtc->index);
1561                 }
1562
1563                 evo_kick(push, mast);
1564         }
1565
1566         nv_encoder->crtc = encoder->crtc;
1567 }
1568
1569 static void
1570 nv50_dac_disconnect(struct drm_encoder *encoder)
1571 {
1572         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1573         struct nv50_mast *mast = nv50_mast(encoder->dev);
1574         const int or = nv_encoder->or;
1575         u32 *push;
1576
1577         if (nv_encoder->crtc) {
1578                 nv50_crtc_prepare(nv_encoder->crtc);
1579
1580                 push = evo_wait(mast, 4);
1581                 if (push) {
1582                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1583                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1584                                 evo_data(push, 0x00000000);
1585                         } else {
1586                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1587                                 evo_data(push, 0x00000000);
1588                         }
1589                         evo_kick(push, mast);
1590                 }
1591         }
1592
1593         nv_encoder->crtc = NULL;
1594 }
1595
1596 static enum drm_connector_status
1597 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1598 {
1599         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1600         struct nv50_disp *disp = nv50_disp(encoder->dev);
1601         struct {
1602                 struct nv50_disp_mthd_v1 base;
1603                 struct nv50_disp_dac_load_v0 load;
1604         } args = {
1605                 .base.version = 1,
1606                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1607                 .base.hasht  = nv_encoder->dcb->hasht,
1608                 .base.hashm  = nv_encoder->dcb->hashm,
1609         };
1610         int ret;
1611
1612         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1613         if (args.load.data == 0)
1614                 args.load.data = 340;
1615
1616         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1617         if (ret || !args.load.load)
1618                 return connector_status_disconnected;
1619
1620         return connector_status_connected;
1621 }
1622
1623 static void
1624 nv50_dac_destroy(struct drm_encoder *encoder)
1625 {
1626         drm_encoder_cleanup(encoder);
1627         kfree(encoder);
1628 }
1629
1630 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1631         .dpms = nv50_dac_dpms,
1632         .mode_fixup = nv50_dac_mode_fixup,
1633         .prepare = nv50_dac_disconnect,
1634         .commit = nv50_dac_commit,
1635         .mode_set = nv50_dac_mode_set,
1636         .disable = nv50_dac_disconnect,
1637         .get_crtc = nv50_display_crtc_get,
1638         .detect = nv50_dac_detect
1639 };
1640
1641 static const struct drm_encoder_funcs nv50_dac_func = {
1642         .destroy = nv50_dac_destroy,
1643 };
1644
1645 static int
1646 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1647 {
1648         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1649         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
1650         struct nouveau_encoder *nv_encoder;
1651         struct drm_encoder *encoder;
1652         int type = DRM_MODE_ENCODER_DAC;
1653
1654         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1655         if (!nv_encoder)
1656                 return -ENOMEM;
1657         nv_encoder->dcb = dcbe;
1658         nv_encoder->or = ffs(dcbe->or) - 1;
1659         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1660
1661         encoder = to_drm_encoder(nv_encoder);
1662         encoder->possible_crtcs = dcbe->heads;
1663         encoder->possible_clones = 0;
1664         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1665         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1666
1667         drm_mode_connector_attach_encoder(connector, encoder);
1668         return 0;
1669 }
1670
1671 /******************************************************************************
1672  * Audio
1673  *****************************************************************************/
1674 static void
1675 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1676 {
1677         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1678         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1679         struct nouveau_connector *nv_connector;
1680         struct nv50_disp *disp = nv50_disp(encoder->dev);
1681         struct __packed {
1682                 struct {
1683                         struct nv50_disp_mthd_v1 mthd;
1684                         struct nv50_disp_sor_hda_eld_v0 eld;
1685                 } base;
1686                 u8 data[sizeof(nv_connector->base.eld)];
1687         } args = {
1688                 .base.mthd.version = 1,
1689                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1690                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1691                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1692                                      (0x0100 << nv_crtc->index),
1693         };
1694
1695         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1696         if (!drm_detect_monitor_audio(nv_connector->edid))
1697                 return;
1698
1699         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1700         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1701
1702         nvif_mthd(disp->disp, 0, &args,
1703                   sizeof(args.base) + drm_eld_size(args.data));
1704 }
1705
1706 static void
1707 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1708 {
1709         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1710         struct nv50_disp *disp = nv50_disp(encoder->dev);
1711         struct {
1712                 struct nv50_disp_mthd_v1 base;
1713                 struct nv50_disp_sor_hda_eld_v0 eld;
1714         } args = {
1715                 .base.version = 1,
1716                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1717                 .base.hasht   = nv_encoder->dcb->hasht,
1718                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1719                                 (0x0100 << nv_crtc->index),
1720         };
1721
1722         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1723 }
1724
1725 /******************************************************************************
1726  * HDMI
1727  *****************************************************************************/
1728 static void
1729 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1730 {
1731         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1732         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1733         struct nv50_disp *disp = nv50_disp(encoder->dev);
1734         struct {
1735                 struct nv50_disp_mthd_v1 base;
1736                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1737         } args = {
1738                 .base.version = 1,
1739                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1740                 .base.hasht  = nv_encoder->dcb->hasht,
1741                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1742                                (0x0100 << nv_crtc->index),
1743                 .pwr.state = 1,
1744                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1745         };
1746         struct nouveau_connector *nv_connector;
1747         u32 max_ac_packet;
1748
1749         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1750         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1751                 return;
1752
1753         max_ac_packet  = mode->htotal - mode->hdisplay;
1754         max_ac_packet -= args.pwr.rekey;
1755         max_ac_packet -= 18; /* constant from tegra */
1756         args.pwr.max_ac_packet = max_ac_packet / 32;
1757
1758         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1759         nv50_audio_mode_set(encoder, mode);
1760 }
1761
1762 static void
1763 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1764 {
1765         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1766         struct nv50_disp *disp = nv50_disp(encoder->dev);
1767         struct {
1768                 struct nv50_disp_mthd_v1 base;
1769                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1770         } args = {
1771                 .base.version = 1,
1772                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1773                 .base.hasht  = nv_encoder->dcb->hasht,
1774                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1775                                (0x0100 << nv_crtc->index),
1776         };
1777
1778         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1779 }
1780
1781 /******************************************************************************
1782  * SOR
1783  *****************************************************************************/
1784 static void
1785 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1786 {
1787         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1788         struct nv50_disp *disp = nv50_disp(encoder->dev);
1789         struct {
1790                 struct nv50_disp_mthd_v1 base;
1791                 struct nv50_disp_sor_pwr_v0 pwr;
1792         } args = {
1793                 .base.version = 1,
1794                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1795                 .base.hasht  = nv_encoder->dcb->hasht,
1796                 .base.hashm  = nv_encoder->dcb->hashm,
1797                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1798         };
1799         struct {
1800                 struct nv50_disp_mthd_v1 base;
1801                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1802         } link = {
1803                 .base.version = 1,
1804                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1805                 .base.hasht  = nv_encoder->dcb->hasht,
1806                 .base.hashm  = nv_encoder->dcb->hashm,
1807                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1808         };
1809         struct drm_device *dev = encoder->dev;
1810         struct drm_encoder *partner;
1811
1812         nv_encoder->last_dpms = mode;
1813
1814         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1815                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1816
1817                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1818                         continue;
1819
1820                 if (nv_partner != nv_encoder &&
1821                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1822                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1823                                 return;
1824                         break;
1825                 }
1826         }
1827
1828         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1829                 args.pwr.state = 1;
1830                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1831                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1832         } else {
1833                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1834         }
1835 }
1836
1837 static bool
1838 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1839                     const struct drm_display_mode *mode,
1840                     struct drm_display_mode *adjusted_mode)
1841 {
1842         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1843         struct nouveau_connector *nv_connector;
1844
1845         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1846         if (nv_connector && nv_connector->native_mode) {
1847                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1848                         int id = adjusted_mode->base.id;
1849                         *adjusted_mode = *nv_connector->native_mode;
1850                         adjusted_mode->base.id = id;
1851                 }
1852         }
1853
1854         return true;
1855 }
1856
1857 static void
1858 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1859 {
1860         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1861         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1862         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1863                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1864                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1865                         evo_data(push, (nv_encoder->ctrl = temp));
1866                 } else {
1867                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1868                         evo_data(push, (nv_encoder->ctrl = temp));
1869                 }
1870                 evo_kick(push, mast);
1871         }
1872 }
1873
1874 static void
1875 nv50_sor_disconnect(struct drm_encoder *encoder)
1876 {
1877         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1878         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1879
1880         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1881         nv_encoder->crtc = NULL;
1882
1883         if (nv_crtc) {
1884                 nv50_crtc_prepare(&nv_crtc->base);
1885                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1886                 nv50_audio_disconnect(encoder, nv_crtc);
1887                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1888         }
1889 }
1890
1891 static void
1892 nv50_sor_commit(struct drm_encoder *encoder)
1893 {
1894 }
1895
1896 static void
1897 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1898                   struct drm_display_mode *mode)
1899 {
1900         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1901         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1902         struct {
1903                 struct nv50_disp_mthd_v1 base;
1904                 struct nv50_disp_sor_lvds_script_v0 lvds;
1905         } lvds = {
1906                 .base.version = 1,
1907                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1908                 .base.hasht   = nv_encoder->dcb->hasht,
1909                 .base.hashm   = nv_encoder->dcb->hashm,
1910         };
1911         struct nv50_disp *disp = nv50_disp(encoder->dev);
1912         struct nv50_mast *mast = nv50_mast(encoder->dev);
1913         struct drm_device *dev = encoder->dev;
1914         struct nouveau_drm *drm = nouveau_drm(dev);
1915         struct nouveau_connector *nv_connector;
1916         struct nvbios *bios = &drm->vbios;
1917         u32 mask, ctrl;
1918         u8 owner = 1 << nv_crtc->index;
1919         u8 proto = 0xf;
1920         u8 depth = 0x0;
1921
1922         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1923         nv_encoder->crtc = encoder->crtc;
1924
1925         switch (nv_encoder->dcb->type) {
1926         case DCB_OUTPUT_TMDS:
1927                 if (nv_encoder->dcb->sorconf.link & 1) {
1928                         if (mode->clock < 165000)
1929                                 proto = 0x1;
1930                         else
1931                                 proto = 0x5;
1932                 } else {
1933                         proto = 0x2;
1934                 }
1935
1936                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1937                 break;
1938         case DCB_OUTPUT_LVDS:
1939                 proto = 0x0;
1940
1941                 if (bios->fp_no_ddc) {
1942                         if (bios->fp.dual_link)
1943                                 lvds.lvds.script |= 0x0100;
1944                         if (bios->fp.if_is_24bit)
1945                                 lvds.lvds.script |= 0x0200;
1946                 } else {
1947                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1948                                 if (((u8 *)nv_connector->edid)[121] == 2)
1949                                         lvds.lvds.script |= 0x0100;
1950                         } else
1951                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1952                                 lvds.lvds.script |= 0x0100;
1953                         }
1954
1955                         if (lvds.lvds.script & 0x0100) {
1956                                 if (bios->fp.strapless_is_24bit & 2)
1957                                         lvds.lvds.script |= 0x0200;
1958                         } else {
1959                                 if (bios->fp.strapless_is_24bit & 1)
1960                                         lvds.lvds.script |= 0x0200;
1961                         }
1962
1963                         if (nv_connector->base.display_info.bpc == 8)
1964                                 lvds.lvds.script |= 0x0200;
1965                 }
1966
1967                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
1968                 break;
1969         case DCB_OUTPUT_DP:
1970                 if (nv_connector->base.display_info.bpc == 6) {
1971                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1972                         depth = 0x2;
1973                 } else
1974                 if (nv_connector->base.display_info.bpc == 8) {
1975                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1976                         depth = 0x5;
1977                 } else {
1978                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
1979                         depth = 0x6;
1980                 }
1981
1982                 if (nv_encoder->dcb->sorconf.link & 1)
1983                         proto = 0x8;
1984                 else
1985                         proto = 0x9;
1986                 nv50_audio_mode_set(encoder, mode);
1987                 break;
1988         default:
1989                 BUG_ON(1);
1990                 break;
1991         }
1992
1993         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1994
1995         if (nv50_vers(mast) >= GF110_DISP) {
1996                 u32 *push = evo_wait(mast, 3);
1997                 if (push) {
1998                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1999                         u32 syncs = 0x00000001;
2000
2001                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2002                                 syncs |= 0x00000008;
2003                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2004                                 syncs |= 0x00000010;
2005
2006                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2007                                 magic |= 0x00000001;
2008
2009                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2010                         evo_data(push, syncs | (depth << 6));
2011                         evo_data(push, magic);
2012                         evo_kick(push, mast);
2013                 }
2014
2015                 ctrl = proto << 8;
2016                 mask = 0x00000f00;
2017         } else {
2018                 ctrl = (depth << 16) | (proto << 8);
2019                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2020                         ctrl |= 0x00001000;
2021                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2022                         ctrl |= 0x00002000;
2023                 mask = 0x000f3f00;
2024         }
2025
2026         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2027 }
2028
2029 static void
2030 nv50_sor_destroy(struct drm_encoder *encoder)
2031 {
2032         drm_encoder_cleanup(encoder);
2033         kfree(encoder);
2034 }
2035
2036 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2037         .dpms = nv50_sor_dpms,
2038         .mode_fixup = nv50_sor_mode_fixup,
2039         .prepare = nv50_sor_disconnect,
2040         .commit = nv50_sor_commit,
2041         .mode_set = nv50_sor_mode_set,
2042         .disable = nv50_sor_disconnect,
2043         .get_crtc = nv50_display_crtc_get,
2044 };
2045
2046 static const struct drm_encoder_funcs nv50_sor_func = {
2047         .destroy = nv50_sor_destroy,
2048 };
2049
2050 static int
2051 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2052 {
2053         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2054         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2055         struct nouveau_encoder *nv_encoder;
2056         struct drm_encoder *encoder;
2057         int type;
2058
2059         switch (dcbe->type) {
2060         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2061         case DCB_OUTPUT_TMDS:
2062         case DCB_OUTPUT_DP:
2063         default:
2064                 type = DRM_MODE_ENCODER_TMDS;
2065                 break;
2066         }
2067
2068         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2069         if (!nv_encoder)
2070                 return -ENOMEM;
2071         nv_encoder->dcb = dcbe;
2072         nv_encoder->or = ffs(dcbe->or) - 1;
2073         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
2074         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2075
2076         encoder = to_drm_encoder(nv_encoder);
2077         encoder->possible_crtcs = dcbe->heads;
2078         encoder->possible_clones = 0;
2079         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
2080         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2081
2082         drm_mode_connector_attach_encoder(connector, encoder);
2083         return 0;
2084 }
2085
2086 /******************************************************************************
2087  * PIOR
2088  *****************************************************************************/
2089
2090 static void
2091 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2092 {
2093         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2094         struct nv50_disp *disp = nv50_disp(encoder->dev);
2095         struct {
2096                 struct nv50_disp_mthd_v1 base;
2097                 struct nv50_disp_pior_pwr_v0 pwr;
2098         } args = {
2099                 .base.version = 1,
2100                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2101                 .base.hasht  = nv_encoder->dcb->hasht,
2102                 .base.hashm  = nv_encoder->dcb->hashm,
2103                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2104                 .pwr.type = nv_encoder->dcb->type,
2105         };
2106
2107         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2108 }
2109
2110 static bool
2111 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2112                      const struct drm_display_mode *mode,
2113                      struct drm_display_mode *adjusted_mode)
2114 {
2115         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2116         struct nouveau_connector *nv_connector;
2117
2118         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2119         if (nv_connector && nv_connector->native_mode) {
2120                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2121                         int id = adjusted_mode->base.id;
2122                         *adjusted_mode = *nv_connector->native_mode;
2123                         adjusted_mode->base.id = id;
2124                 }
2125         }
2126
2127         adjusted_mode->clock *= 2;
2128         return true;
2129 }
2130
2131 static void
2132 nv50_pior_commit(struct drm_encoder *encoder)
2133 {
2134 }
2135
2136 static void
2137 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2138                    struct drm_display_mode *adjusted_mode)
2139 {
2140         struct nv50_mast *mast = nv50_mast(encoder->dev);
2141         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2142         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2143         struct nouveau_connector *nv_connector;
2144         u8 owner = 1 << nv_crtc->index;
2145         u8 proto, depth;
2146         u32 *push;
2147
2148         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2149         switch (nv_connector->base.display_info.bpc) {
2150         case 10: depth = 0x6; break;
2151         case  8: depth = 0x5; break;
2152         case  6: depth = 0x2; break;
2153         default: depth = 0x0; break;
2154         }
2155
2156         switch (nv_encoder->dcb->type) {
2157         case DCB_OUTPUT_TMDS:
2158         case DCB_OUTPUT_DP:
2159                 proto = 0x0;
2160                 break;
2161         default:
2162                 BUG_ON(1);
2163                 break;
2164         }
2165
2166         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2167
2168         push = evo_wait(mast, 8);
2169         if (push) {
2170                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2171                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2172                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2173                                 ctrl |= 0x00001000;
2174                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2175                                 ctrl |= 0x00002000;
2176                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2177                         evo_data(push, ctrl);
2178                 }
2179
2180                 evo_kick(push, mast);
2181         }
2182
2183         nv_encoder->crtc = encoder->crtc;
2184 }
2185
2186 static void
2187 nv50_pior_disconnect(struct drm_encoder *encoder)
2188 {
2189         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2190         struct nv50_mast *mast = nv50_mast(encoder->dev);
2191         const int or = nv_encoder->or;
2192         u32 *push;
2193
2194         if (nv_encoder->crtc) {
2195                 nv50_crtc_prepare(nv_encoder->crtc);
2196
2197                 push = evo_wait(mast, 4);
2198                 if (push) {
2199                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2200                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2201                                 evo_data(push, 0x00000000);
2202                         }
2203                         evo_kick(push, mast);
2204                 }
2205         }
2206
2207         nv_encoder->crtc = NULL;
2208 }
2209
2210 static void
2211 nv50_pior_destroy(struct drm_encoder *encoder)
2212 {
2213         drm_encoder_cleanup(encoder);
2214         kfree(encoder);
2215 }
2216
2217 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2218         .dpms = nv50_pior_dpms,
2219         .mode_fixup = nv50_pior_mode_fixup,
2220         .prepare = nv50_pior_disconnect,
2221         .commit = nv50_pior_commit,
2222         .mode_set = nv50_pior_mode_set,
2223         .disable = nv50_pior_disconnect,
2224         .get_crtc = nv50_display_crtc_get,
2225 };
2226
2227 static const struct drm_encoder_funcs nv50_pior_func = {
2228         .destroy = nv50_pior_destroy,
2229 };
2230
2231 static int
2232 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2233 {
2234         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2235         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2236         struct nouveau_i2c_port *ddc = NULL;
2237         struct nouveau_encoder *nv_encoder;
2238         struct drm_encoder *encoder;
2239         int type;
2240
2241         switch (dcbe->type) {
2242         case DCB_OUTPUT_TMDS:
2243                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2244                 type = DRM_MODE_ENCODER_TMDS;
2245                 break;
2246         case DCB_OUTPUT_DP:
2247                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2248                 type = DRM_MODE_ENCODER_TMDS;
2249                 break;
2250         default:
2251                 return -ENODEV;
2252         }
2253
2254         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2255         if (!nv_encoder)
2256                 return -ENOMEM;
2257         nv_encoder->dcb = dcbe;
2258         nv_encoder->or = ffs(dcbe->or) - 1;
2259         nv_encoder->i2c = ddc;
2260
2261         encoder = to_drm_encoder(nv_encoder);
2262         encoder->possible_crtcs = dcbe->heads;
2263         encoder->possible_clones = 0;
2264         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2265         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2266
2267         drm_mode_connector_attach_encoder(connector, encoder);
2268         return 0;
2269 }
2270
2271 /******************************************************************************
2272  * Framebuffer
2273  *****************************************************************************/
2274
2275 static void
2276 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2277 {
2278         int i;
2279         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2280                 nvif_object_fini(&fbdma->base[i]);
2281         nvif_object_fini(&fbdma->core);
2282         list_del(&fbdma->head);
2283         kfree(fbdma);
2284 }
2285
2286 static int
2287 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2288 {
2289         struct nouveau_drm *drm = nouveau_drm(dev);
2290         struct nv50_disp *disp = nv50_disp(dev);
2291         struct nv50_mast *mast = nv50_mast(dev);
2292         struct __attribute__ ((packed)) {
2293                 struct nv_dma_v0 base;
2294                 union {
2295                         struct nv50_dma_v0 nv50;
2296                         struct gf100_dma_v0 gf100;
2297                         struct gf110_dma_v0 gf110;
2298                 };
2299         } args = {};
2300         struct nv50_fbdma *fbdma;
2301         struct drm_crtc *crtc;
2302         u32 size = sizeof(args.base);
2303         int ret;
2304
2305         list_for_each_entry(fbdma, &disp->fbdma, head) {
2306                 if (fbdma->core.handle == name)
2307                         return 0;
2308         }
2309
2310         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2311         if (!fbdma)
2312                 return -ENOMEM;
2313         list_add(&fbdma->head, &disp->fbdma);
2314
2315         args.base.target = NV_DMA_V0_TARGET_VRAM;
2316         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2317         args.base.start = offset;
2318         args.base.limit = offset + length - 1;
2319
2320         if (drm->device.info.chipset < 0x80) {
2321                 args.nv50.part = NV50_DMA_V0_PART_256;
2322                 size += sizeof(args.nv50);
2323         } else
2324         if (drm->device.info.chipset < 0xc0) {
2325                 args.nv50.part = NV50_DMA_V0_PART_256;
2326                 args.nv50.kind = kind;
2327                 size += sizeof(args.nv50);
2328         } else
2329         if (drm->device.info.chipset < 0xd0) {
2330                 args.gf100.kind = kind;
2331                 size += sizeof(args.gf100);
2332         } else {
2333                 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2334                 args.gf110.kind = kind;
2335                 size += sizeof(args.gf110);
2336         }
2337
2338         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2339                 struct nv50_head *head = nv50_head(crtc);
2340                 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
2341                                             name, NV_DMA_IN_MEMORY, &args, size,
2342                                            &fbdma->base[head->base.index]);
2343                 if (ret) {
2344                         nv50_fbdma_fini(fbdma);
2345                         return ret;
2346                 }
2347         }
2348
2349         ret = nvif_object_init(&mast->base.base.user, NULL, name,
2350                                 NV_DMA_IN_MEMORY, &args, size,
2351                                &fbdma->core);
2352         if (ret) {
2353                 nv50_fbdma_fini(fbdma);
2354                 return ret;
2355         }
2356
2357         return 0;
2358 }
2359
2360 static void
2361 nv50_fb_dtor(struct drm_framebuffer *fb)
2362 {
2363 }
2364
2365 static int
2366 nv50_fb_ctor(struct drm_framebuffer *fb)
2367 {
2368         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2369         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2370         struct nouveau_bo *nvbo = nv_fb->nvbo;
2371         struct nv50_disp *disp = nv50_disp(fb->dev);
2372         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2373         u8 tile = nvbo->tile_mode;
2374
2375         if (drm->device.info.chipset >= 0xc0)
2376                 tile >>= 4; /* yep.. */
2377
2378         switch (fb->depth) {
2379         case  8: nv_fb->r_format = 0x1e00; break;
2380         case 15: nv_fb->r_format = 0xe900; break;
2381         case 16: nv_fb->r_format = 0xe800; break;
2382         case 24:
2383         case 32: nv_fb->r_format = 0xcf00; break;
2384         case 30: nv_fb->r_format = 0xd100; break;
2385         default:
2386                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2387                  return -EINVAL;
2388         }
2389
2390         if (disp->disp->oclass < G82_DISP) {
2391                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2392                                             (fb->pitches[0] | 0x00100000);
2393                 nv_fb->r_format |= kind << 16;
2394         } else
2395         if (disp->disp->oclass < GF110_DISP) {
2396                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2397                                            (fb->pitches[0] | 0x00100000);
2398         } else {
2399                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2400                                            (fb->pitches[0] | 0x01000000);
2401         }
2402         nv_fb->r_handle = 0xffff0000 | kind;
2403
2404         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2405                                drm->device.info.ram_user, kind);
2406 }
2407
2408 /******************************************************************************
2409  * Init
2410  *****************************************************************************/
2411
2412 void
2413 nv50_display_fini(struct drm_device *dev)
2414 {
2415 }
2416
2417 int
2418 nv50_display_init(struct drm_device *dev)
2419 {
2420         struct nv50_disp *disp = nv50_disp(dev);
2421         struct drm_crtc *crtc;
2422         u32 *push;
2423
2424         push = evo_wait(nv50_mast(dev), 32);
2425         if (!push)
2426                 return -EBUSY;
2427
2428         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2429                 struct nv50_sync *sync = nv50_sync(crtc);
2430                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2431         }
2432
2433         evo_mthd(push, 0x0088, 1);
2434         evo_data(push, nv50_mast(dev)->base.sync.handle);
2435         evo_kick(push, nv50_mast(dev));
2436         return 0;
2437 }
2438
2439 void
2440 nv50_display_destroy(struct drm_device *dev)
2441 {
2442         struct nv50_disp *disp = nv50_disp(dev);
2443         struct nv50_fbdma *fbdma, *fbtmp;
2444
2445         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2446                 nv50_fbdma_fini(fbdma);
2447         }
2448
2449         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2450
2451         nouveau_bo_unmap(disp->sync);
2452         if (disp->sync)
2453                 nouveau_bo_unpin(disp->sync);
2454         nouveau_bo_ref(NULL, &disp->sync);
2455
2456         nouveau_display(dev)->priv = NULL;
2457         kfree(disp);
2458 }
2459
2460 int
2461 nv50_display_create(struct drm_device *dev)
2462 {
2463         struct nvif_device *device = &nouveau_drm(dev)->device;
2464         struct nouveau_drm *drm = nouveau_drm(dev);
2465         struct dcb_table *dcb = &drm->vbios.dcb;
2466         struct drm_connector *connector, *tmp;
2467         struct nv50_disp *disp;
2468         struct dcb_output *dcbe;
2469         int crtcs, ret, i;
2470
2471         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2472         if (!disp)
2473                 return -ENOMEM;
2474         INIT_LIST_HEAD(&disp->fbdma);
2475
2476         nouveau_display(dev)->priv = disp;
2477         nouveau_display(dev)->dtor = nv50_display_destroy;
2478         nouveau_display(dev)->init = nv50_display_init;
2479         nouveau_display(dev)->fini = nv50_display_fini;
2480         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2481         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2482         disp->disp = &nouveau_display(dev)->disp;
2483
2484         /* small shared memory area we use for notifiers and semaphores */
2485         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2486                              0, 0x0000, NULL, NULL, &disp->sync);
2487         if (!ret) {
2488                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2489                 if (!ret) {
2490                         ret = nouveau_bo_map(disp->sync);
2491                         if (ret)
2492                                 nouveau_bo_unpin(disp->sync);
2493                 }
2494                 if (ret)
2495                         nouveau_bo_ref(NULL, &disp->sync);
2496         }
2497
2498         if (ret)
2499                 goto out;
2500
2501         /* allocate master evo channel */
2502         ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2503                               &disp->mast);
2504         if (ret)
2505                 goto out;
2506
2507         /* create crtc objects to represent the hw heads */
2508         if (disp->disp->oclass >= GF110_DISP)
2509                 crtcs = nvif_rd32(device, 0x022448);
2510         else
2511                 crtcs = 2;
2512
2513         for (i = 0; i < crtcs; i++) {
2514                 ret = nv50_crtc_create(dev, i);
2515                 if (ret)
2516                         goto out;
2517         }
2518
2519         /* create encoder/connector objects based on VBIOS DCB table */
2520         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2521                 connector = nouveau_connector_create(dev, dcbe->connector);
2522                 if (IS_ERR(connector))
2523                         continue;
2524
2525                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2526                         switch (dcbe->type) {
2527                         case DCB_OUTPUT_TMDS:
2528                         case DCB_OUTPUT_LVDS:
2529                         case DCB_OUTPUT_DP:
2530                                 ret = nv50_sor_create(connector, dcbe);
2531                                 break;
2532                         case DCB_OUTPUT_ANALOG:
2533                                 ret = nv50_dac_create(connector, dcbe);
2534                                 break;
2535                         default:
2536                                 ret = -ENODEV;
2537                                 break;
2538                         }
2539                 } else {
2540                         ret = nv50_pior_create(connector, dcbe);
2541                 }
2542
2543                 if (ret) {
2544                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2545                                      dcbe->location, dcbe->type,
2546                                      ffs(dcbe->or) - 1, ret);
2547                         ret = 0;
2548                 }
2549         }
2550
2551         /* cull any connectors we created that don't have an encoder */
2552         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2553                 if (connector->encoder_ids[0])
2554                         continue;
2555
2556                 NV_WARN(drm, "%s has no encoders, removing\n",
2557                         connector->name);
2558                 connector->funcs->destroy(connector);
2559         }
2560
2561 out:
2562         if (ret)
2563                 nv50_display_destroy(dev);
2564         return ret;
2565 }