2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice shall be included in
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
24 * Secure boot is the process by which NVIDIA-signed firmware is loaded into
25 * some of the falcons of a GPU. For production devices this is the only way
26 * for the firmware to access useful (but sensitive) registers.
28 * A Falcon microprocessor supporting advanced security modes can run in one of
31 * - Non-secure (NS). In this mode, functionality is similar to Falcon
32 * architectures before security modes were introduced (pre-Maxwell), but
33 * capability is restricted. In particular, certain registers may be
34 * inaccessible for reads and/or writes, and physical memory access may be
35 * disabled (on certain Falcon instances). This is the only possible mode that
36 * can be used if you don't have microcode cryptographically signed by NVIDIA.
38 * - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's
39 * not possible to read or write any Falcon internal state or Falcon registers
40 * from outside the Falcon (for example, from the host system). The only way
41 * to enable this mode is by loading microcode that has been signed by NVIDIA.
42 * (The loading process involves tagging the IMEM block as secure, writing the
43 * signature into a Falcon register, and starting execution. The hardware will
44 * validate the signature, and if valid, grant HS privileges.)
46 * - Light Secure (LS). In this mode, the microprocessor has more privileges
47 * than NS but fewer than HS. Some of the microprocessor state is visible to
48 * host software to ease debugging. The only way to enable this mode is by HS
49 * microcode enabling LS mode. Some privileges available to HS mode are not
50 * available here. LS mode is introduced in GM20x.
52 * Secure boot consists in temporarily switching a HS-capable falcon (typically
53 * PMU) into HS mode in order to validate the LS firmwares of managed falcons,
54 * load them, and switch managed falcons into LS mode. Once secure boot
55 * completes, no falcon remains in HS mode.
57 * Secure boot requires a write-protected memory region (WPR) which can only be
58 * written by the secure falcon. On dGPU, the driver sets up the WPR region in
59 * video memory. On Tegra, it is set up by the bootloader and its location and
60 * size written into memory controller registers.
62 * The secure boot process takes place as follows:
64 * 1) A LS blob is constructed that contains all the LS firmwares we want to
65 * load, along with their signatures and bootloaders.
67 * 2) A HS blob (also called ACR) is created that contains the signed HS
68 * firmware in charge of loading the LS firmwares into their respective
71 * 3) The HS blob is loaded (via its own bootloader) and executed on the
72 * HS-capable falcon. It authenticates itself, switches the secure falcon to
73 * HS mode and setup the WPR region around the LS blob (dGPU) or copies the
74 * LS blob into the WPR region (Tegra).
76 * 4) The LS blob is now secure from all external tampering. The HS falcon
77 * checks the signatures of the LS firmwares and, if valid, switches the
78 * managed falcons to LS mode and makes them ready to run the LS firmware.
80 * 5) The managed falcons remain in LS mode and can be started.
86 #include <core/gpuobj.h>
87 #include <core/firmware.h>
88 #include <subdev/fb.h>
91 FALCON_DMAIDX_UCODE = 0,
92 FALCON_DMAIDX_VIRT = 1,
93 FALCON_DMAIDX_PHYS_VID = 2,
94 FALCON_DMAIDX_PHYS_SYS_COH = 3,
95 FALCON_DMAIDX_PHYS_SYS_NCOH = 4,
99 * struct fw_bin_header - header of firmware files
100 * @bin_magic: always 0x3b1d14f0
101 * @bin_ver: version of the bin format
102 * @bin_size: entire image size including this header
103 * @header_offset: offset of the firmware/bootloader header in the file
104 * @data_offset: offset of the firmware/bootloader payload in the file
105 * @data_size: size of the payload
107 * This header is located at the beginning of the HS firmware and HS bootloader
108 * files, to describe where the headers and data can be found.
110 struct fw_bin_header {
120 * struct fw_bl_desc - firmware bootloader descriptor
121 * @start_tag: starting tag of bootloader
122 * @desc_dmem_load_off: DMEM offset of flcn_bl_dmem_desc
123 * @code_off: offset of code section
124 * @code_size: size of code section
125 * @data_off: offset of data section
126 * @data_size: size of data section
128 * This structure is embedded in bootloader firmware files at to describe the
129 * IMEM and DMEM layout expected by the bootloader.
148 * struct lsf_ucode_desc - LS falcon signatures
149 * @prd_keys: signature to use when the GPU is in production mode
150 * @dgb_keys: signature to use when the GPU is in debug mode
151 * @b_prd_present: whether the production key is present
152 * @b_dgb_present: whether the debug key is present
153 * @falcon_id: ID of the falcon the ucode applies to
155 * Directly loaded from a signature file.
157 struct lsf_ucode_desc {
166 * struct lsf_lsb_header - LS firmware header
167 * @signature: signature to verify the firmware against
168 * @ucode_off: offset of the ucode blob in the WPR region. The ucode
169 * blob contains the bootloader, code and data of the
171 * @ucode_size: size of the ucode blob, including bootloader
172 * @data_size: size of the ucode blob data
173 * @bl_code_size: size of the bootloader code
174 * @bl_imem_off: offset in imem of the bootloader
175 * @bl_data_off: offset of the bootloader data in WPR region
176 * @bl_data_size: size of the bootloader data
177 * @app_code_off: offset of the app code relative to ucode_off
178 * @app_code_size: size of the app code
179 * @app_data_off: offset of the app data relative to ucode_off
180 * @app_data_size: size of the app data
181 * @flags: flags for the secure bootloader
183 * This structure is written into the WPR region for each managed falcon. Each
184 * instance is referenced by the lsb_offset member of the corresponding
187 struct lsf_lsb_header {
188 struct lsf_ucode_desc signature;
201 #define LSF_FLAG_LOAD_CODE_AT_0 1
202 #define LSF_FLAG_DMACTL_REQ_CTX 4
203 #define LSF_FLAG_FORCE_PRIV_LOAD 8
207 * struct lsf_wpr_header - LS blob WPR Header
208 * @falcon_id: LS falcon ID
209 * @lsb_offset: offset of the lsb_lsf_header in the WPR region
210 * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon
211 * @lazy_bootstrap: skip bootstrapping by ACR
212 * @status: bootstrapping status
214 * An array of these is written at the beginning of the WPR region, one for
215 * each managed falcon. The array is terminated by an instance which falcon_id
216 * is LSF_FALCON_ID_INVALID.
218 struct lsf_wpr_header {
224 #define LSF_IMAGE_STATUS_NONE 0
225 #define LSF_IMAGE_STATUS_COPY 1
226 #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2
227 #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3
228 #define LSF_IMAGE_STATUS_VALIDATION_DONE 4
229 #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5
230 #define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6
235 * struct ls_ucode_img_desc - descriptor of firmware image
236 * @descriptor_size: size of this descriptor
237 * @image_size: size of the whole image
238 * @bootloader_start_offset: start offset of the bootloader in ucode image
239 * @bootloader_size: size of the bootloader
240 * @bootloader_imem_offset: start off set of the bootloader in IMEM
241 * @bootloader_entry_point: entry point of the bootloader in IMEM
242 * @app_start_offset: start offset of the LS firmware
243 * @app_size: size of the LS firmware's code and data
244 * @app_imem_offset: offset of the app in IMEM
245 * @app_imem_entry: entry point of the app in IMEM
246 * @app_dmem_offset: offset of the data in DMEM
247 * @app_resident_code_offset: offset of app code from app_start_offset
248 * @app_resident_code_size: size of the code
249 * @app_resident_data_offset: offset of data from app_start_offset
250 * @app_resident_data_size: size of data
252 * A firmware image contains the code, data, and bootloader of a given LS
253 * falcon in a single blob. This structure describes where everything is.
255 * This can be generated from a (bootloader, code, data) set if they have
256 * been loaded separately, or come directly from a file.
258 struct ls_ucode_img_desc {
264 u32 bootloader_start_offset;
266 u32 bootloader_imem_offset;
267 u32 bootloader_entry_point;
268 u32 app_start_offset;
273 u32 app_resident_code_offset;
274 u32 app_resident_code_size;
275 u32 app_resident_data_offset;
276 u32 app_resident_data_size;
278 struct {u32 start; u32 size; } load_ovl[64];
283 * struct ls_ucode_img - temporary storage for loaded LS firmwares
284 * @node: to link within lsf_ucode_mgr
285 * @falcon_id: ID of the falcon this LS firmware is for
286 * @ucode_desc: loaded or generated map of ucode_data
287 * @ucode_header: header of the firmware
288 * @ucode_data: firmware payload (code and data)
289 * @ucode_size: size in bytes of data in ucode_data
290 * @wpr_header: WPR header to be written to the LS blob
291 * @lsb_header: LSB header to be written to the LS blob
293 * Preparing the WPR LS blob requires information about all the LS firmwares
294 * (size, etc) to be known. This structure contains all the data of one LS
297 struct ls_ucode_img {
298 struct list_head node;
299 enum nvkm_secboot_falcon falcon_id;
301 struct ls_ucode_img_desc ucode_desc;
306 struct lsf_wpr_header wpr_header;
307 struct lsf_lsb_header lsb_header;
311 * struct ls_ucode_mgr - manager for all LS falcon firmwares
312 * @count: number of managed LS falcons
313 * @wpr_size: size of the required WPR region in bytes
314 * @img_list: linked list of lsf_ucode_img
316 struct ls_ucode_mgr {
319 struct list_head img_list;
330 * struct hsf_fw_header - HS firmware descriptor
331 * @sig_dbg_offset: offset of the debug signature
332 * @sig_dbg_size: size of the debug signature
333 * @sig_prod_offset: offset of the production signature
334 * @sig_prod_size: size of the production signature
335 * @patch_loc: offset of the offset (sic) of where the signature is
336 * @patch_sig: offset of the offset (sic) to add to sig_*_offset
337 * @hdr_offset: offset of the load header (see struct hs_load_header)
338 * @hdr_size: size of above header
340 * This structure is embedded in the HS firmware image at
341 * hs_bin_hdr.header_offset.
343 struct hsf_fw_header {
355 * struct hsf_load_header - HS firmware load header
357 struct hsf_load_header {
358 u32 non_sec_code_off;
359 u32 non_sec_code_size;
370 * Convenience function to duplicate a firmware file in memory and check that
371 * it has the required minimum size.
374 gm200_secboot_load_firmware(struct nvkm_subdev *subdev, const char *name,
377 const struct firmware *fw;
381 ret = nvkm_firmware_get(subdev->device, name, &fw);
384 if (fw->size < min_size) {
385 nvkm_error(subdev, "%s is smaller than expected size %zu\n",
387 nvkm_firmware_put(fw);
388 return ERR_PTR(-EINVAL);
390 blob = kmemdup(fw->data, fw->size, GFP_KERNEL);
391 nvkm_firmware_put(fw);
393 return ERR_PTR(-ENOMEM);
400 * Low-secure blob creation
403 #define BL_DESC_BLK_SIZE 256
405 * Build a ucode image and descriptor from provided bootloader, code and data.
407 * @bl: bootloader image, including 16-bytes descriptor
408 * @code: LS firmware code segment
409 * @data: LS firmware data segment
410 * @desc: ucode descriptor to be written
412 * Return: allocated ucode image with corresponding descriptor information. desc
413 * is also updated to contain the right offsets within returned image.
416 ls_ucode_img_build(const struct firmware *bl, const struct firmware *code,
417 const struct firmware *data, struct ls_ucode_img_desc *desc)
419 struct fw_bin_header *bin_hdr = (void *)bl->data;
420 struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset;
421 void *bl_data = (void *)bl->data + bin_hdr->data_offset;
425 desc->bootloader_start_offset = pos;
426 desc->bootloader_size = ALIGN(bl_desc->code_size, sizeof(u32));
427 desc->bootloader_imem_offset = bl_desc->start_tag * 256;
428 desc->bootloader_entry_point = bl_desc->start_tag * 256;
430 pos = ALIGN(pos + desc->bootloader_size, BL_DESC_BLK_SIZE);
431 desc->app_start_offset = pos;
432 desc->app_size = ALIGN(code->size, BL_DESC_BLK_SIZE) +
433 ALIGN(data->size, BL_DESC_BLK_SIZE);
434 desc->app_imem_offset = 0;
435 desc->app_imem_entry = 0;
436 desc->app_dmem_offset = 0;
437 desc->app_resident_code_offset = 0;
438 desc->app_resident_code_size = ALIGN(code->size, BL_DESC_BLK_SIZE);
440 pos = ALIGN(pos + desc->app_resident_code_size, BL_DESC_BLK_SIZE);
441 desc->app_resident_data_offset = pos - desc->app_start_offset;
442 desc->app_resident_data_size = ALIGN(data->size, BL_DESC_BLK_SIZE);
444 desc->image_size = ALIGN(bl_desc->code_size, BL_DESC_BLK_SIZE) +
447 image = kzalloc(desc->image_size, GFP_KERNEL);
449 return ERR_PTR(-ENOMEM);
451 memcpy(image + desc->bootloader_start_offset, bl_data,
453 memcpy(image + desc->app_start_offset, code->data, code->size);
454 memcpy(image + desc->app_start_offset + desc->app_resident_data_offset,
455 data->data, data->size);
461 * ls_ucode_img_load_generic() - load and prepare a LS ucode image
463 * Load the LS microcode, bootloader and signature and pack them into a single
464 * blob. Also generate the corresponding ucode descriptor.
467 ls_ucode_img_load_generic(struct nvkm_subdev *subdev,
468 struct ls_ucode_img *img, const char *falcon_name,
471 const struct firmware *bl, *code, *data;
472 struct lsf_ucode_desc *lsf_desc;
476 img->ucode_header = NULL;
478 snprintf(f, sizeof(f), "gr/%s_bl", falcon_name);
479 ret = nvkm_firmware_get(subdev->device, f, &bl);
483 snprintf(f, sizeof(f), "gr/%s_inst", falcon_name);
484 ret = nvkm_firmware_get(subdev->device, f, &code);
488 snprintf(f, sizeof(f), "gr/%s_data", falcon_name);
489 ret = nvkm_firmware_get(subdev->device, f, &data);
493 img->ucode_data = ls_ucode_img_build(bl, code, data,
495 if (IS_ERR(img->ucode_data)) {
496 ret = PTR_ERR(img->ucode_data);
499 img->ucode_size = img->ucode_desc.image_size;
501 snprintf(f, sizeof(f), "gr/%s_sig", falcon_name);
502 lsf_desc = gm200_secboot_load_firmware(subdev, f, sizeof(*lsf_desc));
503 if (IS_ERR(lsf_desc)) {
504 ret = PTR_ERR(lsf_desc);
507 /* not needed? the signature should already have the right value */
508 lsf_desc->falcon_id = falcon_id;
509 memcpy(&img->lsb_header.signature, lsf_desc, sizeof(*lsf_desc));
510 img->falcon_id = lsf_desc->falcon_id;
513 /* success path - only free requested firmware files */
517 kfree(img->ucode_data);
519 nvkm_firmware_put(data);
521 nvkm_firmware_put(code);
523 nvkm_firmware_put(bl);
528 typedef int (*lsf_load_func)(struct nvkm_subdev *, struct ls_ucode_img *);
531 ls_ucode_img_load_fecs(struct nvkm_subdev *subdev, struct ls_ucode_img *img)
533 return ls_ucode_img_load_generic(subdev, img, "fecs",
534 NVKM_SECBOOT_FALCON_FECS);
538 ls_ucode_img_load_gpccs(struct nvkm_subdev *subdev, struct ls_ucode_img *img)
540 return ls_ucode_img_load_generic(subdev, img, "gpccs",
541 NVKM_SECBOOT_FALCON_GPCCS);
545 * ls_ucode_img_load() - create a lsf_ucode_img and load it
547 static struct ls_ucode_img *
548 ls_ucode_img_load(struct nvkm_subdev *subdev, lsf_load_func load_func)
550 struct ls_ucode_img *img;
553 img = kzalloc(sizeof(*img), GFP_KERNEL);
555 return ERR_PTR(-ENOMEM);
557 ret = load_func(subdev, img);
566 static const lsf_load_func lsf_load_funcs[] = {
567 [NVKM_SECBOOT_FALCON_END] = NULL, /* reserve enough space */
568 [NVKM_SECBOOT_FALCON_FECS] = ls_ucode_img_load_fecs,
569 [NVKM_SECBOOT_FALCON_GPCCS] = ls_ucode_img_load_gpccs,
573 * ls_ucode_img_populate_bl_desc() - populate a DMEM BL descriptor for LS image
574 * @img: ucode image to generate against
575 * @desc: descriptor to populate
576 * @sb: secure boot state to use for base addresses
578 * Populate the DMEM BL descriptor with the information contained in a
583 ls_ucode_img_populate_bl_desc(struct ls_ucode_img *img, u64 wpr_addr,
584 struct gm200_flcn_bl_desc *desc)
586 struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
589 addr_base = wpr_addr + img->lsb_header.ucode_off +
590 pdesc->app_start_offset;
592 memset(desc, 0, sizeof(*desc));
593 desc->ctx_dma = FALCON_DMAIDX_UCODE;
594 desc->code_dma_base.lo = lower_32_bits(
595 (addr_base + pdesc->app_resident_code_offset));
596 desc->code_dma_base.hi = upper_32_bits(
597 (addr_base + pdesc->app_resident_code_offset));
598 desc->non_sec_code_size = pdesc->app_resident_code_size;
599 desc->data_dma_base.lo = lower_32_bits(
600 (addr_base + pdesc->app_resident_data_offset));
601 desc->data_dma_base.hi = upper_32_bits(
602 (addr_base + pdesc->app_resident_data_offset));
603 desc->data_size = pdesc->app_resident_data_size;
604 desc->code_entry_point = pdesc->app_imem_entry;
607 #define LSF_LSB_HEADER_ALIGN 256
608 #define LSF_BL_DATA_ALIGN 256
609 #define LSF_BL_DATA_SIZE_ALIGN 256
610 #define LSF_BL_CODE_SIZE_ALIGN 256
611 #define LSF_UCODE_DATA_ALIGN 4096
614 * ls_ucode_img_fill_headers - fill the WPR and LSB headers of an image
615 * @gsb: secure boot device used
616 * @img: image to generate for
617 * @offset: offset in the WPR region where this image starts
619 * Allocate space in the WPR area from offset and write the WPR and LSB headers
622 * Return: offset at the end of this image.
625 ls_ucode_img_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_img *img,
628 struct lsf_wpr_header *whdr = &img->wpr_header;
629 struct lsf_lsb_header *lhdr = &img->lsb_header;
630 struct ls_ucode_img_desc *desc = &img->ucode_desc;
632 if (img->ucode_header) {
633 nvkm_fatal(&gsb->base.subdev,
634 "images withough loader are not supported yet!\n");
638 /* Fill WPR header */
639 whdr->falcon_id = img->falcon_id;
640 whdr->bootstrap_owner = gsb->base.func->boot_falcon;
641 whdr->status = LSF_IMAGE_STATUS_COPY;
643 /* Align, save off, and include an LSB header size */
644 offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN);
645 whdr->lsb_offset = offset;
646 offset += sizeof(struct lsf_lsb_header);
649 * Align, save off, and include the original (static) ucode
652 offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN);
653 lhdr->ucode_off = offset;
654 offset += img->ucode_size;
657 * For falcons that use a boot loader (BL), we append a loader
658 * desc structure on the end of the ucode image and consider
659 * this the boot loader data. The host will then copy the loader
660 * desc args to this space within the WPR region (before locking
661 * down) and the HS bin will then copy them to DMEM 0 for the
664 lhdr->bl_code_size = ALIGN(desc->bootloader_size,
665 LSF_BL_CODE_SIZE_ALIGN);
666 lhdr->ucode_size = ALIGN(desc->app_resident_data_offset,
667 LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size;
668 lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) +
669 lhdr->bl_code_size - lhdr->ucode_size;
671 * Though the BL is located at 0th offset of the image, the VA
672 * is different to make sure that it doesn't collide the actual
675 lhdr->bl_imem_off = desc->bootloader_imem_offset;
676 lhdr->app_code_off = desc->app_start_offset +
677 desc->app_resident_code_offset;
678 lhdr->app_code_size = desc->app_resident_code_size;
679 lhdr->app_data_off = desc->app_start_offset +
680 desc->app_resident_data_offset;
681 lhdr->app_data_size = desc->app_resident_data_size;
684 if (img->falcon_id == gsb->base.func->boot_falcon)
685 lhdr->flags = LSF_FLAG_DMACTL_REQ_CTX;
687 /* GPCCS will be loaded using PRI */
688 if (img->falcon_id == NVKM_SECBOOT_FALCON_GPCCS)
689 lhdr->flags |= LSF_FLAG_FORCE_PRIV_LOAD;
691 /* Align (size bloat) and save off BL descriptor size */
692 lhdr->bl_data_size = ALIGN(sizeof(struct gm200_flcn_bl_desc),
693 LSF_BL_DATA_SIZE_ALIGN);
695 * Align, save off, and include the additional BL data
697 offset = ALIGN(offset, LSF_BL_DATA_ALIGN);
698 lhdr->bl_data_off = offset;
699 offset += lhdr->bl_data_size;
705 ls_ucode_mgr_init(struct ls_ucode_mgr *mgr)
707 memset(mgr, 0, sizeof(*mgr));
708 INIT_LIST_HEAD(&mgr->img_list);
712 ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr)
714 struct ls_ucode_img *img, *t;
716 list_for_each_entry_safe(img, t, &mgr->img_list, node) {
717 kfree(img->ucode_data);
718 kfree(img->ucode_header);
724 ls_ucode_mgr_add_img(struct ls_ucode_mgr *mgr, struct ls_ucode_img *img)
727 list_add_tail(&img->node, &mgr->img_list);
731 * ls_ucode_mgr_fill_headers - fill WPR and LSB headers of all managed images
734 ls_ucode_mgr_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr)
736 struct ls_ucode_img *img;
740 * Start with an array of WPR headers at the base of the WPR.
741 * The expectation here is that the secure falcon will do a single DMA
742 * read of this array and cache it internally so it's ok to pack these.
743 * Also, we add 1 to the falcon count to indicate the end of the array.
745 offset = sizeof(struct lsf_wpr_header) * (mgr->count + 1);
748 * Walk the managed falcons, accounting for the LSB structs
749 * as well as the ucode images.
751 list_for_each_entry(img, &mgr->img_list, node) {
752 offset = ls_ucode_img_fill_headers(gsb, img, offset);
755 mgr->wpr_size = offset;
759 * ls_ucode_mgr_write_wpr - write the WPR blob contents
762 ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr,
763 struct nvkm_gpuobj *wpr_blob)
765 struct ls_ucode_img *img;
770 list_for_each_entry(img, &mgr->img_list, node) {
771 nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header,
772 sizeof(img->wpr_header));
774 nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset,
775 &img->lsb_header, sizeof(img->lsb_header));
777 /* Generate and write BL descriptor */
778 if (!img->ucode_header) {
779 u8 desc[gsb->func->bl_desc_size];
780 struct gm200_flcn_bl_desc gdesc;
782 ls_ucode_img_populate_bl_desc(img, gsb->wpr_addr,
784 gsb->func->fixup_bl_desc(&gdesc, &desc);
785 nvkm_gpuobj_memcpy_to(wpr_blob,
786 img->lsb_header.bl_data_off,
787 &desc, gsb->func->bl_desc_size);
791 nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off,
792 img->ucode_data, img->ucode_size);
794 pos += sizeof(img->wpr_header);
797 nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID);
804 /* Both size and address of WPR need to be 128K-aligned */
805 #define WPR_ALIGNMENT 0x20000
807 * gm200_secboot_prepare_ls_blob() - prepare the LS blob
809 * For each securely managed falcon, load the FW, signatures and bootloaders and
810 * prepare a ucode blob. Then, compute the offsets in the WPR region for each
811 * blob, and finally write the headers and ucode blobs into a GPU object that
812 * will be copied into the WPR region by the HS firmware.
815 gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb)
817 struct nvkm_secboot *sb = &gsb->base;
818 struct nvkm_device *device = sb->subdev.device;
819 struct ls_ucode_mgr mgr;
823 ls_ucode_mgr_init(&mgr);
825 /* Load all LS blobs */
826 for_each_set_bit(falcon_id, &gsb->base.func->managed_falcons,
827 NVKM_SECBOOT_FALCON_END) {
828 struct ls_ucode_img *img;
830 img = ls_ucode_img_load(&sb->subdev, lsf_load_funcs[falcon_id]);
836 ls_ucode_mgr_add_img(&mgr, img);
840 * Fill the WPR and LSF headers with the right offsets and compute
843 ls_ucode_mgr_fill_headers(gsb, &mgr);
844 mgr.wpr_size = ALIGN(mgr.wpr_size, WPR_ALIGNMENT);
846 /* Allocate GPU object that will contain the WPR region */
847 ret = nvkm_gpuobj_new(device, mgr.wpr_size, WPR_ALIGNMENT, false, NULL,
852 nvkm_debug(&sb->subdev, "%d managed LS falcons, WPR size is %d bytes\n",
853 mgr.count, mgr.wpr_size);
855 /* If WPR address and size are not fixed, set them to fit the LS blob */
856 if (!gsb->wpr_size) {
857 gsb->wpr_addr = gsb->ls_blob->addr;
858 gsb->wpr_size = gsb->ls_blob->size;
862 ret = ls_ucode_mgr_write_wpr(gsb, &mgr, gsb->ls_blob);
865 ls_ucode_mgr_cleanup(&mgr);
871 * High-secure blob creation
875 * gm200_secboot_hsf_patch_signature() - patch HS blob with correct signature
878 gm200_secboot_hsf_patch_signature(struct gm200_secboot *gsb, void *acr_image)
880 struct nvkm_secboot *sb = &gsb->base;
881 struct fw_bin_header *hsbin_hdr = acr_image;
882 struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset;
883 void *hs_data = acr_image + hsbin_hdr->data_offset;
887 /* Falcon in debug or production mode? */
888 if ((nvkm_rd32(sb->subdev.device, sb->base + 0xc08) >> 20) & 0x1) {
889 sig = acr_image + fw_hdr->sig_dbg_offset;
890 sig_size = fw_hdr->sig_dbg_size;
892 sig = acr_image + fw_hdr->sig_prod_offset;
893 sig_size = fw_hdr->sig_prod_size;
896 /* Patch signature */
897 memcpy(hs_data + fw_hdr->patch_loc, sig + fw_hdr->patch_sig, sig_size);
901 * gm200_secboot_populate_hsf_bl_desc() - populate BL descriptor for HS image
904 gm200_secboot_populate_hsf_bl_desc(void *acr_image,
905 struct gm200_flcn_bl_desc *bl_desc)
907 struct fw_bin_header *hsbin_hdr = acr_image;
908 struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset;
909 struct hsf_load_header *load_hdr = acr_image + fw_hdr->hdr_offset;
912 * Descriptor for the bootloader that will load the ACR image into
915 fw_hdr = acr_image + hsbin_hdr->header_offset;
916 load_hdr = acr_image + fw_hdr->hdr_offset;
917 memset(bl_desc, 0, sizeof(*bl_desc));
918 bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
919 bl_desc->non_sec_code_off = load_hdr->non_sec_code_off;
920 bl_desc->non_sec_code_size = load_hdr->non_sec_code_size;
921 bl_desc->sec_code_off = load_hdr->app[0].sec_code_off;
922 bl_desc->sec_code_size = load_hdr->app[0].sec_code_size;
923 bl_desc->code_entry_point = 0;
925 * We need to set code_dma_base to the virtual address of the acr_blob,
926 * and add this address to data_dma_base before writing it into DMEM
928 bl_desc->code_dma_base.lo = 0;
929 bl_desc->data_dma_base.lo = load_hdr->data_dma_base;
930 bl_desc->data_size = load_hdr->data_size;
934 * gm200_secboot_prepare_hs_blob - load and prepare a HS blob and BL descriptor
936 * @gsb secure boot instance to prepare for
937 * @fw name of the HS firmware to load
938 * @blob pointer to gpuobj that will be allocated to receive the HS FW payload
939 * @bl_desc pointer to the BL descriptor to write for this firmware
940 * @patch whether we should patch the HS descriptor (only for HS loaders)
943 gm200_secboot_prepare_hs_blob(struct gm200_secboot *gsb, const char *fw,
944 struct nvkm_gpuobj **blob,
945 struct gm200_flcn_bl_desc *bl_desc, bool patch)
947 struct nvkm_subdev *subdev = &gsb->base.subdev;
949 struct fw_bin_header *hsbin_hdr;
950 struct hsf_fw_header *fw_hdr;
952 struct hsf_load_header *load_hdr;
953 struct hsflcn_acr_desc *desc;
956 acr_image = gm200_secboot_load_firmware(subdev, fw, 0);
957 if (IS_ERR(acr_image))
958 return PTR_ERR(acr_image);
959 hsbin_hdr = acr_image;
961 /* Patch signature */
962 gm200_secboot_hsf_patch_signature(gsb, acr_image);
964 acr_data = acr_image + hsbin_hdr->data_offset;
966 /* Patch descriptor? */
968 fw_hdr = acr_image + hsbin_hdr->header_offset;
969 load_hdr = acr_image + fw_hdr->hdr_offset;
970 desc = acr_data + load_hdr->data_dma_base;
971 gsb->func->fixup_hs_desc(gsb, desc);
974 /* Generate HS BL descriptor */
975 gm200_secboot_populate_hsf_bl_desc(acr_image, bl_desc);
977 /* Create ACR blob and copy HS data to it */
978 ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256),
979 0x1000, false, NULL, blob);
984 nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size);
994 * High-secure bootloader blob creation
998 gm200_secboot_prepare_hsbl_blob(struct gm200_secboot *gsb)
1000 struct nvkm_subdev *subdev = &gsb->base.subdev;
1002 gsb->hsbl_blob = gm200_secboot_load_firmware(subdev, "acr/bl", 0);
1003 if (IS_ERR(gsb->hsbl_blob)) {
1004 int ret = PTR_ERR(gsb->hsbl_blob);
1006 gsb->hsbl_blob = NULL;
1014 * gm20x_secboot_prepare_blobs - load blobs common to all GM20X GPUs.
1016 * This includes the LS blob, HS ucode loading blob, and HS bootloader.
1018 * The HS ucode unload blob is only used on dGPU.
1021 gm20x_secboot_prepare_blobs(struct gm200_secboot *gsb)
1025 /* Load and prepare the managed falcon's firmwares */
1026 ret = gm200_secboot_prepare_ls_blob(gsb);
1030 /* Load the HS firmware that will load the LS firmwares */
1031 ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_load",
1032 &gsb->acr_load_blob,
1033 &gsb->acr_load_bl_desc, true);
1037 /* Load the HS firmware bootloader */
1038 ret = gm200_secboot_prepare_hsbl_blob(gsb);
1046 gm200_secboot_prepare_blobs(struct nvkm_secboot *sb)
1048 struct gm200_secboot *gsb = gm200_secboot(sb);
1051 ret = gm20x_secboot_prepare_blobs(gsb);
1055 /* dGPU only: load the HS firmware that unprotects the WPR region */
1056 ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_unload",
1057 &gsb->acr_unload_blob,
1058 &gsb->acr_unload_bl_desc, false);
1068 * Secure Boot Execution
1072 * gm200_secboot_load_hs_bl() - load HS bootloader into DMEM and IMEM
1075 gm200_secboot_load_hs_bl(struct gm200_secboot *gsb, void *data, u32 data_size)
1077 struct nvkm_device *device = gsb->base.subdev.device;
1078 struct fw_bin_header *hdr = gsb->hsbl_blob;
1079 struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset;
1080 void *blob_data = gsb->hsbl_blob + hdr->data_offset;
1081 void *hsbl_code = blob_data + hsbl_desc->code_off;
1082 void *hsbl_data = blob_data + hsbl_desc->data_off;
1083 u32 code_size = ALIGN(hsbl_desc->code_size, 256);
1084 const u32 base = gsb->base.base;
1090 * Copy HS bootloader data
1092 nvkm_wr32(device, base + 0x1c0, (0x00000000 | (0x1 << 24)));
1093 for (i = 0; i < hsbl_desc->data_size / 4; i++)
1094 nvkm_wr32(device, base + 0x1c4, ((u32 *)hsbl_data)[i]);
1097 * Copy HS bootloader interface structure where the HS descriptor
1100 nvkm_wr32(device, base + 0x1c0,
1101 (hsbl_desc->dmem_load_off | (0x1 << 24)));
1102 for (i = 0; i < data_size / 4; i++)
1103 nvkm_wr32(device, base + 0x1c4, ((u32 *)data)[i]);
1105 /* Copy HS bootloader code to end of IMEM */
1106 blk = (nvkm_rd32(device, base + 0x108) & 0x1ff) - (code_size >> 8);
1107 tag = hsbl_desc->start_tag;
1108 nvkm_wr32(device, base + 0x180, ((blk & 0xff) << 8) | (0x1 << 24));
1109 for (i = 0; i < code_size / 4; i++) {
1110 /* write new tag every 256B */
1111 if ((i & 0x3f) == 0) {
1112 nvkm_wr32(device, base + 0x188, tag & 0xffff);
1115 nvkm_wr32(device, base + 0x184, ((u32 *)hsbl_code)[i]);
1117 nvkm_wr32(device, base + 0x188, 0);
1121 * gm200_secboot_setup_falcon() - set up the secure falcon for secure boot
1124 gm200_secboot_setup_falcon(struct gm200_secboot *gsb)
1126 struct nvkm_device *device = gsb->base.subdev.device;
1127 struct fw_bin_header *hdr = gsb->hsbl_blob;
1128 struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset;
1129 /* virtual start address for boot vector */
1130 u32 virt_addr = hsbl_desc->start_tag << 8;
1131 const u32 base = gsb->base.base;
1132 const u32 reg_base = base + 0xe00;
1136 ret = nvkm_secboot_falcon_reset(&gsb->base);
1140 /* setup apertures - virtual */
1141 nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_UCODE), 0x4);
1142 nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_VIRT), 0x0);
1143 /* setup apertures - physical */
1144 nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_VID), 0x4);
1145 nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_SYS_COH),
1147 nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_SYS_NCOH),
1151 if (nvkm_memory_target(gsb->inst->memory) == NVKM_MEM_TARGET_VRAM)
1152 inst_loc = 0x0; /* FB */
1154 inst_loc = 0x3; /* Non-coherent sysmem */
1156 nvkm_mask(device, base + 0x048, 0x1, 0x1);
1157 nvkm_wr32(device, base + 0x480,
1158 ((gsb->inst->addr >> 12) & 0xfffffff) |
1159 (inst_loc << 28) | (1 << 30));
1161 /* Set boot vector to code's starting virtual address */
1162 nvkm_wr32(device, base + 0x104, virt_addr);
1168 * gm200_secboot_run_hs_blob() - run the given high-secure blob
1171 gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob,
1172 struct gm200_flcn_bl_desc *desc)
1174 struct nvkm_vma vma;
1176 const u32 bl_desc_size = gsb->func->bl_desc_size;
1177 u8 bl_desc[bl_desc_size];
1180 /* Map the HS firmware so the HS bootloader can see it */
1181 ret = nvkm_gpuobj_map(blob, gsb->vm, NV_MEM_ACCESS_RW, &vma);
1185 /* Add the mapping address to the DMA bases */
1186 vma_addr = flcn64_to_u64(desc->code_dma_base) + vma.offset;
1187 desc->code_dma_base.lo = lower_32_bits(vma_addr);
1188 desc->code_dma_base.hi = upper_32_bits(vma_addr);
1189 vma_addr = flcn64_to_u64(desc->data_dma_base) + vma.offset;
1190 desc->data_dma_base.lo = lower_32_bits(vma_addr);
1191 desc->data_dma_base.hi = upper_32_bits(vma_addr);
1193 /* Fixup the BL header */
1194 gsb->func->fixup_bl_desc(desc, &bl_desc);
1196 /* Reset the falcon and make it ready to run the HS bootloader */
1197 ret = gm200_secboot_setup_falcon(gsb);
1201 /* Load the HS bootloader into the falcon's IMEM/DMEM */
1202 gm200_secboot_load_hs_bl(gsb, &bl_desc, bl_desc_size);
1204 /* Start the HS bootloader */
1205 ret = nvkm_secboot_falcon_run(&gsb->base);
1210 /* Restore the original DMA addresses */
1211 vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset;
1212 desc->code_dma_base.lo = lower_32_bits(vma_addr);
1213 desc->code_dma_base.hi = upper_32_bits(vma_addr);
1214 vma_addr = flcn64_to_u64(desc->data_dma_base) - vma.offset;
1215 desc->data_dma_base.lo = lower_32_bits(vma_addr);
1216 desc->data_dma_base.hi = upper_32_bits(vma_addr);
1218 /* We don't need the ACR firmware anymore */
1219 nvkm_gpuobj_unmap(&vma);
1225 * gm200_secboot_reset() - execute secure boot from the prepared state
1227 * Load the HS bootloader and ask the falcon to run it. This will in turn
1228 * load the HS firmware and run it, so once the falcon stops all the managed
1229 * falcons should have their LS firmware loaded and be ready to run.
1232 gm200_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon)
1234 struct gm200_secboot *gsb = gm200_secboot(sb);
1238 * Dummy GM200 implementation: perform secure boot each time we are
1239 * called on FECS. Since only FECS and GPCCS are managed and started
1240 * together, this ought to be safe.
1242 * Once we have proper PMU firmware and support, this will be changed
1243 * to a proper call to the PMU method.
1245 if (falcon != NVKM_SECBOOT_FALCON_FECS)
1248 /* If WPR is set and we have an unload blob, run it to unlock WPR */
1249 if (gsb->acr_unload_blob &&
1250 gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) {
1251 ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob,
1252 &gsb->acr_unload_bl_desc);
1257 /* Reload all managed falcons */
1258 ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_load_blob,
1259 &gsb->acr_load_bl_desc);
1264 gsb->falcon_state[falcon] = RESET;
1269 gm200_secboot_start(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon)
1271 struct gm200_secboot *gsb = gm200_secboot(sb);
1275 case NVKM_SECBOOT_FALCON_FECS:
1278 case NVKM_SECBOOT_FALCON_GPCCS:
1282 nvkm_error(&sb->subdev, "cannot start unhandled falcon!\n");
1286 nvkm_wr32(sb->subdev.device, base + 0x130, 0x00000002);
1287 gsb->falcon_state[falcon] = RUNNING;
1295 gm200_secboot_init(struct nvkm_secboot *sb)
1297 struct gm200_secboot *gsb = gm200_secboot(sb);
1298 struct nvkm_device *device = sb->subdev.device;
1300 const u64 vm_area_len = 600 * 1024;
1303 /* Allocate instance block and VM */
1304 ret = nvkm_gpuobj_new(device, 0x1000, 0, true, NULL, &gsb->inst);
1308 ret = nvkm_gpuobj_new(device, 0x8000, 0, true, NULL, &gsb->pgd);
1312 ret = nvkm_vm_new(device, 0, vm_area_len, 0, NULL, &vm);
1316 atomic_inc(&vm->engref[NVKM_SUBDEV_PMU]);
1318 ret = nvkm_vm_ref(vm, &gsb->vm, gsb->pgd);
1319 nvkm_vm_ref(NULL, &vm, NULL);
1323 nvkm_kmap(gsb->inst);
1324 nvkm_wo32(gsb->inst, 0x200, lower_32_bits(gsb->pgd->addr));
1325 nvkm_wo32(gsb->inst, 0x204, upper_32_bits(gsb->pgd->addr));
1326 nvkm_wo32(gsb->inst, 0x208, lower_32_bits(vm_area_len - 1));
1327 nvkm_wo32(gsb->inst, 0x20c, upper_32_bits(vm_area_len - 1));
1328 nvkm_done(gsb->inst);
1334 gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend)
1336 struct gm200_secboot *gsb = gm200_secboot(sb);
1340 /* Run the unload blob to unprotect the WPR region */
1341 if (gsb->acr_unload_blob &&
1342 gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE)
1343 ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob,
1344 &gsb->acr_unload_bl_desc);
1346 for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++)
1347 gsb->falcon_state[i] = NON_SECURE;
1353 gm200_secboot_dtor(struct nvkm_secboot *sb)
1355 struct gm200_secboot *gsb = gm200_secboot(sb);
1357 nvkm_gpuobj_del(&gsb->acr_unload_blob);
1359 kfree(gsb->hsbl_blob);
1360 nvkm_gpuobj_del(&gsb->acr_load_blob);
1361 nvkm_gpuobj_del(&gsb->ls_blob);
1363 nvkm_vm_ref(NULL, &gsb->vm, gsb->pgd);
1364 nvkm_gpuobj_del(&gsb->pgd);
1365 nvkm_gpuobj_del(&gsb->inst);
1371 static const struct nvkm_secboot_func
1373 .dtor = gm200_secboot_dtor,
1374 .init = gm200_secboot_init,
1375 .fini = gm200_secboot_fini,
1376 .prepare_blobs = gm200_secboot_prepare_blobs,
1377 .reset = gm200_secboot_reset,
1378 .start = gm200_secboot_start,
1379 .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS) |
1380 BIT(NVKM_SECBOOT_FALCON_GPCCS),
1381 .boot_falcon = NVKM_SECBOOT_FALCON_PMU,
1385 * gm200_fixup_bl_desc - just copy the BL descriptor
1387 * Use the GM200 descriptor format by default.
1390 gm200_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret)
1392 memcpy(ret, desc, sizeof(*desc));
1396 gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb,
1397 struct hsflcn_acr_desc *desc)
1399 desc->ucode_blob_base = gsb->ls_blob->addr;
1400 desc->ucode_blob_size = gsb->ls_blob->size;
1402 desc->wpr_offset = 0;
1404 /* WPR region information for the HS binary to set up */
1405 desc->wpr_region_id = 1;
1406 desc->regions.no_regions = 1;
1407 desc->regions.region_props[0].region_id = 1;
1408 desc->regions.region_props[0].start_addr = gsb->wpr_addr >> 8;
1409 desc->regions.region_props[0].end_addr =
1410 (gsb->wpr_addr + gsb->wpr_size) >> 8;
1413 static const struct gm200_secboot_func
1414 gm200_secboot_func = {
1415 .bl_desc_size = sizeof(struct gm200_flcn_bl_desc),
1416 .fixup_bl_desc = gm200_secboot_fixup_bl_desc,
1417 .fixup_hs_desc = gm200_secboot_fixup_hs_desc,
1421 gm200_secboot_new(struct nvkm_device *device, int index,
1422 struct nvkm_secboot **psb)
1425 struct gm200_secboot *gsb;
1427 gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
1434 ret = nvkm_secboot_ctor(&gm200_secboot, device, index, &gsb->base);
1438 gsb->func = &gm200_secboot_func;
1443 MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
1444 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
1445 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
1446 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
1447 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
1448 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
1449 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
1450 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
1451 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
1452 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
1453 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
1454 MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
1455 MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
1456 MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
1457 MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
1459 MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
1460 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
1461 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
1462 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
1463 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
1464 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
1465 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
1466 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
1467 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
1468 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
1469 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
1470 MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
1471 MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
1472 MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
1473 MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
1475 MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
1476 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
1477 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
1478 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
1479 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
1480 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
1481 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
1482 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
1483 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
1484 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
1485 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
1486 MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
1487 MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
1488 MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
1489 MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");