2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
34 #ifdef DSS_SUBSYS_NAME
35 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
37 #define pr_fmt(fmt) fmt
40 #define DSSDBG(format, ...) \
41 pr_debug(format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSERR(format, ...) \
45 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
48 #define DSSERR(format, ...) \
49 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
52 #ifdef DSS_SUBSYS_NAME
53 #define DSSINFO(format, ...) \
54 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
57 #define DSSINFO(format, ...) \
58 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
61 #ifdef DSS_SUBSYS_NAME
62 #define DSSWARN(format, ...) \
63 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
66 #define DSSWARN(format, ...) \
67 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
70 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
71 number. For example 7:0 */
72 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
73 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
74 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
75 #define FLD_MOD(orig, val, start, end) \
76 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
78 enum dss_io_pad_mode {
79 DSS_IO_PAD_MODE_RESET,
81 DSS_IO_PAD_MODE_BYPASS,
84 enum dss_hdmi_venc_clk_source_select {
89 enum dss_dsi_content_type {
91 DSS_DSI_CONTENT_GENERIC,
94 enum dss_writeback_channel {
105 enum dss_clk_source {
106 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
108 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
109 * OMAP4: PLL1_CLK1 */
110 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
111 * OMAP4: PLL1_CLK2 */
112 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
113 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
126 #define DSS_PLL_MAX_HSDIVS 4
129 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
130 * Type-B PLLs: clkout[0] refers to m2.
132 struct dss_pll_clock_info {
133 /* rates that we get with dividers below */
135 unsigned long clkdco;
136 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
142 u16 mX[DSS_PLL_MAX_HSDIVS];
147 int (*enable)(struct dss_pll *pll);
148 void (*disable)(struct dss_pll *pll);
149 int (*set_config)(struct dss_pll *pll,
150 const struct dss_pll_clock_info *cinfo);
159 unsigned long fint_min, fint_max;
160 unsigned long clkdco_min, clkdco_low, clkdco_max;
164 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
177 struct regulator *regulator;
181 const struct dss_pll_hw *hw;
183 const struct dss_pll_ops *ops;
185 struct dss_pll_clock_info cinfo;
188 struct dispc_clock_info {
189 /* rates that we get with dividers below */
198 struct dss_lcd_mgr_config {
199 enum dss_io_pad_mode io_pad_mode;
204 struct dispc_clock_info clock_info;
206 int video_port_width;
208 int lcden_sig_polarity;
212 struct platform_device;
215 struct platform_device *dss_get_core_pdev(void);
216 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
217 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
218 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
219 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
221 static inline bool dss_mgr_is_lcd(enum omap_channel id)
223 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
224 id == OMAP_DSS_CHANNEL_LCD3)
231 int dss_init_platform_driver(void) __init;
232 void dss_uninit_platform_driver(void);
234 int dss_runtime_get(void);
235 void dss_runtime_put(void);
237 unsigned long dss_get_dispc_clk_rate(void);
238 int dss_dpi_select_source(int port, enum omap_channel channel);
239 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
240 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
241 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
242 void dss_dump_clocks(struct seq_file *s);
245 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
246 struct regulator *regulator);
247 void dss_video_pll_uninit(struct dss_pll *pll);
250 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
251 u32 dss_of_port_get_port_number(struct device_node *port);
253 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
254 void dss_debug_dump_clocks(struct seq_file *s);
257 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
258 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
259 enum omap_channel channel);
261 void dss_sdi_init(int datapairs);
262 int dss_sdi_enable(void);
263 void dss_sdi_disable(void);
265 void dss_select_dsi_clk_source(int dsi_module,
266 enum dss_clk_source clk_src);
267 void dss_select_lcd_clk_source(enum omap_channel channel,
268 enum dss_clk_source clk_src);
269 enum dss_clk_source dss_get_dispc_clk_source(void);
270 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
271 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
273 void dss_set_venc_output(enum omap_dss_venc_type type);
274 void dss_set_dac_pwrdn_bgz(bool enable);
276 int dss_set_fck_rate(unsigned long rate);
278 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
279 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
280 dss_div_calc_func func, void *data);
283 int sdi_init_platform_driver(void) __init;
284 void sdi_uninit_platform_driver(void);
286 #ifdef CONFIG_OMAP2_DSS_SDI
287 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
288 void sdi_uninit_port(struct device_node *port);
290 static inline int sdi_init_port(struct platform_device *pdev,
291 struct device_node *port)
295 static inline void sdi_uninit_port(struct device_node *port)
302 #ifdef CONFIG_OMAP2_DSS_DSI
305 struct file_operations;
307 int dsi_init_platform_driver(void) __init;
308 void dsi_uninit_platform_driver(void);
310 void dsi_dump_clocks(struct seq_file *s);
312 void dsi_irq_handler(void);
313 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
316 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
318 WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
325 int dpi_init_platform_driver(void) __init;
326 void dpi_uninit_platform_driver(void);
328 #ifdef CONFIG_OMAP2_DSS_DPI
329 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
330 void dpi_uninit_port(struct device_node *port);
332 static inline int dpi_init_port(struct platform_device *pdev,
333 struct device_node *port)
337 static inline void dpi_uninit_port(struct device_node *port)
343 int dispc_init_platform_driver(void) __init;
344 void dispc_uninit_platform_driver(void);
345 void dispc_dump_clocks(struct seq_file *s);
347 void dispc_enable_sidle(void);
348 void dispc_disable_sidle(void);
350 void dispc_lcd_enable_signal(bool enable);
351 void dispc_pck_free_enable(bool enable);
352 void dispc_enable_fifomerge(bool enable);
353 void dispc_enable_gamma_table(bool enable);
355 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
356 unsigned long pck, void *data);
357 bool dispc_div_calc(unsigned long dispc,
358 unsigned long pck_min, unsigned long pck_max,
359 dispc_div_calc_func func, void *data);
361 bool dispc_mgr_timings_ok(enum omap_channel channel,
362 const struct omap_video_timings *timings);
363 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
364 struct dispc_clock_info *cinfo);
367 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
368 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
369 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
372 void dispc_mgr_set_clock_div(enum omap_channel channel,
373 const struct dispc_clock_info *cinfo);
374 int dispc_mgr_get_clock_div(enum omap_channel channel,
375 struct dispc_clock_info *cinfo);
376 void dispc_set_tv_pclk(unsigned long pclk);
378 u32 dispc_wb_get_framedone_irq(void);
379 bool dispc_wb_go_busy(void);
380 void dispc_wb_go(void);
381 void dispc_wb_enable(bool enable);
382 bool dispc_wb_is_enabled(void);
383 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
384 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
385 bool mem_to_mem, const struct omap_video_timings *timings);
388 int venc_init_platform_driver(void) __init;
389 void venc_uninit_platform_driver(void);
392 int hdmi4_init_platform_driver(void) __init;
393 void hdmi4_uninit_platform_driver(void);
395 int hdmi5_init_platform_driver(void) __init;
396 void hdmi5_uninit_platform_driver(void);
399 int rfbi_init_platform_driver(void) __init;
400 void rfbi_uninit_platform_driver(void);
403 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
404 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
407 for (b = 0; b < 32; ++b) {
408 if (irqstatus & (1 << b))
415 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
416 unsigned long clkdco, void *data);
417 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
420 int dss_pll_register(struct dss_pll *pll);
421 void dss_pll_unregister(struct dss_pll *pll);
422 struct dss_pll *dss_pll_find(const char *name);
423 int dss_pll_enable(struct dss_pll *pll);
424 void dss_pll_disable(struct dss_pll *pll);
425 int dss_pll_set_config(struct dss_pll *pll,
426 const struct dss_pll_clock_info *cinfo);
428 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
429 unsigned long out_min, unsigned long out_max,
430 dss_hsdiv_calc_func func, void *data);
431 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
432 unsigned long pll_min, unsigned long pll_max,
433 dss_pll_calc_func func, void *data);
434 int dss_pll_write_config_type_a(struct dss_pll *pll,
435 const struct dss_pll_clock_info *cinfo);
436 int dss_pll_write_config_type_b(struct dss_pll *pll,
437 const struct dss_pll_clock_info *cinfo);
438 int dss_pll_wait_reset_done(struct dss_pll *pll);