drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86         struct radeon_encoder *radeon_encoder =
  87                 to_radeon_encoder(radeon_crtc->encoder);
  88         /* fixme - fill in enc_priv for atom dac */
  89         enum radeon_tv_std tv_std = TV_STD_NTSC;
  90         bool is_tv = false, is_cv = false;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  96                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  97                 tv_std = tv_dac->tv_std;
  98                 is_tv = true;
  99         }
 100
 101         memset(&args, 0, sizeof(args));
 102
 103         args.ucScaler = radeon_crtc->crtc_id;
 104
 105         if (is_tv) {
 106                 switch (tv_std) {
 107                 case TV_STD_NTSC:
 108                 default:
 109                         args.ucTVStandard = ATOM_TV_NTSC;
 110                         break;
 111                 case TV_STD_PAL:
 112                         args.ucTVStandard = ATOM_TV_PAL;
 113                         break;
 114                 case TV_STD_PAL_M:
 115                         args.ucTVStandard = ATOM_TV_PALM;
 116                         break;
 117                 case TV_STD_PAL_60:
 118                         args.ucTVStandard = ATOM_TV_PAL60;
 119                         break;
 120                 case TV_STD_NTSC_J:
 121                         args.ucTVStandard = ATOM_TV_NTSCJ;
 122                         break;
 123                 case TV_STD_SCART_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 125                         break;
 126                 case TV_STD_SECAM:
 127                         args.ucTVStandard = ATOM_TV_SECAM;
 128                         break;
 129                 case TV_STD_PAL_CN:
 130                         args.ucTVStandard = ATOM_TV_PALCN;
 131                         break;
 132                 }
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else if (is_cv) {
 135                 args.ucTVStandard = ATOM_TV_CV;
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else {
 138                 switch (radeon_crtc->rmx_type) {
 139                 case RMX_FULL:
 140                         args.ucEnable = ATOM_SCALER_EXPANSION;
 141                         break;
 142                 case RMX_CENTER:
 143                         args.ucEnable = ATOM_SCALER_CENTER;
 144                         break;
 145                 case RMX_ASPECT:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 default:
 149                         if (ASIC_IS_AVIVO(rdev))
 150                                 args.ucEnable = ATOM_SCALER_DISABLE;
 151                         else
 152                                 args.ucEnable = ATOM_SCALER_CENTER;
 153                         break;
 154                 }
 155         }
 156         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 157         if ((is_tv || is_cv)
 158             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 159                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 160         }
 161 }
 162
 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 164 {
 165         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 166         struct drm_device *dev = crtc->dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168         int index =
 169             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 170         ENABLE_CRTC_PS_ALLOCATION args;
 171
 172         memset(&args, 0, sizeof(args));
 173
 174         args.ucCRTC = radeon_crtc->crtc_id;
 175         args.ucEnable = lock;
 176
 177         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 178 }
 179
 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 181 {
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 183         struct drm_device *dev = crtc->dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 186         ENABLE_CRTC_PS_ALLOCATION args;
 187
 188         memset(&args, 0, sizeof(args));
 189
 190         args.ucCRTC = radeon_crtc->crtc_id;
 191         args.ucEnable = state;
 192
 193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 194 }
 195
 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 202         ENABLE_CRTC_PS_ALLOCATION args;
 203
 204         memset(&args, 0, sizeof(args));
 205
 206         args.ucCRTC = radeon_crtc->crtc_id;
 207         args.ucEnable = state;
 208
 209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 210 }
 211
 212 static const u32 vga_control_regs[6] =
 213 {
 214         AVIVO_D1VGA_CONTROL,
 215         AVIVO_D2VGA_CONTROL,
 216         EVERGREEN_D3VGA_CONTROL,
 217         EVERGREEN_D4VGA_CONTROL,
 218         EVERGREEN_D5VGA_CONTROL,
 219         EVERGREEN_D6VGA_CONTROL,
 220 };
 221
 222 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 223 {
 224         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 225         struct drm_device *dev = crtc->dev;
 226         struct radeon_device *rdev = dev->dev_private;
 227         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 228         BLANK_CRTC_PS_ALLOCATION args;
 229         u32 vga_control = 0;
 230
 231         memset(&args, 0, sizeof(args));
 232
 233         if (ASIC_IS_DCE8(rdev)) {
 234                 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
 235                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
 236         }
 237
 238         args.ucCRTC = radeon_crtc->crtc_id;
 239         args.ucBlanking = state;
 240
 241         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 242
 243         if (ASIC_IS_DCE8(rdev)) {
 244                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
 245         }
 246 }
 247
 248 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 249 {
 250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 251         struct drm_device *dev = crtc->dev;
 252         struct radeon_device *rdev = dev->dev_private;
 253         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 254         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 255
 256         memset(&args, 0, sizeof(args));
 257
 258         args.ucDispPipeId = radeon_crtc->crtc_id;
 259         args.ucEnable = state;
 260
 261         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 262 }
 263
 264 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 265 {
 266         struct drm_device *dev = crtc->dev;
 267         struct radeon_device *rdev = dev->dev_private;
 268         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 269
 270         switch (mode) {
 271         case DRM_MODE_DPMS_ON:
 272                 radeon_crtc->enabled = true;
 273                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 274                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 275                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 276                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 277                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 278                 radeon_crtc_load_lut(crtc);
 279                 break;
 280         case DRM_MODE_DPMS_STANDBY:
 281         case DRM_MODE_DPMS_SUSPEND:
 282         case DRM_MODE_DPMS_OFF:
 283                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 284                 if (radeon_crtc->enabled)
 285                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 286                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 287                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 288                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 289                 radeon_crtc->enabled = false;
 290                 break;
 291         }
 292         /* adjust pm to dpms */
 293         radeon_pm_compute_clocks(rdev);
 294 }
 295
 296 static void
 297 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 298                              struct drm_display_mode *mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 304         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 305         u16 misc = 0;
 306
 307         memset(&args, 0, sizeof(args));
 308         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 309         args.usH_Blanking_Time =
 310                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 311         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 312         args.usV_Blanking_Time =
 313                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 314         args.usH_SyncOffset =
 315                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 316         args.usH_SyncWidth =
 317                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 318         args.usV_SyncOffset =
 319                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 320         args.usV_SyncWidth =
 321                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 322         args.ucH_Border = radeon_crtc->h_border;
 323         args.ucV_Border = radeon_crtc->v_border;
 324
 325         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 326                 misc |= ATOM_VSYNC_POLARITY;
 327         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 328                 misc |= ATOM_HSYNC_POLARITY;
 329         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 330                 misc |= ATOM_COMPOSITESYNC;
 331         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 332                 misc |= ATOM_INTERLACE;
 333         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 334                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 335
 336         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 337         args.ucCRTC = radeon_crtc->crtc_id;
 338
 339         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 340 }
 341
 342 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 343                                      struct drm_display_mode *mode)
 344 {
 345         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 346         struct drm_device *dev = crtc->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 349         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 350         u16 misc = 0;
 351
 352         memset(&args, 0, sizeof(args));
 353         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 354         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 355         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 356         args.usH_SyncWidth =
 357                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 358         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 359         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 360         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 361         args.usV_SyncWidth =
 362                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 363
 364         args.ucOverscanRight = radeon_crtc->h_border;
 365         args.ucOverscanLeft = radeon_crtc->h_border;
 366         args.ucOverscanBottom = radeon_crtc->v_border;
 367         args.ucOverscanTop = radeon_crtc->v_border;
 368
 369         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 370                 misc |= ATOM_VSYNC_POLARITY;
 371         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 372                 misc |= ATOM_HSYNC_POLARITY;
 373         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 374                 misc |= ATOM_COMPOSITESYNC;
 375         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 376                 misc |= ATOM_INTERLACE;
 377         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 378                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 379
 380         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 381         args.ucCRTC = radeon_crtc->crtc_id;
 382
 383         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 384 }
 385
 386 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 387 {
 388         u32 ss_cntl;
 389
 390         if (ASIC_IS_DCE4(rdev)) {
 391                 switch (pll_id) {
 392                 case ATOM_PPLL1:
 393                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 394                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 395                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 396                         break;
 397                 case ATOM_PPLL2:
 398                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 399                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 400                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 401                         break;
 402                 case ATOM_DCPLL:
 403                 case ATOM_PPLL_INVALID:
 404                         return;
 405                 }
 406         } else if (ASIC_IS_AVIVO(rdev)) {
 407                 switch (pll_id) {
 408                 case ATOM_PPLL1:
 409                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 410                         ss_cntl &= ~1;
 411                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 412                         break;
 413                 case ATOM_PPLL2:
 414                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 415                         ss_cntl &= ~1;
 416                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 417                         break;
 418                 case ATOM_DCPLL:
 419                 case ATOM_PPLL_INVALID:
 420                         return;
 421                 }
 422         }
 423 }
 424
 425
 426 union atom_enable_ss {
 427         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 428         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 429         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 430         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 431         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 432 };
 433
 434 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 435                                      int enable,
 436                                      int pll_id,
 437                                      int crtc_id,
 438                                      struct radeon_atom_ss *ss)
 439 {
 440         unsigned i;
 441         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 442         union atom_enable_ss args;
 443
 444         if (enable) {
 445                 /* Don't mess with SS if percentage is 0 or external ss.
 446                  * SS is already disabled previously, and disabling it
 447                  * again can cause display problems if the pll is already
 448                  * programmed.
 449                  */
 450                 if (ss->percentage == 0)
 451                         return;
 452                 if (ss->type & ATOM_EXTERNAL_SS_MASK)
 453                         return;
 454         } else {
 455                 for (i = 0; i < rdev->num_crtc; i++) {
 456                         if (rdev->mode_info.crtcs[i] &&
 457                             rdev->mode_info.crtcs[i]->enabled &&
 458                             i != crtc_id &&
 459                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 460                                 /* one other crtc is using this pll don't turn
 461                                  * off spread spectrum as it might turn off
 462                                  * display on active crtc
 463                                  */
 464                                 return;
 465                         }
 466                 }
 467         }
 468
 469         memset(&args, 0, sizeof(args));
 470
 471         if (ASIC_IS_DCE5(rdev)) {
 472                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 473                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 474                 switch (pll_id) {
 475                 case ATOM_PPLL1:
 476                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 477                         break;
 478                 case ATOM_PPLL2:
 479                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 480                         break;
 481                 case ATOM_DCPLL:
 482                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 483                         break;
 484                 case ATOM_PPLL_INVALID:
 485                         return;
 486                 }
 487                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 488                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 489                 args.v3.ucEnable = enable;
 490         } else if (ASIC_IS_DCE4(rdev)) {
 491                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 492                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 493                 switch (pll_id) {
 494                 case ATOM_PPLL1:
 495                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 496                         break;
 497                 case ATOM_PPLL2:
 498                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 499                         break;
 500                 case ATOM_DCPLL:
 501                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 502                         break;
 503                 case ATOM_PPLL_INVALID:
 504                         return;
 505                 }
 506                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 507                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 508                 args.v2.ucEnable = enable;
 509         } else if (ASIC_IS_DCE3(rdev)) {
 510                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 511                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 512                 args.v1.ucSpreadSpectrumStep = ss->step;
 513                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 514                 args.v1.ucSpreadSpectrumRange = ss->range;
 515                 args.v1.ucPpll = pll_id;
 516                 args.v1.ucEnable = enable;
 517         } else if (ASIC_IS_AVIVO(rdev)) {
 518                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 519                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 520                         atombios_disable_ss(rdev, pll_id);
 521                         return;
 522                 }
 523                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 524                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 525                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 526                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 527                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 528                 args.lvds_ss_2.ucEnable = enable;
 529         } else {
 530                 if (enable == ATOM_DISABLE) {
 531                         atombios_disable_ss(rdev, pll_id);
 532                         return;
 533                 }
 534                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 535                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 536                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 537                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 538                 args.lvds_ss.ucEnable = enable;
 539         }
 540         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 541 }
 542
 543 union adjust_pixel_clock {
 544         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 545         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 546 };
 547
 548 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 549                                struct drm_display_mode *mode)
 550 {
 551         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 552         struct drm_device *dev = crtc->dev;
 553         struct radeon_device *rdev = dev->dev_private;
 554         struct drm_encoder *encoder = radeon_crtc->encoder;
 555         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 556         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 557         u32 adjusted_clock = mode->clock;
 558         int encoder_mode = atombios_get_encoder_mode(encoder);
 559         u32 dp_clock = mode->clock;
 560         u32 clock = mode->clock;
 561         int bpc = radeon_crtc->bpc;
 562         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 563
 564         /* reset the pll flags */
 565         radeon_crtc->pll_flags = 0;
 566
 567         if (ASIC_IS_AVIVO(rdev)) {
 568                 if ((rdev->family == CHIP_RS600) ||
 569                     (rdev->family == CHIP_RS690) ||
 570                     (rdev->family == CHIP_RS740))
 571                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 572                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 573
 574                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 575                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 576                 else
 577                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 578
 579                 if (rdev->family < CHIP_RV770)
 580                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 581                 /* use frac fb div on APUs */
 582                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 583                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 584                 /* use frac fb div on RS780/RS880 */
 585                 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 586                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 587                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 588                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 589         } else {
 590                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 591
 592                 if (mode->clock > 200000)       /* range limits??? */
 593                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 594                 else
 595                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 596         }
 597
 598         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 599             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 600                 if (connector) {
 601                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 602                         struct radeon_connector_atom_dig *dig_connector =
 603                                 radeon_connector->con_priv;
 604
 605                         dp_clock = dig_connector->dp_clock;
 606                 }
 607         }
 608
 609         /* use recommended ref_div for ss */
 610         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 611                 if (radeon_crtc->ss_enabled) {
 612                         if (radeon_crtc->ss.refdiv) {
 613                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 614                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 615                                 if (ASIC_IS_AVIVO(rdev))
 616                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 617                         }
 618                 }
 619         }
 620
 621         if (ASIC_IS_AVIVO(rdev)) {
 622                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 623                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 624                         adjusted_clock = mode->clock * 2;
 625                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 626                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 627                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 628                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 629         } else {
 630                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 631                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 632                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 633                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 634         }
 635
 636         /* adjust pll for deep color modes */
 637         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 638                 switch (bpc) {
 639                 case 8:
 640                 default:
 641                         break;
 642                 case 10:
 643                         clock = (clock * 5) / 4;
 644                         break;
 645                 case 12:
 646                         clock = (clock * 3) / 2;
 647                         break;
 648                 case 16:
 649                         clock = clock * 2;
 650                         break;
 651                 }
 652         }
 653
 654         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 655          * accordingly based on the encoder/transmitter to work around
 656          * special hw requirements.
 657          */
 658         if (ASIC_IS_DCE3(rdev)) {
 659                 union adjust_pixel_clock args;
 660                 u8 frev, crev;
 661                 int index;
 662
 663                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 664                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 665                                            &crev))
 666                         return adjusted_clock;
 667
 668                 memset(&args, 0, sizeof(args));
 669
 670                 switch (frev) {
 671                 case 1:
 672                         switch (crev) {
 673                         case 1:
 674                         case 2:
 675                                 args.v1.usPixelClock = cpu_to_le16(clock / 10);
 676                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 677                                 args.v1.ucEncodeMode = encoder_mode;
 678                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 679                                         args.v1.ucConfig |=
 680                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 681
 682                                 atom_execute_table(rdev->mode_info.atom_context,
 683                                                    index, (uint32_t *)&args);
 684                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 685                                 break;
 686                         case 3:
 687                                 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
 688                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 689                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 690                                 args.v3.sInput.ucDispPllConfig = 0;
 691                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 692                                         args.v3.sInput.ucDispPllConfig |=
 693                                                 DISPPLL_CONFIG_SS_ENABLE;
 694                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 695                                         args.v3.sInput.ucDispPllConfig |=
 696                                                 DISPPLL_CONFIG_COHERENT_MODE;
 697                                         /* 16200 or 27000 */
 698                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 699                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 700                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 701                                         if (dig->coherent_mode)
 702                                                 args.v3.sInput.ucDispPllConfig |=
 703                                                         DISPPLL_CONFIG_COHERENT_MODE;
 704                                         if (is_duallink)
 705                                                 args.v3.sInput.ucDispPllConfig |=
 706                                                         DISPPLL_CONFIG_DUAL_LINK;
 707                                 }
 708                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 709                                     ENCODER_OBJECT_ID_NONE)
 710                                         args.v3.sInput.ucExtTransmitterID =
 711                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 712                                 else
 713                                         args.v3.sInput.ucExtTransmitterID = 0;
 714
 715                                 atom_execute_table(rdev->mode_info.atom_context,
 716                                                    index, (uint32_t *)&args);
 717                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 718                                 if (args.v3.sOutput.ucRefDiv) {
 719                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 720                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 721                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 722                                 }
 723                                 if (args.v3.sOutput.ucPostDiv) {
 724                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 725                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 726                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 727                                 }
 728                                 break;
 729                         default:
 730                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 731                                 return adjusted_clock;
 732                         }
 733                         break;
 734                 default:
 735                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 736                         return adjusted_clock;
 737                 }
 738         }
 739         return adjusted_clock;
 740 }
 741
 742 union set_pixel_clock {
 743         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 744         PIXEL_CLOCK_PARAMETERS v1;
 745         PIXEL_CLOCK_PARAMETERS_V2 v2;
 746         PIXEL_CLOCK_PARAMETERS_V3 v3;
 747         PIXEL_CLOCK_PARAMETERS_V5 v5;
 748         PIXEL_CLOCK_PARAMETERS_V6 v6;
 749 };
 750
 751 /* on DCE5, make sure the voltage is high enough to support the
 752  * required disp clk.
 753  */
 754 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 755                                     u32 dispclk)
 756 {
 757         u8 frev, crev;
 758         int index;
 759         union set_pixel_clock args;
 760
 761         memset(&args, 0, sizeof(args));
 762
 763         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 764         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 765                                    &crev))
 766                 return;
 767
 768         switch (frev) {
 769         case 1:
 770                 switch (crev) {
 771                 case 5:
 772                         /* if the default dcpll clock is specified,
 773                          * SetPixelClock provides the dividers
 774                          */
 775                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 776                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 777                         args.v5.ucPpll = ATOM_DCPLL;
 778                         break;
 779                 case 6:
 780                         /* if the default dcpll clock is specified,
 781                          * SetPixelClock provides the dividers
 782                          */
 783                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 784                         if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 785                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 786                         else if (ASIC_IS_DCE6(rdev))
 787                                 args.v6.ucPpll = ATOM_PPLL0;
 788                         else
 789                                 args.v6.ucPpll = ATOM_DCPLL;
 790                         break;
 791                 default:
 792                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 793                         return;
 794                 }
 795                 break;
 796         default:
 797                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 798                 return;
 799         }
 800         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 801 }
 802
 803 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 804                                       u32 crtc_id,
 805                                       int pll_id,
 806                                       u32 encoder_mode,
 807                                       u32 encoder_id,
 808                                       u32 clock,
 809                                       u32 ref_div,
 810                                       u32 fb_div,
 811                                       u32 frac_fb_div,
 812                                       u32 post_div,
 813                                       int bpc,
 814                                       bool ss_enabled,
 815                                       struct radeon_atom_ss *ss)
 816 {
 817         struct drm_device *dev = crtc->dev;
 818         struct radeon_device *rdev = dev->dev_private;
 819         u8 frev, crev;
 820         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 821         union set_pixel_clock args;
 822
 823         memset(&args, 0, sizeof(args));
 824
 825         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 826                                    &crev))
 827                 return;
 828
 829         switch (frev) {
 830         case 1:
 831                 switch (crev) {
 832                 case 1:
 833                         if (clock == ATOM_DISABLE)
 834                                 return;
 835                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 836                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 837                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 838                         args.v1.ucFracFbDiv = frac_fb_div;
 839                         args.v1.ucPostDiv = post_div;
 840                         args.v1.ucPpll = pll_id;
 841                         args.v1.ucCRTC = crtc_id;
 842                         args.v1.ucRefDivSrc = 1;
 843                         break;
 844                 case 2:
 845                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 846                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 847                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 848                         args.v2.ucFracFbDiv = frac_fb_div;
 849                         args.v2.ucPostDiv = post_div;
 850                         args.v2.ucPpll = pll_id;
 851                         args.v2.ucCRTC = crtc_id;
 852                         args.v2.ucRefDivSrc = 1;
 853                         break;
 854                 case 3:
 855                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 856                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 857                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 858                         args.v3.ucFracFbDiv = frac_fb_div;
 859                         args.v3.ucPostDiv = post_div;
 860                         args.v3.ucPpll = pll_id;
 861                         if (crtc_id == ATOM_CRTC2)
 862                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 863                         else
 864                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 865                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 866                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 867                         args.v3.ucTransmitterId = encoder_id;
 868                         args.v3.ucEncoderMode = encoder_mode;
 869                         break;
 870                 case 5:
 871                         args.v5.ucCRTC = crtc_id;
 872                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 873                         args.v5.ucRefDiv = ref_div;
 874                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 875                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 876                         args.v5.ucPostDiv = post_div;
 877                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 878                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 879                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 880                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 881                                 switch (bpc) {
 882                                 case 8:
 883                                 default:
 884                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 885                                         break;
 886                                 case 10:
 887                                         /* yes this is correct, the atom define is wrong */
 888                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
 889                                         break;
 890                                 case 12:
 891                                         /* yes this is correct, the atom define is wrong */
 892                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 893                                         break;
 894                                 }
 895                         }
 896                         args.v5.ucTransmitterID = encoder_id;
 897                         args.v5.ucEncoderMode = encoder_mode;
 898                         args.v5.ucPpll = pll_id;
 899                         break;
 900                 case 6:
 901                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 902                         args.v6.ucRefDiv = ref_div;
 903                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 904                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 905                         args.v6.ucPostDiv = post_div;
 906                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 907                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 908                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 909                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 910                                 switch (bpc) {
 911                                 case 8:
 912                                 default:
 913                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 914                                         break;
 915                                 case 10:
 916                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
 917                                         break;
 918                                 case 12:
 919                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
 920                                         break;
 921                                 case 16:
 922                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 923                                         break;
 924                                 }
 925                         }
 926                         args.v6.ucTransmitterID = encoder_id;
 927                         args.v6.ucEncoderMode = encoder_mode;
 928                         args.v6.ucPpll = pll_id;
 929                         break;
 930                 default:
 931                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 932                         return;
 933                 }
 934                 break;
 935         default:
 936                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 937                 return;
 938         }
 939
 940         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 941 }
 942
 943 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 944 {
 945         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 946         struct drm_device *dev = crtc->dev;
 947         struct radeon_device *rdev = dev->dev_private;
 948         struct radeon_encoder *radeon_encoder =
 949                 to_radeon_encoder(radeon_crtc->encoder);
 950         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 951
 952         radeon_crtc->bpc = 8;
 953         radeon_crtc->ss_enabled = false;
 954
 955         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 956             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 957                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 958                 struct drm_connector *connector =
 959                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 960                 struct radeon_connector *radeon_connector =
 961                         to_radeon_connector(connector);
 962                 struct radeon_connector_atom_dig *dig_connector =
 963                         radeon_connector->con_priv;
 964                 int dp_clock;
 965
 966                 /* Assign mode clock for hdmi deep color max clock limit check */
 967                 radeon_connector->pixelclock_for_modeset = mode->clock;
 968                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 969
 970                 switch (encoder_mode) {
 971                 case ATOM_ENCODER_MODE_DP_MST:
 972                 case ATOM_ENCODER_MODE_DP:
 973                         /* DP/eDP */
 974                         dp_clock = dig_connector->dp_clock / 10;
 975                         if (ASIC_IS_DCE4(rdev))
 976                                 radeon_crtc->ss_enabled =
 977                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 978                                                                          ASIC_INTERNAL_SS_ON_DP,
 979                                                                          dp_clock);
 980                         else {
 981                                 if (dp_clock == 16200) {
 982                                         radeon_crtc->ss_enabled =
 983                                                 radeon_atombios_get_ppll_ss_info(rdev,
 984                                                                                  &radeon_crtc->ss,
 985                                                                                  ATOM_DP_SS_ID2);
 986                                         if (!radeon_crtc->ss_enabled)
 987                                                 radeon_crtc->ss_enabled =
 988                                                         radeon_atombios_get_ppll_ss_info(rdev,
 989                                                                                          &radeon_crtc->ss,
 990                                                                                          ATOM_DP_SS_ID1);
 991                                 } else {
 992                                         radeon_crtc->ss_enabled =
 993                                                 radeon_atombios_get_ppll_ss_info(rdev,
 994                                                                                  &radeon_crtc->ss,
 995                                                                                  ATOM_DP_SS_ID1);
 996                                 }
 997                                 /* disable spread spectrum on DCE3 DP */
 998                                 radeon_crtc->ss_enabled = false;
 999                         }
1000                         break;
1001                 case ATOM_ENCODER_MODE_LVDS:
1002                         if (ASIC_IS_DCE4(rdev))
1003                                 radeon_crtc->ss_enabled =
1004                                         radeon_atombios_get_asic_ss_info(rdev,
1005                                                                          &radeon_crtc->ss,
1006                                                                          dig->lcd_ss_id,
1007                                                                          mode->clock / 10);
1008                         else
1009                                 radeon_crtc->ss_enabled =
1010                                         radeon_atombios_get_ppll_ss_info(rdev,
1011                                                                          &radeon_crtc->ss,
1012                                                                          dig->lcd_ss_id);
1013                         break;
1014                 case ATOM_ENCODER_MODE_DVI:
1015                         if (ASIC_IS_DCE4(rdev))
1016                                 radeon_crtc->ss_enabled =
1017                                         radeon_atombios_get_asic_ss_info(rdev,
1018                                                                          &radeon_crtc->ss,
1019                                                                          ASIC_INTERNAL_SS_ON_TMDS,
1020                                                                          mode->clock / 10);
1021                         break;
1022                 case ATOM_ENCODER_MODE_HDMI:
1023                         if (ASIC_IS_DCE4(rdev))
1024                                 radeon_crtc->ss_enabled =
1025                                         radeon_atombios_get_asic_ss_info(rdev,
1026                                                                          &radeon_crtc->ss,
1027                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1028                                                                          mode->clock / 10);
1029                         break;
1030                 default:
1031                         break;
1032                 }
1033         }
1034
1035         /* adjust pixel clock as needed */
1036         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1037
1038         return true;
1039 }
1040
1041 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1042 {
1043         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1044         struct drm_device *dev = crtc->dev;
1045         struct radeon_device *rdev = dev->dev_private;
1046         struct radeon_encoder *radeon_encoder =
1047                 to_radeon_encoder(radeon_crtc->encoder);
1048         u32 pll_clock = mode->clock;
1049         u32 clock = mode->clock;
1050         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1051         struct radeon_pll *pll;
1052         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1053
1054         /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1055         if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) &&
1056             (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1057             (radeon_crtc->bpc > 8))
1058                 clock = radeon_crtc->adjusted_clock;
1059
1060         switch (radeon_crtc->pll_id) {
1061         case ATOM_PPLL1:
1062                 pll = &rdev->clock.p1pll;
1063                 break;
1064         case ATOM_PPLL2:
1065                 pll = &rdev->clock.p2pll;
1066                 break;
1067         case ATOM_DCPLL:
1068         case ATOM_PPLL_INVALID:
1069         default:
1070                 pll = &rdev->clock.dcpll;
1071                 break;
1072         }
1073
1074         /* update pll params */
1075         pll->flags = radeon_crtc->pll_flags;
1076         pll->reference_div = radeon_crtc->pll_reference_div;
1077         pll->post_div = radeon_crtc->pll_post_div;
1078
1079         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1080                 /* TV seems to prefer the legacy algo on some boards */
1081                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1082                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1083         else if (ASIC_IS_AVIVO(rdev))
1084                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1085                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1086         else
1087                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1088                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1089
1090         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1091                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1092
1093         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1094                                   encoder_mode, radeon_encoder->encoder_id, clock,
1095                                   ref_div, fb_div, frac_fb_div, post_div,
1096                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1097
1098         if (radeon_crtc->ss_enabled) {
1099                 /* calculate ss amount and step size */
1100                 if (ASIC_IS_DCE4(rdev)) {
1101                         u32 step_size;
1102                         u32 amount = (((fb_div * 10) + frac_fb_div) *
1103                                       (u32)radeon_crtc->ss.percentage) /
1104                                 (100 * (u32)radeon_crtc->ss.percentage_divider);
1105                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1106                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1107                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1108                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1109                                 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1110                                         (125 * 25 * pll->reference_freq / 100);
1111                         else
1112                                 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1113                                         (125 * 25 * pll->reference_freq / 100);
1114                         radeon_crtc->ss.step = step_size;
1115                 }
1116
1117                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1118                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1119         }
1120 }
1121
1122 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1123                                  struct drm_framebuffer *fb,
1124                                  int x, int y, int atomic)
1125 {
1126         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1127         struct drm_device *dev = crtc->dev;
1128         struct radeon_device *rdev = dev->dev_private;
1129         struct radeon_framebuffer *radeon_fb;
1130         struct drm_framebuffer *target_fb;
1131         struct drm_gem_object *obj;
1132         struct radeon_bo *rbo;
1133         uint64_t fb_location;
1134         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1135         unsigned bankw, bankh, mtaspect, tile_split;
1136         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1137         u32 tmp, viewport_w, viewport_h;
1138         int r;
1139
1140         /* no fb bound */
1141         if (!atomic && !crtc->primary->fb) {
1142                 DRM_DEBUG_KMS("No FB bound\n");
1143                 return 0;
1144         }
1145
1146         if (atomic) {
1147                 radeon_fb = to_radeon_framebuffer(fb);
1148                 target_fb = fb;
1149         }
1150         else {
1151                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1152                 target_fb = crtc->primary->fb;
1153         }
1154
1155         /* If atomic, assume fb object is pinned & idle & fenced and
1156          * just update base pointers
1157          */
1158         obj = radeon_fb->obj;
1159         rbo = gem_to_radeon_bo(obj);
1160         r = radeon_bo_reserve(rbo, false);
1161         if (unlikely(r != 0))
1162                 return r;
1163
1164         if (atomic)
1165                 fb_location = radeon_bo_gpu_offset(rbo);
1166         else {
1167                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1168                 if (unlikely(r != 0)) {
1169                         radeon_bo_unreserve(rbo);
1170                         return -EINVAL;
1171                 }
1172         }
1173
1174         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1175         radeon_bo_unreserve(rbo);
1176
1177         switch (target_fb->bits_per_pixel) {
1178         case 8:
1179                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1180                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1181                 break;
1182         case 15:
1183                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1184                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1185                 break;
1186         case 16:
1187                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1188                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1189 #ifdef __BIG_ENDIAN
1190                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1191 #endif
1192                 break;
1193         case 24:
1194         case 32:
1195                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1196                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1197 #ifdef __BIG_ENDIAN
1198                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1199 #endif
1200                 break;
1201         default:
1202                 DRM_ERROR("Unsupported screen depth %d\n",
1203                           target_fb->bits_per_pixel);
1204                 return -EINVAL;
1205         }
1206
1207         if (tiling_flags & RADEON_TILING_MACRO) {
1208                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1209
1210                 /* Set NUM_BANKS. */
1211                 if (rdev->family >= CHIP_TAHITI) {
1212                         unsigned index, num_banks;
1213
1214                         if (rdev->family >= CHIP_BONAIRE) {
1215                                 unsigned tileb, tile_split_bytes;
1216
1217                                 /* Calculate the macrotile mode index. */
1218                                 tile_split_bytes = 64 << tile_split;
1219                                 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1220                                 tileb = min(tile_split_bytes, tileb);
1221
1222                                 for (index = 0; tileb > 64; index++)
1223                                         tileb >>= 1;
1224
1225                                 if (index >= 16) {
1226                                         DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1227                                                   target_fb->bits_per_pixel, tile_split);
1228                                         return -EINVAL;
1229                                 }
1230
1231                                 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1232                         } else {
1233                                 switch (target_fb->bits_per_pixel) {
1234                                 case 8:
1235                                         index = 10;
1236                                         break;
1237                                 case 16:
1238                                         index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1239                                         break;
1240                                 default:
1241                                 case 32:
1242                                         index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1243                                         break;
1244                                 }
1245
1246                                 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1247                         }
1248
1249                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1250                 } else {
1251                         /* NI and older. */
1252                         if (rdev->family >= CHIP_CAYMAN)
1253                                 tmp = rdev->config.cayman.tile_config;
1254                         else
1255                                 tmp = rdev->config.evergreen.tile_config;
1256
1257                         switch ((tmp & 0xf0) >> 4) {
1258                         case 0: /* 4 banks */
1259                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1260                                 break;
1261                         case 1: /* 8 banks */
1262                         default:
1263                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1264                                 break;
1265                         case 2: /* 16 banks */
1266                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1267                                 break;
1268                         }
1269                 }
1270
1271                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1272                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1273                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1274                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1275                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1276                 if (rdev->family >= CHIP_BONAIRE) {
1277                         /* XXX need to know more about the surface tiling mode */
1278                         fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1279                 }
1280         } else if (tiling_flags & RADEON_TILING_MICRO)
1281                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1282
1283         if (rdev->family >= CHIP_BONAIRE) {
1284                 /* Read the pipe config from the 2D TILED SCANOUT mode.
1285                  * It should be the same for the other modes too, but not all
1286                  * modes set the pipe config field. */
1287                 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1288
1289                 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1290         } else if ((rdev->family == CHIP_TAHITI) ||
1291                    (rdev->family == CHIP_PITCAIRN))
1292                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1293         else if ((rdev->family == CHIP_VERDE) ||
1294                  (rdev->family == CHIP_OLAND) ||
1295                  (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
1296                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1297
1298         switch (radeon_crtc->crtc_id) {
1299         case 0:
1300                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1301                 break;
1302         case 1:
1303                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1304                 break;
1305         case 2:
1306                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1307                 break;
1308         case 3:
1309                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1310                 break;
1311         case 4:
1312                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1313                 break;
1314         case 5:
1315                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1316                 break;
1317         default:
1318                 break;
1319         }
1320
1321         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1322                upper_32_bits(fb_location));
1323         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1324                upper_32_bits(fb_location));
1325         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1326                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1327         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1328                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1329         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1330         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331
1332         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1335         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1336         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1337         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1338
1339         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1340         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1341         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1342
1343         if (rdev->family >= CHIP_BONAIRE)
1344                 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1345                        target_fb->height);
1346         else
1347                 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1348                        target_fb->height);
1349         x &= ~3;
1350         y &= ~1;
1351         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1352                (x << 16) | y);
1353         viewport_w = crtc->mode.hdisplay;
1354         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1355         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1356                (viewport_w << 16) | viewport_h);
1357
1358         /* pageflip setup */
1359         /* make sure flip is at vb rather than hb */
1360         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1361         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1362         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1363
1364         /* set pageflip to happen anywhere in vblank interval */
1365         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1366
1367         if (!atomic && fb && fb != crtc->primary->fb) {
1368                 radeon_fb = to_radeon_framebuffer(fb);
1369                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1370                 r = radeon_bo_reserve(rbo, false);
1371                 if (unlikely(r != 0))
1372                         return r;
1373                 radeon_bo_unpin(rbo);
1374                 radeon_bo_unreserve(rbo);
1375         }
1376
1377         /* Bytes per pixel may have changed */
1378         radeon_bandwidth_update(rdev);
1379
1380         return 0;
1381 }
1382
1383 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1384                                   struct drm_framebuffer *fb,
1385                                   int x, int y, int atomic)
1386 {
1387         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1388         struct drm_device *dev = crtc->dev;
1389         struct radeon_device *rdev = dev->dev_private;
1390         struct radeon_framebuffer *radeon_fb;
1391         struct drm_gem_object *obj;
1392         struct radeon_bo *rbo;
1393         struct drm_framebuffer *target_fb;
1394         uint64_t fb_location;
1395         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1396         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1397         u32 tmp, viewport_w, viewport_h;
1398         int r;
1399
1400         /* no fb bound */
1401         if (!atomic && !crtc->primary->fb) {
1402                 DRM_DEBUG_KMS("No FB bound\n");
1403                 return 0;
1404         }
1405
1406         if (atomic) {
1407                 radeon_fb = to_radeon_framebuffer(fb);
1408                 target_fb = fb;
1409         }
1410         else {
1411                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1412                 target_fb = crtc->primary->fb;
1413         }
1414
1415         obj = radeon_fb->obj;
1416         rbo = gem_to_radeon_bo(obj);
1417         r = radeon_bo_reserve(rbo, false);
1418         if (unlikely(r != 0))
1419                 return r;
1420
1421         /* If atomic, assume fb object is pinned & idle & fenced and
1422          * just update base pointers
1423          */
1424         if (atomic)
1425                 fb_location = radeon_bo_gpu_offset(rbo);
1426         else {
1427                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1428                 if (unlikely(r != 0)) {
1429                         radeon_bo_unreserve(rbo);
1430                         return -EINVAL;
1431                 }
1432         }
1433         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1434         radeon_bo_unreserve(rbo);
1435
1436         switch (target_fb->bits_per_pixel) {
1437         case 8:
1438                 fb_format =
1439                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1440                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1441                 break;
1442         case 15:
1443                 fb_format =
1444                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1445                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1446                 break;
1447         case 16:
1448                 fb_format =
1449                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1450                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1451 #ifdef __BIG_ENDIAN
1452                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1453 #endif
1454                 break;
1455         case 24:
1456         case 32:
1457                 fb_format =
1458                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1459                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1460 #ifdef __BIG_ENDIAN
1461                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1462 #endif
1463                 break;
1464         default:
1465                 DRM_ERROR("Unsupported screen depth %d\n",
1466                           target_fb->bits_per_pixel);
1467                 return -EINVAL;
1468         }
1469
1470         if (rdev->family >= CHIP_R600) {
1471                 if (tiling_flags & RADEON_TILING_MACRO)
1472                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1473                 else if (tiling_flags & RADEON_TILING_MICRO)
1474                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1475         } else {
1476                 if (tiling_flags & RADEON_TILING_MACRO)
1477                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1478
1479                 if (tiling_flags & RADEON_TILING_MICRO)
1480                         fb_format |= AVIVO_D1GRPH_TILED;
1481         }
1482
1483         if (radeon_crtc->crtc_id == 0)
1484                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1485         else
1486                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1487
1488         if (rdev->family >= CHIP_RV770) {
1489                 if (radeon_crtc->crtc_id) {
1490                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1491                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1492                 } else {
1493                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1494                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1495                 }
1496         }
1497         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1498                (u32) fb_location);
1499         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1500                radeon_crtc->crtc_offset, (u32) fb_location);
1501         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1502         if (rdev->family >= CHIP_R600)
1503                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1504
1505         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1506         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1507         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1508         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1509         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1510         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1511
1512         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1513         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1514         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1515
1516         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1517                target_fb->height);
1518         x &= ~3;
1519         y &= ~1;
1520         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1521                (x << 16) | y);
1522         viewport_w = crtc->mode.hdisplay;
1523         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1524         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1525                (viewport_w << 16) | viewport_h);
1526
1527         /* pageflip setup */
1528         /* make sure flip is at vb rather than hb */
1529         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1530         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1531         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1532
1533         /* set pageflip to happen anywhere in vblank interval */
1534         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1535
1536         if (!atomic && fb && fb != crtc->primary->fb) {
1537                 radeon_fb = to_radeon_framebuffer(fb);
1538                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1539                 r = radeon_bo_reserve(rbo, false);
1540                 if (unlikely(r != 0))
1541                         return r;
1542                 radeon_bo_unpin(rbo);
1543                 radeon_bo_unreserve(rbo);
1544         }
1545
1546         /* Bytes per pixel may have changed */
1547         radeon_bandwidth_update(rdev);
1548
1549         return 0;
1550 }
1551
1552 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1553                            struct drm_framebuffer *old_fb)
1554 {
1555         struct drm_device *dev = crtc->dev;
1556         struct radeon_device *rdev = dev->dev_private;
1557
1558         if (ASIC_IS_DCE4(rdev))
1559                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1560         else if (ASIC_IS_AVIVO(rdev))
1561                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1562         else
1563                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1564 }
1565
1566 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1567                                   struct drm_framebuffer *fb,
1568                                   int x, int y, enum mode_set_atomic state)
1569 {
1570        struct drm_device *dev = crtc->dev;
1571        struct radeon_device *rdev = dev->dev_private;
1572
1573         if (ASIC_IS_DCE4(rdev))
1574                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1575         else if (ASIC_IS_AVIVO(rdev))
1576                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1577         else
1578                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1579 }
1580
1581 /* properly set additional regs when using atombios */
1582 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1583 {
1584         struct drm_device *dev = crtc->dev;
1585         struct radeon_device *rdev = dev->dev_private;
1586         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1587         u32 disp_merge_cntl;
1588
1589         switch (radeon_crtc->crtc_id) {
1590         case 0:
1591                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1592                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1593                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1594                 break;
1595         case 1:
1596                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1597                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1598                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1599                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1600                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1601                 break;
1602         }
1603 }
1604
1605 /**
1606  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1607  *
1608  * @crtc: drm crtc
1609  *
1610  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1611  */
1612 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->dev;
1615         struct drm_crtc *test_crtc;
1616         struct radeon_crtc *test_radeon_crtc;
1617         u32 pll_in_use = 0;
1618
1619         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1620                 if (crtc == test_crtc)
1621                         continue;
1622
1623                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1624                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1625                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1626         }
1627         return pll_in_use;
1628 }
1629
1630 /**
1631  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1632  *
1633  * @crtc: drm crtc
1634  *
1635  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1636  * also in DP mode.  For DP, a single PPLL can be used for all DP
1637  * crtcs/encoders.
1638  */
1639 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1640 {
1641         struct drm_device *dev = crtc->dev;
1642         struct drm_crtc *test_crtc;
1643         struct radeon_crtc *test_radeon_crtc;
1644
1645         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1646                 if (crtc == test_crtc)
1647                         continue;
1648                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1649                 if (test_radeon_crtc->encoder &&
1650                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1651                         /* for DP use the same PLL for all */
1652                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1653                                 return test_radeon_crtc->pll_id;
1654                 }
1655         }
1656         return ATOM_PPLL_INVALID;
1657 }
1658
1659 /**
1660  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1661  *
1662  * @crtc: drm crtc
1663  * @encoder: drm encoder
1664  *
1665  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1666  * be shared (i.e., same clock).
1667  */
1668 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1669 {
1670         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1671         struct drm_device *dev = crtc->dev;
1672         struct drm_crtc *test_crtc;
1673         struct radeon_crtc *test_radeon_crtc;
1674         u32 adjusted_clock, test_adjusted_clock;
1675
1676         adjusted_clock = radeon_crtc->adjusted_clock;
1677
1678         if (adjusted_clock == 0)
1679                 return ATOM_PPLL_INVALID;
1680
1681         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1682                 if (crtc == test_crtc)
1683                         continue;
1684                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1685                 if (test_radeon_crtc->encoder &&
1686                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1687                         /* check if we are already driving this connector with another crtc */
1688                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1689                                 /* if we are, return that pll */
1690                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1691                                         return test_radeon_crtc->pll_id;
1692                         }
1693                         /* for non-DP check the clock */
1694                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1695                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1696                             (adjusted_clock == test_adjusted_clock) &&
1697                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1698                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1699                                 return test_radeon_crtc->pll_id;
1700                 }
1701         }
1702         return ATOM_PPLL_INVALID;
1703 }
1704
1705 /**
1706  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1707  *
1708  * @crtc: drm crtc
1709  *
1710  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1711  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1712  * monitors a dedicated PPLL must be used.  If a particular board has
1713  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1714  * as there is no need to program the PLL itself.  If we are not able to
1715  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1716  * avoid messing up an existing monitor.
1717  *
1718  * Asic specific PLL information
1719  *
1720  * DCE 8.x
1721  * KB/KV
1722  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1723  * CI
1724  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1725  *
1726  * DCE 6.1
1727  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1728  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1729  *
1730  * DCE 6.0
1731  * - PPLL0 is available to all UNIPHY (DP only)
1732  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1733  *
1734  * DCE 5.0
1735  * - DCPLL is available to all UNIPHY (DP only)
1736  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1737  *
1738  * DCE 3.0/4.0/4.1
1739  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1740  *
1741  */
1742 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1743 {
1744         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1745         struct drm_device *dev = crtc->dev;
1746         struct radeon_device *rdev = dev->dev_private;
1747         struct radeon_encoder *radeon_encoder =
1748                 to_radeon_encoder(radeon_crtc->encoder);
1749         u32 pll_in_use;
1750         int pll;
1751
1752         if (ASIC_IS_DCE8(rdev)) {
1753                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1754                         if (rdev->clock.dp_extclk)
1755                                 /* skip PPLL programming if using ext clock */
1756                                 return ATOM_PPLL_INVALID;
1757                         else {
1758                                 /* use the same PPLL for all DP monitors */
1759                                 pll = radeon_get_shared_dp_ppll(crtc);
1760                                 if (pll != ATOM_PPLL_INVALID)
1761                                         return pll;
1762                         }
1763                 } else {
1764                         /* use the same PPLL for all monitors with the same clock */
1765                         pll = radeon_get_shared_nondp_ppll(crtc);
1766                         if (pll != ATOM_PPLL_INVALID)
1767                                 return pll;
1768                 }
1769                 /* otherwise, pick one of the plls */
1770                 if ((rdev->family == CHIP_KAVERI) ||
1771                     (rdev->family == CHIP_KABINI) ||
1772                     (rdev->family == CHIP_MULLINS)) {
1773                         /* KB/KV/ML has PPLL1 and PPLL2 */
1774                         pll_in_use = radeon_get_pll_use_mask(crtc);
1775                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1776                                 return ATOM_PPLL2;
1777                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1778                                 return ATOM_PPLL1;
1779                         DRM_ERROR("unable to allocate a PPLL\n");
1780                         return ATOM_PPLL_INVALID;
1781                 } else {
1782                         /* CI has PPLL0, PPLL1, and PPLL2 */
1783                         pll_in_use = radeon_get_pll_use_mask(crtc);
1784                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1785                                 return ATOM_PPLL2;
1786                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1787                                 return ATOM_PPLL1;
1788                         if (!(pll_in_use & (1 << ATOM_PPLL0)))
1789                                 return ATOM_PPLL0;
1790                         DRM_ERROR("unable to allocate a PPLL\n");
1791                         return ATOM_PPLL_INVALID;
1792                 }
1793         } else if (ASIC_IS_DCE61(rdev)) {
1794                 struct radeon_encoder_atom_dig *dig =
1795                         radeon_encoder->enc_priv;
1796
1797                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1798                     (dig->linkb == false))
1799                         /* UNIPHY A uses PPLL2 */
1800                         return ATOM_PPLL2;
1801                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1802                         /* UNIPHY B/C/D/E/F */
1803                         if (rdev->clock.dp_extclk)
1804                                 /* skip PPLL programming if using ext clock */
1805                                 return ATOM_PPLL_INVALID;
1806                         else {
1807                                 /* use the same PPLL for all DP monitors */
1808                                 pll = radeon_get_shared_dp_ppll(crtc);
1809                                 if (pll != ATOM_PPLL_INVALID)
1810                                         return pll;
1811                         }
1812                 } else {
1813                         /* use the same PPLL for all monitors with the same clock */
1814                         pll = radeon_get_shared_nondp_ppll(crtc);
1815                         if (pll != ATOM_PPLL_INVALID)
1816                                 return pll;
1817                 }
1818                 /* UNIPHY B/C/D/E/F */
1819                 pll_in_use = radeon_get_pll_use_mask(crtc);
1820                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1821                         return ATOM_PPLL0;
1822                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1823                         return ATOM_PPLL1;
1824                 DRM_ERROR("unable to allocate a PPLL\n");
1825                 return ATOM_PPLL_INVALID;
1826         } else if (ASIC_IS_DCE41(rdev)) {
1827                 /* Don't share PLLs on DCE4.1 chips */
1828                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1829                         if (rdev->clock.dp_extclk)
1830                                 /* skip PPLL programming if using ext clock */
1831                                 return ATOM_PPLL_INVALID;
1832                 }
1833                 pll_in_use = radeon_get_pll_use_mask(crtc);
1834                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1835                         return ATOM_PPLL1;
1836                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1837                         return ATOM_PPLL2;
1838                 DRM_ERROR("unable to allocate a PPLL\n");
1839                 return ATOM_PPLL_INVALID;
1840         } else if (ASIC_IS_DCE4(rdev)) {
1841                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1842                  * depending on the asic:
1843                  * DCE4: PPLL or ext clock
1844                  * DCE5: PPLL, DCPLL, or ext clock
1845                  * DCE6: PPLL, PPLL0, or ext clock
1846                  *
1847                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1848                  * PPLL/DCPLL programming and only program the DP DTO for the
1849                  * crtc virtual pixel clock.
1850                  */
1851                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1852                         if (rdev->clock.dp_extclk)
1853                                 /* skip PPLL programming if using ext clock */
1854                                 return ATOM_PPLL_INVALID;
1855                         else if (ASIC_IS_DCE6(rdev))
1856                                 /* use PPLL0 for all DP */
1857                                 return ATOM_PPLL0;
1858                         else if (ASIC_IS_DCE5(rdev))
1859                                 /* use DCPLL for all DP */
1860                                 return ATOM_DCPLL;
1861                         else {
1862                                 /* use the same PPLL for all DP monitors */
1863                                 pll = radeon_get_shared_dp_ppll(crtc);
1864                                 if (pll != ATOM_PPLL_INVALID)
1865                                         return pll;
1866                         }
1867                 } else {
1868                         /* use the same PPLL for all monitors with the same clock */
1869                         pll = radeon_get_shared_nondp_ppll(crtc);
1870                         if (pll != ATOM_PPLL_INVALID)
1871                                 return pll;
1872                 }
1873                 /* all other cases */
1874                 pll_in_use = radeon_get_pll_use_mask(crtc);
1875                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1876                         return ATOM_PPLL1;
1877                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1878                         return ATOM_PPLL2;
1879                 DRM_ERROR("unable to allocate a PPLL\n");
1880                 return ATOM_PPLL_INVALID;
1881         } else {
1882                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1883                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1884                  * the matching btw pll and crtc is done through
1885                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1886                  * pll (1 or 2) to select which register to write. ie if using
1887                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1888                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1889                  * choose which value to write. Which is reverse order from
1890                  * register logic. So only case that works is when pllid is
1891                  * same as crtcid or when both pll and crtc are enabled and
1892                  * both use same clock.
1893                  *
1894                  * So just return crtc id as if crtc and pll were hard linked
1895                  * together even if they aren't
1896                  */
1897                 return radeon_crtc->crtc_id;
1898         }
1899 }
1900
1901 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1902 {
1903         /* always set DCPLL */
1904         if (ASIC_IS_DCE6(rdev))
1905                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1906         else if (ASIC_IS_DCE4(rdev)) {
1907                 struct radeon_atom_ss ss;
1908                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1909                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1910                                                                    rdev->clock.default_dispclk);
1911                 if (ss_enabled)
1912                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1913                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1914                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1915                 if (ss_enabled)
1916                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1917         }
1918
1919 }
1920
1921 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1922                            struct drm_display_mode *mode,
1923                            struct drm_display_mode *adjusted_mode,
1924                            int x, int y, struct drm_framebuffer *old_fb)
1925 {
1926         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1927         struct drm_device *dev = crtc->dev;
1928         struct radeon_device *rdev = dev->dev_private;
1929         struct radeon_encoder *radeon_encoder =
1930                 to_radeon_encoder(radeon_crtc->encoder);
1931         bool is_tvcv = false;
1932
1933         if (radeon_encoder->active_device &
1934             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1935                 is_tvcv = true;
1936
1937         if (!radeon_crtc->adjusted_clock)
1938                 return -EINVAL;
1939
1940         atombios_crtc_set_pll(crtc, adjusted_mode);
1941
1942         if (ASIC_IS_DCE4(rdev))
1943                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1944         else if (ASIC_IS_AVIVO(rdev)) {
1945                 if (is_tvcv)
1946                         atombios_crtc_set_timing(crtc, adjusted_mode);
1947                 else
1948                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1949         } else {
1950                 atombios_crtc_set_timing(crtc, adjusted_mode);
1951                 if (radeon_crtc->crtc_id == 0)
1952                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1953                 radeon_legacy_atom_fixup(crtc);
1954         }
1955         atombios_crtc_set_base(crtc, x, y, old_fb);
1956         atombios_overscan_setup(crtc, mode, adjusted_mode);
1957         atombios_scaler_setup(crtc);
1958         /* update the hw version fpr dpm */
1959         radeon_crtc->hw_mode = *adjusted_mode;
1960
1961         return 0;
1962 }
1963
1964 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1965                                      const struct drm_display_mode *mode,
1966                                      struct drm_display_mode *adjusted_mode)
1967 {
1968         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1969         struct drm_device *dev = crtc->dev;
1970         struct drm_encoder *encoder;
1971
1972         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1973         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1974                 if (encoder->crtc == crtc) {
1975                         radeon_crtc->encoder = encoder;
1976                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1977                         break;
1978                 }
1979         }
1980         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1981                 radeon_crtc->encoder = NULL;
1982                 radeon_crtc->connector = NULL;
1983                 return false;
1984         }
1985         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1986                 return false;
1987         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1988                 return false;
1989         /* pick pll */
1990         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1991         /* if we can't get a PPLL for a non-DP encoder, fail */
1992         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1993             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1994                 return false;
1995
1996         return true;
1997 }
1998
1999 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2000 {
2001         struct drm_device *dev = crtc->dev;
2002         struct radeon_device *rdev = dev->dev_private;
2003
2004         /* disable crtc pair power gating before programming */
2005         if (ASIC_IS_DCE6(rdev))
2006                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2007
2008         atombios_lock_crtc(crtc, ATOM_ENABLE);
2009         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2010 }
2011
2012 static void atombios_crtc_commit(struct drm_crtc *crtc)
2013 {
2014         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2015         atombios_lock_crtc(crtc, ATOM_DISABLE);
2016 }
2017
2018 static void atombios_crtc_disable(struct drm_crtc *crtc)
2019 {
2020         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2021         struct drm_device *dev = crtc->dev;
2022         struct radeon_device *rdev = dev->dev_private;
2023         struct radeon_atom_ss ss;
2024         int i;
2025
2026         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2027         if (crtc->primary->fb) {
2028                 int r;
2029                 struct radeon_framebuffer *radeon_fb;
2030                 struct radeon_bo *rbo;
2031
2032                 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2033                 rbo = gem_to_radeon_bo(radeon_fb->obj);
2034                 r = radeon_bo_reserve(rbo, false);
2035                 if (unlikely(r))
2036                         DRM_ERROR("failed to reserve rbo before unpin\n");
2037                 else {
2038                         radeon_bo_unpin(rbo);
2039                         radeon_bo_unreserve(rbo);
2040                 }
2041         }
2042         /* disable the GRPH */
2043         if (ASIC_IS_DCE4(rdev))
2044                 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2045         else if (ASIC_IS_AVIVO(rdev))
2046                 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2047
2048         if (ASIC_IS_DCE6(rdev))
2049                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2050
2051         for (i = 0; i < rdev->num_crtc; i++) {
2052                 if (rdev->mode_info.crtcs[i] &&
2053                     rdev->mode_info.crtcs[i]->enabled &&
2054                     i != radeon_crtc->crtc_id &&
2055                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2056                         /* one other crtc is using this pll don't turn
2057                          * off the pll
2058                          */
2059                         goto done;
2060                 }
2061         }
2062
2063         switch (radeon_crtc->pll_id) {
2064         case ATOM_PPLL1:
2065         case ATOM_PPLL2:
2066                 /* disable the ppll */
2067                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2068                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2069                 break;
2070         case ATOM_PPLL0:
2071                 /* disable the ppll */
2072                 if ((rdev->family == CHIP_ARUBA) ||
2073                     (rdev->family == CHIP_BONAIRE) ||
2074                     (rdev->family == CHIP_HAWAII))
2075                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2076                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2077                 break;
2078         default:
2079                 break;
2080         }
2081 done:
2082         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2083         radeon_crtc->adjusted_clock = 0;
2084         radeon_crtc->encoder = NULL;
2085         radeon_crtc->connector = NULL;
2086 }
2087
2088 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2089         .dpms = atombios_crtc_dpms,
2090         .mode_fixup = atombios_crtc_mode_fixup,
2091         .mode_set = atombios_crtc_mode_set,
2092         .mode_set_base = atombios_crtc_set_base,
2093         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2094         .prepare = atombios_crtc_prepare,
2095         .commit = atombios_crtc_commit,
2096         .load_lut = radeon_crtc_load_lut,
2097         .disable = atombios_crtc_disable,
2098 };
2099
2100 void radeon_atombios_init_crtc(struct drm_device *dev,
2101                                struct radeon_crtc *radeon_crtc)
2102 {
2103         struct radeon_device *rdev = dev->dev_private;
2104
2105         if (ASIC_IS_DCE4(rdev)) {
2106                 switch (radeon_crtc->crtc_id) {
2107                 case 0:
2108                 default:
2109                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2110                         break;
2111                 case 1:
2112                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2113                         break;
2114                 case 2:
2115                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2116                         break;
2117                 case 3:
2118                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2119                         break;
2120                 case 4:
2121                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2122                         break;
2123                 case 5:
2124                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2125                         break;
2126                 }
2127         } else {
2128                 if (radeon_crtc->crtc_id == 1)
2129                         radeon_crtc->crtc_offset =
2130                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2131                 else
2132                         radeon_crtc->crtc_offset = 0;
2133         }
2134         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2135         radeon_crtc->adjusted_clock = 0;
2136         radeon_crtc->encoder = NULL;
2137         radeon_crtc->connector = NULL;
2138         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2139 }