drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32
  33 extern int atom_debug;
  34
  35 static u8
  36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37 {
  38         u8 backlight_level;
  39         u32 bios_2_scratch;
  40
  41         if (rdev->family >= CHIP_R600)
  42                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43         else
  44                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49         return backlight_level;
  50 }
  51
  52 static void
  53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                        u8 backlight_level)
  55 {
  56         u32 bios_2_scratch;
  57
  58         if (rdev->family >= CHIP_R600)
  59                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60         else
  61                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67         if (rdev->family >= CHIP_R600)
  68                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69         else
  70                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71 }
  72
  73 u8
  74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75 {
  76         struct drm_device *dev = radeon_encoder->base.dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78
  79         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                 return 0;
  81
  82         return radeon_atom_get_backlight_level_from_reg(rdev);
  83 }
  84
  85 void
  86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87 {
  88         struct drm_encoder *encoder = &radeon_encoder->base;
  89         struct drm_device *dev = radeon_encoder->base.dev;
  90         struct radeon_device *rdev = dev->dev_private;
  91         struct radeon_encoder_atom_dig *dig;
  92         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93         int index;
  94
  95         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                 return;
  97
  98         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99             radeon_encoder->enc_priv) {
 100                 dig = radeon_encoder->enc_priv;
 101                 dig->backlight_level = level;
 102                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                 switch (radeon_encoder->encoder_id) {
 105                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                         if (dig->backlight_level == 0) {
 109                                 args.ucAction = ATOM_LCD_BLOFF;
 110                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                         } else {
 112                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                 args.ucAction = ATOM_LCD_BLON;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                         }
 117                         break;
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                         if (dig->backlight_level == 0)
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                         else {
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                         }
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138 {
 139         u8 level;
 140
 141         /* Convert brightness to hardware level */
 142         if (bd->props.brightness < 0)
 143                 level = 0;
 144         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                 level = RADEON_MAX_BL_LEVEL;
 146         else
 147                 level = bd->props.brightness;
 148
 149         return level;
 150 }
 151
 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153 {
 154         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155         struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159         return 0;
 160 }
 161
 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163 {
 164         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165         struct radeon_encoder *radeon_encoder = pdata->encoder;
 166         struct drm_device *dev = radeon_encoder->base.dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168
 169         return radeon_atom_get_backlight_level_from_reg(rdev);
 170 }
 171
 172 static const struct backlight_ops radeon_atom_backlight_ops = {
 173         .get_brightness = radeon_atom_backlight_get_brightness,
 174         .update_status  = radeon_atom_backlight_update_status,
 175 };
 176
 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                 struct drm_connector *drm_connector)
 179 {
 180         struct drm_device *dev = radeon_encoder->base.dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct backlight_device *bd;
 183         struct backlight_properties props;
 184         struct radeon_backlight_privdata *pdata;
 185         struct radeon_encoder_atom_dig *dig;
 186         u8 backlight_level;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 226
 227         dig = radeon_encoder->enc_priv;
 228         dig->bl_dev = bd;
 229
 230         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 231         bd->props.power = FB_BLANK_UNBLANK;
 232         backlight_update_status(bd);
 233
 234         DRM_INFO("radeon atom DIG backlight initialized\n");
 235
 236         return;
 237
 238 error:
 239         kfree(pdata);
 240         return;
 241 }
 242
 243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 244 {
 245         struct drm_device *dev = radeon_encoder->base.dev;
 246         struct radeon_device *rdev = dev->dev_private;
 247         struct backlight_device *bd = NULL;
 248         struct radeon_encoder_atom_dig *dig;
 249
 250         if (!radeon_encoder->enc_priv)
 251                 return;
 252
 253         if (!rdev->is_atom_bios)
 254                 return;
 255
 256         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 257                 return;
 258
 259         dig = radeon_encoder->enc_priv;
 260         bd = dig->bl_dev;
 261         dig->bl_dev = NULL;
 262
 263         if (bd) {
 264                 struct radeon_legacy_backlight_privdata *pdata;
 265
 266                 pdata = bl_get_data(bd);
 267                 backlight_device_unregister(bd);
 268                 kfree(pdata);
 269
 270                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 271         }
 272 }
 273
 274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 275
 276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 277 {
 278 }
 279
 280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 281 {
 282 }
 283
 284 #endif
 285
 286 /* evil but including atombios.h is much worse */
 287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 288                                 struct drm_display_mode *mode);
 289
 290
 291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 292 {
 293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 294         switch (radeon_encoder->encoder_id) {
 295         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 296         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 298         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 299         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 300         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 301         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 302         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 303         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 304         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 305         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 306         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 307                 return true;
 308         default:
 309                 return false;
 310         }
 311 }
 312
 313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 314                                    const struct drm_display_mode *mode,
 315                                    struct drm_display_mode *adjusted_mode)
 316 {
 317         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 318         struct drm_device *dev = encoder->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320
 321         /* set the active encoder to connector routing */
 322         radeon_encoder_set_active_device(encoder);
 323         drm_mode_set_crtcinfo(adjusted_mode, 0);
 324
 325         /* hw bug */
 326         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 327             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 328                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 329
 330         /* get the native mode for LVDS */
 331         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 332                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 333
 334         /* get the native mode for TV */
 335         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 336                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 337                 if (tv_dac) {
 338                         if (tv_dac->tv_std == TV_STD_NTSC ||
 339                             tv_dac->tv_std == TV_STD_NTSC_J ||
 340                             tv_dac->tv_std == TV_STD_PAL_M)
 341                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 342                         else
 343                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 344                 }
 345         }
 346
 347         if (ASIC_IS_DCE3(rdev) &&
 348             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 349              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 350                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 351                 radeon_dp_set_link_config(connector, adjusted_mode);
 352         }
 353
 354         return true;
 355 }
 356
 357 static void
 358 atombios_dac_setup(struct drm_encoder *encoder, int action)
 359 {
 360         struct drm_device *dev = encoder->dev;
 361         struct radeon_device *rdev = dev->dev_private;
 362         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 363         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 364         int index = 0;
 365         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 366
 367         memset(&args, 0, sizeof(args));
 368
 369         switch (radeon_encoder->encoder_id) {
 370         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 371         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 372                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 373                 break;
 374         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 375         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 376                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 377                 break;
 378         }
 379
 380         args.ucAction = action;
 381
 382         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 383                 args.ucDacStandard = ATOM_DAC1_PS2;
 384         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 385                 args.ucDacStandard = ATOM_DAC1_CV;
 386         else {
 387                 switch (dac_info->tv_std) {
 388                 case TV_STD_PAL:
 389                 case TV_STD_PAL_M:
 390                 case TV_STD_SCART_PAL:
 391                 case TV_STD_SECAM:
 392                 case TV_STD_PAL_CN:
 393                         args.ucDacStandard = ATOM_DAC1_PAL;
 394                         break;
 395                 case TV_STD_NTSC:
 396                 case TV_STD_NTSC_J:
 397                 case TV_STD_PAL_60:
 398                 default:
 399                         args.ucDacStandard = ATOM_DAC1_NTSC;
 400                         break;
 401                 }
 402         }
 403         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 404
 405         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 406
 407 }
 408
 409 static void
 410 atombios_tv_setup(struct drm_encoder *encoder, int action)
 411 {
 412         struct drm_device *dev = encoder->dev;
 413         struct radeon_device *rdev = dev->dev_private;
 414         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 415         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 416         int index = 0;
 417         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 418
 419         memset(&args, 0, sizeof(args));
 420
 421         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 422
 423         args.sTVEncoder.ucAction = action;
 424
 425         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 426                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 427         else {
 428                 switch (dac_info->tv_std) {
 429                 case TV_STD_NTSC:
 430                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 431                         break;
 432                 case TV_STD_PAL:
 433                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 434                         break;
 435                 case TV_STD_PAL_M:
 436                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 437                         break;
 438                 case TV_STD_PAL_60:
 439                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 440                         break;
 441                 case TV_STD_NTSC_J:
 442                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 443                         break;
 444                 case TV_STD_SCART_PAL:
 445                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 446                         break;
 447                 case TV_STD_SECAM:
 448                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 449                         break;
 450                 case TV_STD_PAL_CN:
 451                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 452                         break;
 453                 default:
 454                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 455                         break;
 456                 }
 457         }
 458
 459         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 460
 461         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 462
 463 }
 464
 465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 466 {
 467         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 468         int bpc = 8;
 469
 470         if (connector)
 471                 bpc = radeon_get_monitor_bpc(connector);
 472
 473         switch (bpc) {
 474         case 0:
 475                 return PANEL_BPC_UNDEFINE;
 476         case 6:
 477                 return PANEL_6BIT_PER_COLOR;
 478         case 8:
 479         default:
 480                 return PANEL_8BIT_PER_COLOR;
 481         case 10:
 482                 return PANEL_10BIT_PER_COLOR;
 483         case 12:
 484                 return PANEL_12BIT_PER_COLOR;
 485         case 16:
 486                 return PANEL_16BIT_PER_COLOR;
 487         }
 488 }
 489
 490 union dvo_encoder_control {
 491         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 492         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 493         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 494         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 495 };
 496
 497 void
 498 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 499 {
 500         struct drm_device *dev = encoder->dev;
 501         struct radeon_device *rdev = dev->dev_private;
 502         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 503         union dvo_encoder_control args;
 504         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 505         uint8_t frev, crev;
 506
 507         memset(&args, 0, sizeof(args));
 508
 509         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 510                 return;
 511
 512         /* some R4xx chips have the wrong frev */
 513         if (rdev->family <= CHIP_RV410)
 514                 frev = 1;
 515
 516         switch (frev) {
 517         case 1:
 518                 switch (crev) {
 519                 case 1:
 520                         /* R4xx, R5xx */
 521                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 522
 523                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 524                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 525
 526                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 527                         break;
 528                 case 2:
 529                         /* RS600/690/740 */
 530                         args.dvo.sDVOEncoder.ucAction = action;
 531                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 532                         /* DFP1, CRT1, TV1 depending on the type of port */
 533                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 534
 535                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 536                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 537                         break;
 538                 case 3:
 539                         /* R6xx */
 540                         args.dvo_v3.ucAction = action;
 541                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 542                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 543                         break;
 544                 case 4:
 545                         /* DCE8 */
 546                         args.dvo_v4.ucAction = action;
 547                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 548                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 549                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 550                         break;
 551                 default:
 552                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 553                         break;
 554                 }
 555                 break;
 556         default:
 557                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 558                 break;
 559         }
 560
 561         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 562 }
 563
 564 union lvds_encoder_control {
 565         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 566         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 567 };
 568
 569 void
 570 atombios_digital_setup(struct drm_encoder *encoder, int action)
 571 {
 572         struct drm_device *dev = encoder->dev;
 573         struct radeon_device *rdev = dev->dev_private;
 574         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 575         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 576         union lvds_encoder_control args;
 577         int index = 0;
 578         int hdmi_detected = 0;
 579         uint8_t frev, crev;
 580
 581         if (!dig)
 582                 return;
 583
 584         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 585                 hdmi_detected = 1;
 586
 587         memset(&args, 0, sizeof(args));
 588
 589         switch (radeon_encoder->encoder_id) {
 590         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 591                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 592                 break;
 593         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 594         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 595                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 596                 break;
 597         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 598                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 599                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 600                 else
 601                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 602                 break;
 603         }
 604
 605         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 606                 return;
 607
 608         switch (frev) {
 609         case 1:
 610         case 2:
 611                 switch (crev) {
 612                 case 1:
 613                         args.v1.ucMisc = 0;
 614                         args.v1.ucAction = action;
 615                         if (hdmi_detected)
 616                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 617                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 618                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 619                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 620                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 621                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 622                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 623                         } else {
 624                                 if (dig->linkb)
 625                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 626                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 627                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 628                                 /*if (pScrn->rgbBits == 8) */
 629                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 630                         }
 631                         break;
 632                 case 2:
 633                 case 3:
 634                         args.v2.ucMisc = 0;
 635                         args.v2.ucAction = action;
 636                         if (crev == 3) {
 637                                 if (dig->coherent_mode)
 638                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 639                         }
 640                         if (hdmi_detected)
 641                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 642                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 643                         args.v2.ucTruncate = 0;
 644                         args.v2.ucSpatial = 0;
 645                         args.v2.ucTemporal = 0;
 646                         args.v2.ucFRC = 0;
 647                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 648                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 649                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 650                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 651                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 652                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 653                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 654                                 }
 655                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 656                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 657                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 658                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 659                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 660                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 661                                 }
 662                         } else {
 663                                 if (dig->linkb)
 664                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 665                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 666                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 667                         }
 668                         break;
 669                 default:
 670                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 671                         break;
 672                 }
 673                 break;
 674         default:
 675                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 676                 break;
 677         }
 678
 679         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 680 }
 681
 682 int
 683 atombios_get_encoder_mode(struct drm_encoder *encoder)
 684 {
 685         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 686         struct drm_connector *connector;
 687         struct radeon_connector *radeon_connector;
 688         struct radeon_connector_atom_dig *dig_connector;
 689
 690         /* dp bridges are always DP */
 691         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 692                 return ATOM_ENCODER_MODE_DP;
 693
 694         /* DVO is always DVO */
 695         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 696             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 697                 return ATOM_ENCODER_MODE_DVO;
 698
 699         connector = radeon_get_connector_for_encoder(encoder);
 700         /* if we don't have an active device yet, just use one of
 701          * the connectors tied to the encoder.
 702          */
 703         if (!connector)
 704                 connector = radeon_get_connector_for_encoder_init(encoder);
 705         radeon_connector = to_radeon_connector(connector);
 706
 707         switch (connector->connector_type) {
 708         case DRM_MODE_CONNECTOR_DVII:
 709         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 710                 if (radeon_audio != 0) {
 711                         if (radeon_connector->use_digital &&
 712                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 713                                 return ATOM_ENCODER_MODE_HDMI;
 714                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 715                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 716                                 return ATOM_ENCODER_MODE_HDMI;
 717                         else if (radeon_connector->use_digital)
 718                                 return ATOM_ENCODER_MODE_DVI;
 719                         else
 720                                 return ATOM_ENCODER_MODE_CRT;
 721                 } else if (radeon_connector->use_digital) {
 722                         return ATOM_ENCODER_MODE_DVI;
 723                 } else {
 724                         return ATOM_ENCODER_MODE_CRT;
 725                 }
 726                 break;
 727         case DRM_MODE_CONNECTOR_DVID:
 728         case DRM_MODE_CONNECTOR_HDMIA:
 729         default:
 730                 if (radeon_audio != 0) {
 731                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 732                                 return ATOM_ENCODER_MODE_HDMI;
 733                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 734                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 735                                 return ATOM_ENCODER_MODE_HDMI;
 736                         else
 737                                 return ATOM_ENCODER_MODE_DVI;
 738                 } else {
 739                         return ATOM_ENCODER_MODE_DVI;
 740                 }
 741                 break;
 742         case DRM_MODE_CONNECTOR_LVDS:
 743                 return ATOM_ENCODER_MODE_LVDS;
 744                 break;
 745         case DRM_MODE_CONNECTOR_DisplayPort:
 746                 dig_connector = radeon_connector->con_priv;
 747                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 748                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 749                         return ATOM_ENCODER_MODE_DP;
 750                 } else if (radeon_audio != 0) {
 751                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 752                                 return ATOM_ENCODER_MODE_HDMI;
 753                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 754                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 755                                 return ATOM_ENCODER_MODE_HDMI;
 756                         else
 757                                 return ATOM_ENCODER_MODE_DVI;
 758                 } else {
 759                         return ATOM_ENCODER_MODE_DVI;
 760                 }
 761                 break;
 762         case DRM_MODE_CONNECTOR_eDP:
 763                 return ATOM_ENCODER_MODE_DP;
 764         case DRM_MODE_CONNECTOR_DVIA:
 765         case DRM_MODE_CONNECTOR_VGA:
 766                 return ATOM_ENCODER_MODE_CRT;
 767                 break;
 768         case DRM_MODE_CONNECTOR_Composite:
 769         case DRM_MODE_CONNECTOR_SVIDEO:
 770         case DRM_MODE_CONNECTOR_9PinDIN:
 771                 /* fix me */
 772                 return ATOM_ENCODER_MODE_TV;
 773                 /*return ATOM_ENCODER_MODE_CV;*/
 774                 break;
 775         }
 776 }
 777
 778 /*
 779  * DIG Encoder/Transmitter Setup
 780  *
 781  * DCE 3.0/3.1
 782  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 783  * Supports up to 3 digital outputs
 784  * - 2 DIG encoder blocks.
 785  * DIG1 can drive UNIPHY link A or link B
 786  * DIG2 can drive UNIPHY link B or LVTMA
 787  *
 788  * DCE 3.2
 789  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 790  * Supports up to 5 digital outputs
 791  * - 2 DIG encoder blocks.
 792  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 793  *
 794  * DCE 4.0/5.0/6.0
 795  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 796  * Supports up to 6 digital outputs
 797  * - 6 DIG encoder blocks.
 798  * - DIG to PHY mapping is hardcoded
 799  * DIG1 drives UNIPHY0 link A, A+B
 800  * DIG2 drives UNIPHY0 link B
 801  * DIG3 drives UNIPHY1 link A, A+B
 802  * DIG4 drives UNIPHY1 link B
 803  * DIG5 drives UNIPHY2 link A, A+B
 804  * DIG6 drives UNIPHY2 link B
 805  *
 806  * DCE 4.1
 807  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 808  * Supports up to 6 digital outputs
 809  * - 2 DIG encoder blocks.
 810  * llano
 811  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 812  * ontario
 813  * DIG1 drives UNIPHY0/1/2 link A
 814  * DIG2 drives UNIPHY0/1/2 link B
 815  *
 816  * Routing
 817  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 818  * Examples:
 819  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 820  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 821  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 822  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 823  */
 824
 825 union dig_encoder_control {
 826         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 827         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 828         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 829         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 830 };
 831
 832 void
 833 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 834 {
 835         struct drm_device *dev = encoder->dev;
 836         struct radeon_device *rdev = dev->dev_private;
 837         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 838         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 839         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 840         union dig_encoder_control args;
 841         int index = 0;
 842         uint8_t frev, crev;
 843         int dp_clock = 0;
 844         int dp_lane_count = 0;
 845         int hpd_id = RADEON_HPD_NONE;
 846
 847         if (connector) {
 848                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 849                 struct radeon_connector_atom_dig *dig_connector =
 850                         radeon_connector->con_priv;
 851
 852                 dp_clock = dig_connector->dp_clock;
 853                 dp_lane_count = dig_connector->dp_lane_count;
 854                 hpd_id = radeon_connector->hpd.hpd;
 855         }
 856
 857         /* no dig encoder assigned */
 858         if (dig->dig_encoder == -1)
 859                 return;
 860
 861         memset(&args, 0, sizeof(args));
 862
 863         if (ASIC_IS_DCE4(rdev))
 864                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 865         else {
 866                 if (dig->dig_encoder)
 867                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 868                 else
 869                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 870         }
 871
 872         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 873                 return;
 874
 875         switch (frev) {
 876         case 1:
 877                 switch (crev) {
 878                 case 1:
 879                         args.v1.ucAction = action;
 880                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 881                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 882                                 args.v3.ucPanelMode = panel_mode;
 883                         else
 884                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 885
 886                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 887                                 args.v1.ucLaneNum = dp_lane_count;
 888                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 889                                 args.v1.ucLaneNum = 8;
 890                         else
 891                                 args.v1.ucLaneNum = 4;
 892
 893                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 894                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 895                         switch (radeon_encoder->encoder_id) {
 896                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 897                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 898                                 break;
 899                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 900                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 901                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 902                                 break;
 903                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 904                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 905                                 break;
 906                         }
 907                         if (dig->linkb)
 908                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 909                         else
 910                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 911                         break;
 912                 case 2:
 913                 case 3:
 914                         args.v3.ucAction = action;
 915                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 916                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 917                                 args.v3.ucPanelMode = panel_mode;
 918                         else
 919                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 920
 921                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 922                                 args.v3.ucLaneNum = dp_lane_count;
 923                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 924                                 args.v3.ucLaneNum = 8;
 925                         else
 926                                 args.v3.ucLaneNum = 4;
 927
 928                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 929                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 930                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 931                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 932                         break;
 933                 case 4:
 934                         args.v4.ucAction = action;
 935                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 936                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 937                                 args.v4.ucPanelMode = panel_mode;
 938                         else
 939                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 940
 941                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 942                                 args.v4.ucLaneNum = dp_lane_count;
 943                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 944                                 args.v4.ucLaneNum = 8;
 945                         else
 946                                 args.v4.ucLaneNum = 4;
 947
 948                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 949                                 if (dp_clock == 540000)
 950                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 951                                 else if (dp_clock == 324000)
 952                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 953                                 else if (dp_clock == 270000)
 954                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 955                                 else
 956                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 957                         }
 958                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 959                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 960                         if (hpd_id == RADEON_HPD_NONE)
 961                                 args.v4.ucHPD_ID = 0;
 962                         else
 963                                 args.v4.ucHPD_ID = hpd_id + 1;
 964                         break;
 965                 default:
 966                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 967                         break;
 968                 }
 969                 break;
 970         default:
 971                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 972                 break;
 973         }
 974
 975         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 976
 977 }
 978
 979 union dig_transmitter_control {
 980         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 981         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 982         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 983         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 984         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 985 };
 986
 987 void
 988 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 989 {
 990         struct drm_device *dev = encoder->dev;
 991         struct radeon_device *rdev = dev->dev_private;
 992         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 993         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 994         struct drm_connector *connector;
 995         union dig_transmitter_control args;
 996         int index = 0;
 997         uint8_t frev, crev;
 998         bool is_dp = false;
 999         int pll_id = 0;
1000         int dp_clock = 0;
1001         int dp_lane_count = 0;
1002         int connector_object_id = 0;
1003         int igp_lane_info = 0;
1004         int dig_encoder = dig->dig_encoder;
1005         int hpd_id = RADEON_HPD_NONE;
1006
1007         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1008                 connector = radeon_get_connector_for_encoder_init(encoder);
1009                 /* just needed to avoid bailing in the encoder check.  the encoder
1010                  * isn't used for init
1011                  */
1012                 dig_encoder = 0;
1013         } else
1014                 connector = radeon_get_connector_for_encoder(encoder);
1015
1016         if (connector) {
1017                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1018                 struct radeon_connector_atom_dig *dig_connector =
1019                         radeon_connector->con_priv;
1020
1021                 hpd_id = radeon_connector->hpd.hpd;
1022                 dp_clock = dig_connector->dp_clock;
1023                 dp_lane_count = dig_connector->dp_lane_count;
1024                 connector_object_id =
1025                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1026                 igp_lane_info = dig_connector->igp_lane_info;
1027         }
1028
1029         if (encoder->crtc) {
1030                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1031                 pll_id = radeon_crtc->pll_id;
1032         }
1033
1034         /* no dig encoder assigned */
1035         if (dig_encoder == -1)
1036                 return;
1037
1038         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1039                 is_dp = true;
1040
1041         memset(&args, 0, sizeof(args));
1042
1043         switch (radeon_encoder->encoder_id) {
1044         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1045                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1046                 break;
1047         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1048         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1049         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1050         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1051                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1052                 break;
1053         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1054                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1055                 break;
1056         }
1057
1058         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1059                 return;
1060
1061         switch (frev) {
1062         case 1:
1063                 switch (crev) {
1064                 case 1:
1065                         args.v1.ucAction = action;
1066                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1067                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1068                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1069                                 args.v1.asMode.ucLaneSel = lane_num;
1070                                 args.v1.asMode.ucLaneSet = lane_set;
1071                         } else {
1072                                 if (is_dp)
1073                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1074                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1075                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1076                                 else
1077                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1078                         }
1079
1080                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1081
1082                         if (dig_encoder)
1083                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1084                         else
1085                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1086
1087                         if ((rdev->flags & RADEON_IS_IGP) &&
1088                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1089                                 if (is_dp ||
1090                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1091                                         if (igp_lane_info & 0x1)
1092                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1093                                         else if (igp_lane_info & 0x2)
1094                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1095                                         else if (igp_lane_info & 0x4)
1096                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1097                                         else if (igp_lane_info & 0x8)
1098                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1099                                 } else {
1100                                         if (igp_lane_info & 0x3)
1101                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1102                                         else if (igp_lane_info & 0xc)
1103                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1104                                 }
1105                         }
1106
1107                         if (dig->linkb)
1108                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1109                         else
1110                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1111
1112                         if (is_dp)
1113                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1114                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1115                                 if (dig->coherent_mode)
1116                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1117                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1118                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1119                         }
1120                         break;
1121                 case 2:
1122                         args.v2.ucAction = action;
1123                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1124                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1125                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1126                                 args.v2.asMode.ucLaneSel = lane_num;
1127                                 args.v2.asMode.ucLaneSet = lane_set;
1128                         } else {
1129                                 if (is_dp)
1130                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1131                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1132                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1133                                 else
1134                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1135                         }
1136
1137                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1138                         if (dig->linkb)
1139                                 args.v2.acConfig.ucLinkSel = 1;
1140
1141                         switch (radeon_encoder->encoder_id) {
1142                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1143                                 args.v2.acConfig.ucTransmitterSel = 0;
1144                                 break;
1145                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1146                                 args.v2.acConfig.ucTransmitterSel = 1;
1147                                 break;
1148                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1149                                 args.v2.acConfig.ucTransmitterSel = 2;
1150                                 break;
1151                         }
1152
1153                         if (is_dp) {
1154                                 args.v2.acConfig.fCoherentMode = 1;
1155                                 args.v2.acConfig.fDPConnector = 1;
1156                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1157                                 if (dig->coherent_mode)
1158                                         args.v2.acConfig.fCoherentMode = 1;
1159                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1160                                         args.v2.acConfig.fDualLinkConnector = 1;
1161                         }
1162                         break;
1163                 case 3:
1164                         args.v3.ucAction = action;
1165                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1166                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1167                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1168                                 args.v3.asMode.ucLaneSel = lane_num;
1169                                 args.v3.asMode.ucLaneSet = lane_set;
1170                         } else {
1171                                 if (is_dp)
1172                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1173                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1174                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1175                                 else
1176                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1177                         }
1178
1179                         if (is_dp)
1180                                 args.v3.ucLaneNum = dp_lane_count;
1181                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1182                                 args.v3.ucLaneNum = 8;
1183                         else
1184                                 args.v3.ucLaneNum = 4;
1185
1186                         if (dig->linkb)
1187                                 args.v3.acConfig.ucLinkSel = 1;
1188                         if (dig_encoder & 1)
1189                                 args.v3.acConfig.ucEncoderSel = 1;
1190
1191                         /* Select the PLL for the PHY
1192                          * DP PHY should be clocked from external src if there is
1193                          * one.
1194                          */
1195                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1196                         if (is_dp && rdev->clock.dp_extclk)
1197                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1198                         else
1199                                 args.v3.acConfig.ucRefClkSource = pll_id;
1200
1201                         switch (radeon_encoder->encoder_id) {
1202                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1203                                 args.v3.acConfig.ucTransmitterSel = 0;
1204                                 break;
1205                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1206                                 args.v3.acConfig.ucTransmitterSel = 1;
1207                                 break;
1208                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1209                                 args.v3.acConfig.ucTransmitterSel = 2;
1210                                 break;
1211                         }
1212
1213                         if (is_dp)
1214                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1215                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1216                                 if (dig->coherent_mode)
1217                                         args.v3.acConfig.fCoherentMode = 1;
1218                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1219                                         args.v3.acConfig.fDualLinkConnector = 1;
1220                         }
1221                         break;
1222                 case 4:
1223                         args.v4.ucAction = action;
1224                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1225                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1226                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1227                                 args.v4.asMode.ucLaneSel = lane_num;
1228                                 args.v4.asMode.ucLaneSet = lane_set;
1229                         } else {
1230                                 if (is_dp)
1231                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1232                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1233                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1234                                 else
1235                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1236                         }
1237
1238                         if (is_dp)
1239                                 args.v4.ucLaneNum = dp_lane_count;
1240                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1241                                 args.v4.ucLaneNum = 8;
1242                         else
1243                                 args.v4.ucLaneNum = 4;
1244
1245                         if (dig->linkb)
1246                                 args.v4.acConfig.ucLinkSel = 1;
1247                         if (dig_encoder & 1)
1248                                 args.v4.acConfig.ucEncoderSel = 1;
1249
1250                         /* Select the PLL for the PHY
1251                          * DP PHY should be clocked from external src if there is
1252                          * one.
1253                          */
1254                         /* On DCE5 DCPLL usually generates the DP ref clock */
1255                         if (is_dp) {
1256                                 if (rdev->clock.dp_extclk)
1257                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1258                                 else
1259                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1260                         } else
1261                                 args.v4.acConfig.ucRefClkSource = pll_id;
1262
1263                         switch (radeon_encoder->encoder_id) {
1264                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1265                                 args.v4.acConfig.ucTransmitterSel = 0;
1266                                 break;
1267                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1268                                 args.v4.acConfig.ucTransmitterSel = 1;
1269                                 break;
1270                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1271                                 args.v4.acConfig.ucTransmitterSel = 2;
1272                                 break;
1273                         }
1274
1275                         if (is_dp)
1276                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1277                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1278                                 if (dig->coherent_mode)
1279                                         args.v4.acConfig.fCoherentMode = 1;
1280                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1281                                         args.v4.acConfig.fDualLinkConnector = 1;
1282                         }
1283                         break;
1284                 case 5:
1285                         args.v5.ucAction = action;
1286                         if (is_dp)
1287                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1288                         else
1289                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1290
1291                         switch (radeon_encoder->encoder_id) {
1292                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1293                                 if (dig->linkb)
1294                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1295                                 else
1296                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1297                                 break;
1298                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1299                                 if (dig->linkb)
1300                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1301                                 else
1302                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1303                                 break;
1304                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1305                                 if (dig->linkb)
1306                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1307                                 else
1308                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1309                                 break;
1310                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1311                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1312                                 break;
1313                         }
1314                         if (is_dp)
1315                                 args.v5.ucLaneNum = dp_lane_count;
1316                         else if (radeon_encoder->pixel_clock > 165000)
1317                                 args.v5.ucLaneNum = 8;
1318                         else
1319                                 args.v5.ucLaneNum = 4;
1320                         args.v5.ucConnObjId = connector_object_id;
1321                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1322
1323                         if (is_dp && rdev->clock.dp_extclk)
1324                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1325                         else
1326                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1327
1328                         if (is_dp)
1329                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1330                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1331                                 if (dig->coherent_mode)
1332                                         args.v5.asConfig.ucCoherentMode = 1;
1333                         }
1334                         if (hpd_id == RADEON_HPD_NONE)
1335                                 args.v5.asConfig.ucHPDSel = 0;
1336                         else
1337                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1338                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1339                         args.v5.ucDPLaneSet = lane_set;
1340                         break;
1341                 default:
1342                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1343                         break;
1344                 }
1345                 break;
1346         default:
1347                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1348                 break;
1349         }
1350
1351         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1352 }
1353
1354 bool
1355 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1356 {
1357         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1358         struct drm_device *dev = radeon_connector->base.dev;
1359         struct radeon_device *rdev = dev->dev_private;
1360         union dig_transmitter_control args;
1361         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1362         uint8_t frev, crev;
1363
1364         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1365                 goto done;
1366
1367         if (!ASIC_IS_DCE4(rdev))
1368                 goto done;
1369
1370         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1371             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1372                 goto done;
1373
1374         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1375                 goto done;
1376
1377         memset(&args, 0, sizeof(args));
1378
1379         args.v1.ucAction = action;
1380
1381         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1382
1383         /* wait for the panel to power up */
1384         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1385                 int i;
1386
1387                 for (i = 0; i < 300; i++) {
1388                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1389                                 return true;
1390                         mdelay(1);
1391                 }
1392                 return false;
1393         }
1394 done:
1395         return true;
1396 }
1397
1398 union external_encoder_control {
1399         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1400         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1401 };
1402
1403 static void
1404 atombios_external_encoder_setup(struct drm_encoder *encoder,
1405                                 struct drm_encoder *ext_encoder,
1406                                 int action)
1407 {
1408         struct drm_device *dev = encoder->dev;
1409         struct radeon_device *rdev = dev->dev_private;
1410         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1411         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1412         union external_encoder_control args;
1413         struct drm_connector *connector;
1414         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1415         u8 frev, crev;
1416         int dp_clock = 0;
1417         int dp_lane_count = 0;
1418         int connector_object_id = 0;
1419         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1420
1421         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1422                 connector = radeon_get_connector_for_encoder_init(encoder);
1423         else
1424                 connector = radeon_get_connector_for_encoder(encoder);
1425
1426         if (connector) {
1427                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1428                 struct radeon_connector_atom_dig *dig_connector =
1429                         radeon_connector->con_priv;
1430
1431                 dp_clock = dig_connector->dp_clock;
1432                 dp_lane_count = dig_connector->dp_lane_count;
1433                 connector_object_id =
1434                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1435         }
1436
1437         memset(&args, 0, sizeof(args));
1438
1439         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1440                 return;
1441
1442         switch (frev) {
1443         case 1:
1444                 /* no params on frev 1 */
1445                 break;
1446         case 2:
1447                 switch (crev) {
1448                 case 1:
1449                 case 2:
1450                         args.v1.sDigEncoder.ucAction = action;
1451                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1452                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1453
1454                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1455                                 if (dp_clock == 270000)
1456                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1457                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1458                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1459                                 args.v1.sDigEncoder.ucLaneNum = 8;
1460                         else
1461                                 args.v1.sDigEncoder.ucLaneNum = 4;
1462                         break;
1463                 case 3:
1464                         args.v3.sExtEncoder.ucAction = action;
1465                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1466                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1467                         else
1468                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1469                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1470
1471                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1472                                 if (dp_clock == 270000)
1473                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1474                                 else if (dp_clock == 540000)
1475                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1476                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1477                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1478                                 args.v3.sExtEncoder.ucLaneNum = 8;
1479                         else
1480                                 args.v3.sExtEncoder.ucLaneNum = 4;
1481                         switch (ext_enum) {
1482                         case GRAPH_OBJECT_ENUM_ID1:
1483                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1484                                 break;
1485                         case GRAPH_OBJECT_ENUM_ID2:
1486                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1487                                 break;
1488                         case GRAPH_OBJECT_ENUM_ID3:
1489                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1490                                 break;
1491                         }
1492                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1493                         break;
1494                 default:
1495                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1496                         return;
1497                 }
1498                 break;
1499         default:
1500                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1501                 return;
1502         }
1503         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1504 }
1505
1506 static void
1507 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1508 {
1509         struct drm_device *dev = encoder->dev;
1510         struct radeon_device *rdev = dev->dev_private;
1511         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1512         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1513         ENABLE_YUV_PS_ALLOCATION args;
1514         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1515         uint32_t temp, reg;
1516
1517         memset(&args, 0, sizeof(args));
1518
1519         if (rdev->family >= CHIP_R600)
1520                 reg = R600_BIOS_3_SCRATCH;
1521         else
1522                 reg = RADEON_BIOS_3_SCRATCH;
1523
1524         /* XXX: fix up scratch reg handling */
1525         temp = RREG32(reg);
1526         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1527                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1528                              (radeon_crtc->crtc_id << 18)));
1529         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1530                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1531         else
1532                 WREG32(reg, 0);
1533
1534         if (enable)
1535                 args.ucEnable = ATOM_ENABLE;
1536         args.ucCRTC = radeon_crtc->crtc_id;
1537
1538         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1539
1540         WREG32(reg, temp);
1541 }
1542
1543 static void
1544 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1545 {
1546         struct drm_device *dev = encoder->dev;
1547         struct radeon_device *rdev = dev->dev_private;
1548         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1549         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1550         int index = 0;
1551
1552         memset(&args, 0, sizeof(args));
1553
1554         switch (radeon_encoder->encoder_id) {
1555         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1556         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1557                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1558                 break;
1559         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1560         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1561         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1562                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1563                 break;
1564         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1565                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1566                 break;
1567         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1568                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1569                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1570                 else
1571                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1572                 break;
1573         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1574         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1575                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1576                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1577                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1578                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1579                 else
1580                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1581                 break;
1582         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1583         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1584                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1585                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1586                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1587                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1588                 else
1589                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1590                 break;
1591         default:
1592                 return;
1593         }
1594
1595         switch (mode) {
1596         case DRM_MODE_DPMS_ON:
1597                 args.ucAction = ATOM_ENABLE;
1598                 /* workaround for DVOOutputControl on some RS690 systems */
1599                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1600                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1601                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1602                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1603                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1604                 } else
1605                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1606                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1607                         args.ucAction = ATOM_LCD_BLON;
1608                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1609                 }
1610                 break;
1611         case DRM_MODE_DPMS_STANDBY:
1612         case DRM_MODE_DPMS_SUSPEND:
1613         case DRM_MODE_DPMS_OFF:
1614                 args.ucAction = ATOM_DISABLE;
1615                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1616                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1617                         args.ucAction = ATOM_LCD_BLOFF;
1618                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1619                 }
1620                 break;
1621         }
1622 }
1623
1624 static void
1625 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1626 {
1627         struct drm_device *dev = encoder->dev;
1628         struct radeon_device *rdev = dev->dev_private;
1629         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1630         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1631         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1632         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1633         struct radeon_connector *radeon_connector = NULL;
1634         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1635
1636         if (connector) {
1637                 radeon_connector = to_radeon_connector(connector);
1638                 radeon_dig_connector = radeon_connector->con_priv;
1639         }
1640
1641         switch (mode) {
1642         case DRM_MODE_DPMS_ON:
1643                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1644                         if (!connector)
1645                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1646                         else
1647                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1648
1649                         /* setup and enable the encoder */
1650                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1651                         atombios_dig_encoder_setup(encoder,
1652                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1653                                                    dig->panel_mode);
1654                         if (ext_encoder) {
1655                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1656                                         atombios_external_encoder_setup(encoder, ext_encoder,
1657                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1658                         }
1659                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1660                 } else if (ASIC_IS_DCE4(rdev)) {
1661                         /* setup and enable the encoder */
1662                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1663                         /* enable the transmitter */
1664                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1665                 } else {
1666                         /* setup and enable the encoder and transmitter */
1667                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1668                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1669                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1670                 }
1671                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1672                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1673                                 atombios_set_edp_panel_power(connector,
1674                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1675                                 radeon_dig_connector->edp_on = true;
1676                         }
1677                         radeon_dp_link_train(encoder, connector);
1678                         if (ASIC_IS_DCE4(rdev))
1679                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1680                 }
1681                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1682                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1683                 break;
1684         case DRM_MODE_DPMS_STANDBY:
1685         case DRM_MODE_DPMS_SUSPEND:
1686         case DRM_MODE_DPMS_OFF:
1687                 if (ASIC_IS_DCE4(rdev)) {
1688                         /* disable the transmitter */
1689                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1690                 } else {
1691                         /* disable the encoder and transmitter */
1692                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1693                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1694                 }
1695                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1696                         if (ASIC_IS_DCE4(rdev))
1697                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1698                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1699                                 atombios_set_edp_panel_power(connector,
1700                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1701                                 radeon_dig_connector->edp_on = false;
1702                         }
1703                 }
1704                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1705                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1706                 break;
1707         }
1708 }
1709
1710 static void
1711 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1712                              struct drm_encoder *ext_encoder,
1713                              int mode)
1714 {
1715         struct drm_device *dev = encoder->dev;
1716         struct radeon_device *rdev = dev->dev_private;
1717
1718         switch (mode) {
1719         case DRM_MODE_DPMS_ON:
1720         default:
1721                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1722                         atombios_external_encoder_setup(encoder, ext_encoder,
1723                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1724                         atombios_external_encoder_setup(encoder, ext_encoder,
1725                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1726                 } else
1727                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1728                 break;
1729         case DRM_MODE_DPMS_STANDBY:
1730         case DRM_MODE_DPMS_SUSPEND:
1731         case DRM_MODE_DPMS_OFF:
1732                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1733                         atombios_external_encoder_setup(encoder, ext_encoder,
1734                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1735                         atombios_external_encoder_setup(encoder, ext_encoder,
1736                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1737                 } else
1738                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1739                 break;
1740         }
1741 }
1742
1743 static void
1744 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1745 {
1746         struct drm_device *dev = encoder->dev;
1747         struct radeon_device *rdev = dev->dev_private;
1748         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1749         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1750
1751         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1752                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1753                   radeon_encoder->active_device);
1754         switch (radeon_encoder->encoder_id) {
1755         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1756         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1757         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1758         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1759         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1760         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1761         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1762         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1763                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1764                 break;
1765         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1766         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1767         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1768         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1769         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1770                 radeon_atom_encoder_dpms_dig(encoder, mode);
1771                 break;
1772         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1773                 if (ASIC_IS_DCE5(rdev)) {
1774                         switch (mode) {
1775                         case DRM_MODE_DPMS_ON:
1776                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1777                                 break;
1778                         case DRM_MODE_DPMS_STANDBY:
1779                         case DRM_MODE_DPMS_SUSPEND:
1780                         case DRM_MODE_DPMS_OFF:
1781                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1782                                 break;
1783                         }
1784                 } else if (ASIC_IS_DCE3(rdev))
1785                         radeon_atom_encoder_dpms_dig(encoder, mode);
1786                 else
1787                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1788                 break;
1789         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1790         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1791                 if (ASIC_IS_DCE5(rdev)) {
1792                         switch (mode) {
1793                         case DRM_MODE_DPMS_ON:
1794                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1795                                 break;
1796                         case DRM_MODE_DPMS_STANDBY:
1797                         case DRM_MODE_DPMS_SUSPEND:
1798                         case DRM_MODE_DPMS_OFF:
1799                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1800                                 break;
1801                         }
1802                 } else
1803                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1804                 break;
1805         default:
1806                 return;
1807         }
1808
1809         if (ext_encoder)
1810                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1811
1812         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1813
1814 }
1815
1816 union crtc_source_param {
1817         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1818         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1819 };
1820
1821 static void
1822 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1823 {
1824         struct drm_device *dev = encoder->dev;
1825         struct radeon_device *rdev = dev->dev_private;
1826         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1827         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1828         union crtc_source_param args;
1829         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1830         uint8_t frev, crev;
1831         struct radeon_encoder_atom_dig *dig;
1832
1833         memset(&args, 0, sizeof(args));
1834
1835         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1836                 return;
1837
1838         switch (frev) {
1839         case 1:
1840                 switch (crev) {
1841                 case 1:
1842                 default:
1843                         if (ASIC_IS_AVIVO(rdev))
1844                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1845                         else {
1846                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1847                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1848                                 } else {
1849                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1850                                 }
1851                         }
1852                         switch (radeon_encoder->encoder_id) {
1853                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1854                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1855                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1856                                 break;
1857                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1858                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1859                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1860                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1861                                 else
1862                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1863                                 break;
1864                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1865                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1866                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1867                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1868                                 break;
1869                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1870                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1871                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1872                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1873                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1874                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1875                                 else
1876                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1877                                 break;
1878                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1879                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1880                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1881                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1882                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1883                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1884                                 else
1885                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1886                                 break;
1887                         }
1888                         break;
1889                 case 2:
1890                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1891                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1892                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1893
1894                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1895                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1896                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1897                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1898                                 else
1899                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1900                         } else
1901                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1902                         switch (radeon_encoder->encoder_id) {
1903                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1904                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1905                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1906                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1907                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1908                                 dig = radeon_encoder->enc_priv;
1909                                 switch (dig->dig_encoder) {
1910                                 case 0:
1911                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1912                                         break;
1913                                 case 1:
1914                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1915                                         break;
1916                                 case 2:
1917                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1918                                         break;
1919                                 case 3:
1920                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1921                                         break;
1922                                 case 4:
1923                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1924                                         break;
1925                                 case 5:
1926                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1927                                         break;
1928                                 case 6:
1929                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1930                                         break;
1931                                 }
1932                                 break;
1933                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1934                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1935                                 break;
1936                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1937                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1938                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1939                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1940                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1941                                 else
1942                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1943                                 break;
1944                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1945                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1946                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1947                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1948                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1949                                 else
1950                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1951                                 break;
1952                         }
1953                         break;
1954                 }
1955                 break;
1956         default:
1957                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1958                 return;
1959         }
1960
1961         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1962
1963         /* update scratch regs with new routing */
1964         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1965 }
1966
1967 static void
1968 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1969                               struct drm_display_mode *mode)
1970 {
1971         struct drm_device *dev = encoder->dev;
1972         struct radeon_device *rdev = dev->dev_private;
1973         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1974         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1975
1976         /* Funky macbooks */
1977         if ((dev->pdev->device == 0x71C5) &&
1978             (dev->pdev->subsystem_vendor == 0x106b) &&
1979             (dev->pdev->subsystem_device == 0x0080)) {
1980                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1981                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1982
1983                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1984                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1985
1986                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1987                 }
1988         }
1989
1990         /* set scaler clears this on some chips */
1991         if (ASIC_IS_AVIVO(rdev) &&
1992             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1993                 if (ASIC_IS_DCE8(rdev)) {
1994                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1995                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1996                                        CIK_INTERLEAVE_EN);
1997                         else
1998                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1999                 } else if (ASIC_IS_DCE4(rdev)) {
2000                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2001                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2002                                        EVERGREEN_INTERLEAVE_EN);
2003                         else
2004                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2005                 } else {
2006                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2007                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2008                                        AVIVO_D1MODE_INTERLEAVE_EN);
2009                         else
2010                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2011                 }
2012         }
2013 }
2014
2015 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2016 {
2017         struct drm_device *dev = encoder->dev;
2018         struct radeon_device *rdev = dev->dev_private;
2019         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2020         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2021         struct drm_encoder *test_encoder;
2022         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2023         uint32_t dig_enc_in_use = 0;
2024
2025         if (ASIC_IS_DCE6(rdev)) {
2026                 /* DCE6 */
2027                 switch (radeon_encoder->encoder_id) {
2028                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2029                         if (dig->linkb)
2030                                 return 1;
2031                         else
2032                                 return 0;
2033                         break;
2034                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2035                         if (dig->linkb)
2036                                 return 3;
2037                         else
2038                                 return 2;
2039                         break;
2040                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2041                         if (dig->linkb)
2042                                 return 5;
2043                         else
2044                                 return 4;
2045                         break;
2046                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2047                         return 6;
2048                         break;
2049                 }
2050         } else if (ASIC_IS_DCE4(rdev)) {
2051                 /* DCE4/5 */
2052                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2053                         /* ontario follows DCE4 */
2054                         if (rdev->family == CHIP_PALM) {
2055                                 if (dig->linkb)
2056                                         return 1;
2057                                 else
2058                                         return 0;
2059                         } else
2060                                 /* llano follows DCE3.2 */
2061                                 return radeon_crtc->crtc_id;
2062                 } else {
2063                         switch (radeon_encoder->encoder_id) {
2064                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2065                                 if (dig->linkb)
2066                                         return 1;
2067                                 else
2068                                         return 0;
2069                                 break;
2070                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2071                                 if (dig->linkb)
2072                                         return 3;
2073                                 else
2074                                         return 2;
2075                                 break;
2076                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2077                                 if (dig->linkb)
2078                                         return 5;
2079                                 else
2080                                         return 4;
2081                                 break;
2082                         }
2083                 }
2084         }
2085
2086         /* on DCE32 and encoder can driver any block so just crtc id */
2087         if (ASIC_IS_DCE32(rdev)) {
2088                 return radeon_crtc->crtc_id;
2089         }
2090
2091         /* on DCE3 - LVTMA can only be driven by DIGB */
2092         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2093                 struct radeon_encoder *radeon_test_encoder;
2094
2095                 if (encoder == test_encoder)
2096                         continue;
2097
2098                 if (!radeon_encoder_is_digital(test_encoder))
2099                         continue;
2100
2101                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2102                 dig = radeon_test_encoder->enc_priv;
2103
2104                 if (dig->dig_encoder >= 0)
2105                         dig_enc_in_use |= (1 << dig->dig_encoder);
2106         }
2107
2108         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2109                 if (dig_enc_in_use & 0x2)
2110                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2111                 return 1;
2112         }
2113         if (!(dig_enc_in_use & 1))
2114                 return 0;
2115         return 1;
2116 }
2117
2118 /* This only needs to be called once at startup */
2119 void
2120 radeon_atom_encoder_init(struct radeon_device *rdev)
2121 {
2122         struct drm_device *dev = rdev->ddev;
2123         struct drm_encoder *encoder;
2124
2125         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2126                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2127                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2128
2129                 switch (radeon_encoder->encoder_id) {
2130                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2132                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2133                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2134                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2135                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2136                         break;
2137                 default:
2138                         break;
2139                 }
2140
2141                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2142                         atombios_external_encoder_setup(encoder, ext_encoder,
2143                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2144         }
2145 }
2146
2147 static void
2148 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2149                              struct drm_display_mode *mode,
2150                              struct drm_display_mode *adjusted_mode)
2151 {
2152         struct drm_device *dev = encoder->dev;
2153         struct radeon_device *rdev = dev->dev_private;
2154         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2155
2156         radeon_encoder->pixel_clock = adjusted_mode->clock;
2157
2158         /* need to call this here rather than in prepare() since we need some crtc info */
2159         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2160
2161         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2162                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2163                         atombios_yuv_setup(encoder, true);
2164                 else
2165                         atombios_yuv_setup(encoder, false);
2166         }
2167
2168         switch (radeon_encoder->encoder_id) {
2169         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2170         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2171         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2172         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2173                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2174                 break;
2175         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2176         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2177         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2178         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2179         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2180                 /* handled in dpms */
2181                 break;
2182         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2183         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2184         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2185                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2186                 break;
2187         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2188         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2189         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2190         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2191                 atombios_dac_setup(encoder, ATOM_ENABLE);
2192                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2193                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2194                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2195                         else
2196                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2197                 }
2198                 break;
2199         }
2200
2201         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2202
2203         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2204                 if (rdev->asic->display.hdmi_enable)
2205                         radeon_hdmi_enable(rdev, encoder, true);
2206                 if (rdev->asic->display.hdmi_setmode)
2207                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2208         }
2209 }
2210
2211 static bool
2212 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2213 {
2214         struct drm_device *dev = encoder->dev;
2215         struct radeon_device *rdev = dev->dev_private;
2216         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2217         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2218
2219         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2220                                        ATOM_DEVICE_CV_SUPPORT |
2221                                        ATOM_DEVICE_CRT_SUPPORT)) {
2222                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2223                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2224                 uint8_t frev, crev;
2225
2226                 memset(&args, 0, sizeof(args));
2227
2228                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2229                         return false;
2230
2231                 args.sDacload.ucMisc = 0;
2232
2233                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2234                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2235                         args.sDacload.ucDacType = ATOM_DAC_A;
2236                 else
2237                         args.sDacload.ucDacType = ATOM_DAC_B;
2238
2239                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2240                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2241                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2242                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2243                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2244                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2245                         if (crev >= 3)
2246                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2247                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2248                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2249                         if (crev >= 3)
2250                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2251                 }
2252
2253                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2254
2255                 return true;
2256         } else
2257                 return false;
2258 }
2259
2260 static enum drm_connector_status
2261 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2262 {
2263         struct drm_device *dev = encoder->dev;
2264         struct radeon_device *rdev = dev->dev_private;
2265         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2266         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2267         uint32_t bios_0_scratch;
2268
2269         if (!atombios_dac_load_detect(encoder, connector)) {
2270                 DRM_DEBUG_KMS("detect returned false \n");
2271                 return connector_status_unknown;
2272         }
2273
2274         if (rdev->family >= CHIP_R600)
2275                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2276         else
2277                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2278
2279         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2280         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2281                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2282                         return connector_status_connected;
2283         }
2284         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2285                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2286                         return connector_status_connected;
2287         }
2288         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2289                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2290                         return connector_status_connected;
2291         }
2292         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2293                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2294                         return connector_status_connected; /* CTV */
2295                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2296                         return connector_status_connected; /* STV */
2297         }
2298         return connector_status_disconnected;
2299 }
2300
2301 static enum drm_connector_status
2302 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2303 {
2304         struct drm_device *dev = encoder->dev;
2305         struct radeon_device *rdev = dev->dev_private;
2306         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2307         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2308         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2309         u32 bios_0_scratch;
2310
2311         if (!ASIC_IS_DCE4(rdev))
2312                 return connector_status_unknown;
2313
2314         if (!ext_encoder)
2315                 return connector_status_unknown;
2316
2317         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2318                 return connector_status_unknown;
2319
2320         /* load detect on the dp bridge */
2321         atombios_external_encoder_setup(encoder, ext_encoder,
2322                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2323
2324         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2325
2326         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2327         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2328                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2329                         return connector_status_connected;
2330         }
2331         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2332                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2333                         return connector_status_connected;
2334         }
2335         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2336                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2337                         return connector_status_connected;
2338         }
2339         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2340                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2341                         return connector_status_connected; /* CTV */
2342                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2343                         return connector_status_connected; /* STV */
2344         }
2345         return connector_status_disconnected;
2346 }
2347
2348 void
2349 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2350 {
2351         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2352
2353         if (ext_encoder)
2354                 /* ddc_setup on the dp bridge */
2355                 atombios_external_encoder_setup(encoder, ext_encoder,
2356                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2357
2358 }
2359
2360 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2361 {
2362         struct radeon_device *rdev = encoder->dev->dev_private;
2363         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2364         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2365
2366         if ((radeon_encoder->active_device &
2367              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2368             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2369              ENCODER_OBJECT_ID_NONE)) {
2370                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2371                 if (dig) {
2372                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2373                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2374                                 if (rdev->family >= CHIP_R600)
2375                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2376                                 else
2377                                         /* RS600/690/740 have only 1 afmt block */
2378                                         dig->afmt = rdev->mode_info.afmt[0];
2379                         }
2380                 }
2381         }
2382
2383         radeon_atom_output_lock(encoder, true);
2384
2385         if (connector) {
2386                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2387
2388                 /* select the clock/data port if it uses a router */
2389                 if (radeon_connector->router.cd_valid)
2390                         radeon_router_select_cd_port(radeon_connector);
2391
2392                 /* turn eDP panel on for mode set */
2393                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2394                         atombios_set_edp_panel_power(connector,
2395                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2396         }
2397
2398         /* this is needed for the pll/ss setup to work correctly in some cases */
2399         atombios_set_encoder_crtc_source(encoder);
2400         /* set up the FMT blocks */
2401         if (ASIC_IS_DCE8(rdev))
2402                 dce8_program_fmt(encoder);
2403         else if (ASIC_IS_DCE4(rdev))
2404                 dce4_program_fmt(encoder);
2405         else if (ASIC_IS_DCE3(rdev))
2406                 dce3_program_fmt(encoder);
2407         else if (ASIC_IS_AVIVO(rdev))
2408                 avivo_program_fmt(encoder);
2409 }
2410
2411 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2412 {
2413         /* need to call this here as we need the crtc set up */
2414         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2415         radeon_atom_output_lock(encoder, false);
2416 }
2417
2418 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2419 {
2420         struct drm_device *dev = encoder->dev;
2421         struct radeon_device *rdev = dev->dev_private;
2422         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2423         struct radeon_encoder_atom_dig *dig;
2424
2425         /* check for pre-DCE3 cards with shared encoders;
2426          * can't really use the links individually, so don't disable
2427          * the encoder if it's in use by another connector
2428          */
2429         if (!ASIC_IS_DCE3(rdev)) {
2430                 struct drm_encoder *other_encoder;
2431                 struct radeon_encoder *other_radeon_encoder;
2432
2433                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2434                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2435                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2436                             drm_helper_encoder_in_use(other_encoder))
2437                                 goto disable_done;
2438                 }
2439         }
2440
2441         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2442
2443         switch (radeon_encoder->encoder_id) {
2444         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2445         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2446         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2447         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2448                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2449                 break;
2450         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2451         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2452         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2453         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2454         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2455                 /* handled in dpms */
2456                 break;
2457         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2458         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2459         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2460                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2461                 break;
2462         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2463         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2464         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2465         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2466                 atombios_dac_setup(encoder, ATOM_DISABLE);
2467                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2468                         atombios_tv_setup(encoder, ATOM_DISABLE);
2469                 break;
2470         }
2471
2472 disable_done:
2473         if (radeon_encoder_is_digital(encoder)) {
2474                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2475                         if (rdev->asic->display.hdmi_enable)
2476                                 radeon_hdmi_enable(rdev, encoder, false);
2477                 }
2478                 dig = radeon_encoder->enc_priv;
2479                 dig->dig_encoder = -1;
2480         }
2481         radeon_encoder->active_device = 0;
2482 }
2483
2484 /* these are handled by the primary encoders */
2485 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2486 {
2487
2488 }
2489
2490 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2491 {
2492
2493 }
2494
2495 static void
2496 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2497                          struct drm_display_mode *mode,
2498                          struct drm_display_mode *adjusted_mode)
2499 {
2500
2501 }
2502
2503 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2504 {
2505
2506 }
2507
2508 static void
2509 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2510 {
2511
2512 }
2513
2514 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2515                                        const struct drm_display_mode *mode,
2516                                        struct drm_display_mode *adjusted_mode)
2517 {
2518         return true;
2519 }
2520
2521 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2522         .dpms = radeon_atom_ext_dpms,
2523         .mode_fixup = radeon_atom_ext_mode_fixup,
2524         .prepare = radeon_atom_ext_prepare,
2525         .mode_set = radeon_atom_ext_mode_set,
2526         .commit = radeon_atom_ext_commit,
2527         .disable = radeon_atom_ext_disable,
2528         /* no detect for TMDS/LVDS yet */
2529 };
2530
2531 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2532         .dpms = radeon_atom_encoder_dpms,
2533         .mode_fixup = radeon_atom_mode_fixup,
2534         .prepare = radeon_atom_encoder_prepare,
2535         .mode_set = radeon_atom_encoder_mode_set,
2536         .commit = radeon_atom_encoder_commit,
2537         .disable = radeon_atom_encoder_disable,
2538         .detect = radeon_atom_dig_detect,
2539 };
2540
2541 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2542         .dpms = radeon_atom_encoder_dpms,
2543         .mode_fixup = radeon_atom_mode_fixup,
2544         .prepare = radeon_atom_encoder_prepare,
2545         .mode_set = radeon_atom_encoder_mode_set,
2546         .commit = radeon_atom_encoder_commit,
2547         .detect = radeon_atom_dac_detect,
2548 };
2549
2550 void radeon_enc_destroy(struct drm_encoder *encoder)
2551 {
2552         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2553         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2554                 radeon_atom_backlight_exit(radeon_encoder);
2555         kfree(radeon_encoder->enc_priv);
2556         drm_encoder_cleanup(encoder);
2557         kfree(radeon_encoder);
2558 }
2559
2560 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2561         .destroy = radeon_enc_destroy,
2562 };
2563
2564 static struct radeon_encoder_atom_dac *
2565 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2566 {
2567         struct drm_device *dev = radeon_encoder->base.dev;
2568         struct radeon_device *rdev = dev->dev_private;
2569         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2570
2571         if (!dac)
2572                 return NULL;
2573
2574         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2575         return dac;
2576 }
2577
2578 static struct radeon_encoder_atom_dig *
2579 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2580 {
2581         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2582         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2583
2584         if (!dig)
2585                 return NULL;
2586
2587         /* coherent mode by default */
2588         dig->coherent_mode = true;
2589         dig->dig_encoder = -1;
2590
2591         if (encoder_enum == 2)
2592                 dig->linkb = true;
2593         else
2594                 dig->linkb = false;
2595
2596         return dig;
2597 }
2598
2599 void
2600 radeon_add_atom_encoder(struct drm_device *dev,
2601                         uint32_t encoder_enum,
2602                         uint32_t supported_device,
2603                         u16 caps)
2604 {
2605         struct radeon_device *rdev = dev->dev_private;
2606         struct drm_encoder *encoder;
2607         struct radeon_encoder *radeon_encoder;
2608
2609         /* see if we already added it */
2610         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2611                 radeon_encoder = to_radeon_encoder(encoder);
2612                 if (radeon_encoder->encoder_enum == encoder_enum) {
2613                         radeon_encoder->devices |= supported_device;
2614                         return;
2615                 }
2616
2617         }
2618
2619         /* add a new one */
2620         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2621         if (!radeon_encoder)
2622                 return;
2623
2624         encoder = &radeon_encoder->base;
2625         switch (rdev->num_crtc) {
2626         case 1:
2627                 encoder->possible_crtcs = 0x1;
2628                 break;
2629         case 2:
2630         default:
2631                 encoder->possible_crtcs = 0x3;
2632                 break;
2633         case 4:
2634                 encoder->possible_crtcs = 0xf;
2635                 break;
2636         case 6:
2637                 encoder->possible_crtcs = 0x3f;
2638                 break;
2639         }
2640
2641         radeon_encoder->enc_priv = NULL;
2642
2643         radeon_encoder->encoder_enum = encoder_enum;
2644         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2645         radeon_encoder->devices = supported_device;
2646         radeon_encoder->rmx_type = RMX_OFF;
2647         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2648         radeon_encoder->is_ext_encoder = false;
2649         radeon_encoder->caps = caps;
2650
2651         switch (radeon_encoder->encoder_id) {
2652         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2653         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2654         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2655         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2656                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2657                         radeon_encoder->rmx_type = RMX_FULL;
2658                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2659                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2660                 } else {
2661                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2662                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2663                 }
2664                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2665                 break;
2666         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2667                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2668                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2669                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2670                 break;
2671         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2672         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2673         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2674                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2675                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2676                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2677                 break;
2678         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2679         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2680         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2681         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2682         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2683         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2684         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2685         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2686                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2687                         radeon_encoder->rmx_type = RMX_FULL;
2688                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2689                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2690                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2691                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2692                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2693                 } else {
2694                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2695                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2696                 }
2697                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2698                 break;
2699         case ENCODER_OBJECT_ID_SI170B:
2700         case ENCODER_OBJECT_ID_CH7303:
2701         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2702         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2703         case ENCODER_OBJECT_ID_TITFP513:
2704         case ENCODER_OBJECT_ID_VT1623:
2705         case ENCODER_OBJECT_ID_HDMI_SI1930:
2706         case ENCODER_OBJECT_ID_TRAVIS:
2707         case ENCODER_OBJECT_ID_NUTMEG:
2708                 /* these are handled by the primary encoders */
2709                 radeon_encoder->is_ext_encoder = true;
2710                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2711                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2712                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2713                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2714                 else
2715                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2716                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2717                 break;
2718         }
2719 }