drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define R700_PFP_UCODE_SIZE 848
  42 #define R700_PM4_UCODE_SIZE 1360
  43
  44 /* Firmware Names */
  45 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  46 MODULE_FIRMWARE("radeon/R600_me.bin");
  47 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  48 MODULE_FIRMWARE("radeon/RV610_me.bin");
  49 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV630_me.bin");
  51 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV620_me.bin");
  53 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV635_me.bin");
  55 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV670_me.bin");
  57 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RS780_me.bin");
  59 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV770_me.bin");
  61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV730_me.bin");
  63 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV710_me.bin");
  65
  66 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  67
  68 /* r600,rv610,rv630,rv620,rv635,rv670 */
  69 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  70 void r600_gpu_init(struct radeon_device *rdev);
  71 void r600_fini(struct radeon_device *rdev);
  72
  73 /*
  74  * R600 PCIE GART
  75  */
  76 int r600_gart_clear_page(struct radeon_device *rdev, int i)
  77 {
  78         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  79         u64 pte;
  80
  81         if (i < 0 || i > rdev->gart.num_gpu_pages)
  82                 return -EINVAL;
  83         pte = 0;
  84         writeq(pte, ((void __iomem *)ptr) + (i * 8));
  85         return 0;
  86 }
  87
  88 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
  89 {
  90         unsigned i;
  91         u32 tmp;
  92
  93         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
  94         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
  95         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
  96         for (i = 0; i < rdev->usec_timeout; i++) {
  97                 /* read MC_STATUS */
  98                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
  99                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 100                 if (tmp == 2) {
 101                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 102                         return;
 103                 }
 104                 if (tmp) {
 105                         return;
 106                 }
 107                 udelay(1);
 108         }
 109 }
 110
 111 int r600_pcie_gart_init(struct radeon_device *rdev)
 112 {
 113         int r;
 114
 115         if (rdev->gart.table.vram.robj) {
 116                 WARN(1, "R600 PCIE GART already initialized.\n");
 117                 return 0;
 118         }
 119         /* Initialize common gart structure */
 120         r = radeon_gart_init(rdev);
 121         if (r)
 122                 return r;
 123         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 124         return radeon_gart_table_vram_alloc(rdev);
 125 }
 126
 127 int r600_pcie_gart_enable(struct radeon_device *rdev)
 128 {
 129         u32 tmp;
 130         int r, i;
 131
 132         if (rdev->gart.table.vram.robj == NULL) {
 133                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 134                 return -EINVAL;
 135         }
 136         r = radeon_gart_table_vram_pin(rdev);
 137         if (r)
 138                 return r;
 139
 140         /* Setup L2 cache */
 141         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 142                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 143                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 144         WREG32(VM_L2_CNTL2, 0);
 145         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 146         /* Setup TLB control */
 147         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 148                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 149                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 150                 ENABLE_WAIT_L2_QUERY;
 151         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 152         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 153         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 154         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 155         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 156         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 157         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 158         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 159         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 160         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 161         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 162         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 163         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 164         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 165         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 166         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 167         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 168         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 169                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 170         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 171                         (u32)(rdev->dummy_page.addr >> 12));
 172         for (i = 1; i < 7; i++)
 173                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 174
 175         r600_pcie_gart_tlb_flush(rdev);
 176         rdev->gart.ready = true;
 177         return 0;
 178 }
 179
 180 void r600_pcie_gart_disable(struct radeon_device *rdev)
 181 {
 182         u32 tmp;
 183         int i;
 184
 185         /* Disable all tables */
 186         for (i = 0; i < 7; i++)
 187                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 188
 189         /* Disable L2 cache */
 190         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 191                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 192         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 193         /* Setup L1 TLB control */
 194         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 195                 ENABLE_WAIT_L2_QUERY;
 196         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 197         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 198         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 199         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 200         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 201         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 202         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 203         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 204         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 205         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 206         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 207         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 208         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 209         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 210         if (rdev->gart.table.vram.robj) {
 211                 radeon_object_kunmap(rdev->gart.table.vram.robj);
 212                 radeon_object_unpin(rdev->gart.table.vram.robj);
 213         }
 214 }
 215
 216 void r600_pcie_gart_fini(struct radeon_device *rdev)
 217 {
 218         r600_pcie_gart_disable(rdev);
 219         radeon_gart_table_vram_free(rdev);
 220         radeon_gart_fini(rdev);
 221 }
 222
 223 void r600_agp_enable(struct radeon_device *rdev)
 224 {
 225         u32 tmp;
 226         int i;
 227
 228         /* Setup L2 cache */
 229         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 230                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 231                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 232         WREG32(VM_L2_CNTL2, 0);
 233         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 234         /* Setup TLB control */
 235         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 236                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 237                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 238                 ENABLE_WAIT_L2_QUERY;
 239         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 240         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 241         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 242         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 243         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 244         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 245         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 246         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 247         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 248         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 249         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 250         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 251         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 252         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 253         for (i = 0; i < 7; i++)
 254                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 255 }
 256
 257 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 258 {
 259         unsigned i;
 260         u32 tmp;
 261
 262         for (i = 0; i < rdev->usec_timeout; i++) {
 263                 /* read MC_STATUS */
 264                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 265                 if (!tmp)
 266                         return 0;
 267                 udelay(1);
 268         }
 269         return -1;
 270 }
 271
 272 static void r600_mc_program(struct radeon_device *rdev)
 273 {
 274         struct rv515_mc_save save;
 275         u32 tmp;
 276         int i, j;
 277
 278         /* Initialize HDP */
 279         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 280                 WREG32((0x2c14 + j), 0x00000000);
 281                 WREG32((0x2c18 + j), 0x00000000);
 282                 WREG32((0x2c1c + j), 0x00000000);
 283                 WREG32((0x2c20 + j), 0x00000000);
 284                 WREG32((0x2c24 + j), 0x00000000);
 285         }
 286         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 287
 288         rv515_mc_stop(rdev, &save);
 289         if (r600_mc_wait_for_idle(rdev)) {
 290                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 291         }
 292         /* Lockout access through VGA aperture (doesn't exist before R600) */
 293         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 294         /* Update configuration */
 295         if (rdev->flags & RADEON_IS_AGP) {
 296                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 297                         /* VRAM before AGP */
 298                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 299                                 rdev->mc.vram_start >> 12);
 300                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 301                                 rdev->mc.gtt_end >> 12);
 302                 } else {
 303                         /* VRAM after AGP */
 304                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 305                                 rdev->mc.gtt_start >> 12);
 306                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 307                                 rdev->mc.vram_end >> 12);
 308                 }
 309         } else {
 310                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 311                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 312         }
 313         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 314         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 315         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 316         WREG32(MC_VM_FB_LOCATION, tmp);
 317         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 318         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 319         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 320         if (rdev->flags & RADEON_IS_AGP) {
 321                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 322                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 323                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 324         } else {
 325                 WREG32(MC_VM_AGP_BASE, 0);
 326                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 327                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 328         }
 329         if (r600_mc_wait_for_idle(rdev)) {
 330                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 331         }
 332         rv515_mc_resume(rdev, &save);
 333         /* we need to own VRAM, so turn off the VGA renderer here
 334          * to stop it overwriting our objects */
 335         rv515_vga_render_disable(rdev);
 336 }
 337
 338 int r600_mc_init(struct radeon_device *rdev)
 339 {
 340         fixed20_12 a;
 341         u32 tmp;
 342         int chansize, numchan;
 343         int r;
 344
 345         /* Get VRAM informations */
 346         rdev->mc.vram_is_ddr = true;
 347         tmp = RREG32(RAMCFG);
 348         if (tmp & CHANSIZE_OVERRIDE) {
 349                 chansize = 16;
 350         } else if (tmp & CHANSIZE_MASK) {
 351                 chansize = 64;
 352         } else {
 353                 chansize = 32;
 354         }
 355         tmp = RREG32(CHMAP);
 356         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 357         case 0:
 358         default:
 359                 numchan = 1;
 360                 break;
 361         case 1:
 362                 numchan = 2;
 363                 break;
 364         case 2:
 365                 numchan = 4;
 366                 break;
 367         case 3:
 368                 numchan = 8;
 369                 break;
 370         }
 371         rdev->mc.vram_width = numchan * chansize;
 372         /* Could aper size report 0 ? */
 373         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 374         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 375         /* Setup GPU memory space */
 376         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 377         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 378
 379         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 380                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 381
 382         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 383                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 384
 385         if (rdev->flags & RADEON_IS_AGP) {
 386                 r = radeon_agp_init(rdev);
 387                 if (r)
 388                         return r;
 389                 /* gtt_size is setup by radeon_agp_init */
 390                 rdev->mc.gtt_location = rdev->mc.agp_base;
 391                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 392                 /* Try to put vram before or after AGP because we
 393                  * we want SYSTEM_APERTURE to cover both VRAM and
 394                  * AGP so that GPU can catch out of VRAM/AGP access
 395                  */
 396                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 397                         /* Enought place before */
 398                         rdev->mc.vram_location = rdev->mc.gtt_location -
 399                                                         rdev->mc.mc_vram_size;
 400                 } else if (tmp > rdev->mc.mc_vram_size) {
 401                         /* Enought place after */
 402                         rdev->mc.vram_location = rdev->mc.gtt_location +
 403                                                         rdev->mc.gtt_size;
 404                 } else {
 405                         /* Try to setup VRAM then AGP might not
 406                          * not work on some card
 407                          */
 408                         rdev->mc.vram_location = 0x00000000UL;
 409                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 410                 }
 411         } else {
 412                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 413                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 414                                                         0xFFFF) << 24;
 415                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 416                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 417                         /* Enough place after vram */
 418                         rdev->mc.gtt_location = tmp;
 419                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 420                         /* Enough place before vram */
 421                         rdev->mc.gtt_location = 0;
 422                 } else {
 423                         /* Not enough place after or before shrink
 424                          * gart size
 425                          */
 426                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 427                                 rdev->mc.gtt_location = 0;
 428                                 rdev->mc.gtt_size = rdev->mc.vram_location;
 429                         } else {
 430                                 rdev->mc.gtt_location = tmp;
 431                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 432                         }
 433                 }
 434                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 435         }
 436         rdev->mc.vram_start = rdev->mc.vram_location;
 437         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 438         rdev->mc.gtt_start = rdev->mc.gtt_location;
 439         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 440         /* FIXME: we should enforce default clock in case GPU is not in
 441          * default setup
 442          */
 443         a.full = rfixed_const(100);
 444         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 445         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 446         return 0;
 447 }
 448
 449 /* We doesn't check that the GPU really needs a reset we simply do the
 450  * reset, it's up to the caller to determine if the GPU needs one. We
 451  * might add an helper function to check that.
 452  */
 453 int r600_gpu_soft_reset(struct radeon_device *rdev)
 454 {
 455         struct rv515_mc_save save;
 456         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 457                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 458                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 459                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 460                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 461                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 462                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 463                                 S_008010_GUI_ACTIVE(1);
 464         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 465                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 466                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 467                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 468                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 469                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 470                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 471                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 472         u32 srbm_reset = 0;
 473         u32 tmp;
 474
 475         dev_info(rdev->dev, "GPU softreset \n");
 476         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 477                 RREG32(R_008010_GRBM_STATUS));
 478         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 479                 RREG32(R_008014_GRBM_STATUS2));
 480         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 481                 RREG32(R_000E50_SRBM_STATUS));
 482         rv515_mc_stop(rdev, &save);
 483         if (r600_mc_wait_for_idle(rdev)) {
 484                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 485         }
 486         /* Disable CP parsing/prefetching */
 487         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 488         /* Check if any of the rendering block is busy and reset it */
 489         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 490             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 491                 tmp = S_008020_SOFT_RESET_CR(1) |
 492                         S_008020_SOFT_RESET_DB(1) |
 493                         S_008020_SOFT_RESET_CB(1) |
 494                         S_008020_SOFT_RESET_PA(1) |
 495                         S_008020_SOFT_RESET_SC(1) |
 496                         S_008020_SOFT_RESET_SMX(1) |
 497                         S_008020_SOFT_RESET_SPI(1) |
 498                         S_008020_SOFT_RESET_SX(1) |
 499                         S_008020_SOFT_RESET_SH(1) |
 500                         S_008020_SOFT_RESET_TC(1) |
 501                         S_008020_SOFT_RESET_TA(1) |
 502                         S_008020_SOFT_RESET_VC(1) |
 503                         S_008020_SOFT_RESET_VGT(1);
 504                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 505                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 506                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 507                 udelay(50);
 508                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 509                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 510         }
 511         /* Reset CP (we always reset CP) */
 512         tmp = S_008020_SOFT_RESET_CP(1);
 513         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 514         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 515         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 516         udelay(50);
 517         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 518         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 519         /* Reset others GPU block if necessary */
 520         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 521                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 522         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 523                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 524         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 525                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 526         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 527                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 528         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 529                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 530         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 531                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 532         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 533                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 534         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 535                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 536         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 537                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 538         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 539                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 540         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 541                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 542         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 543                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 544         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 545         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 546         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 547         udelay(50);
 548         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 549         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 550         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 551         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 552         udelay(50);
 553         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 554         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 555         /* Wait a little for things to settle down */
 556         udelay(50);
 557         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 558                 RREG32(R_008010_GRBM_STATUS));
 559         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 560                 RREG32(R_008014_GRBM_STATUS2));
 561         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 562                 RREG32(R_000E50_SRBM_STATUS));
 563         /* After reset we need to reinit the asic as GPU often endup in an
 564          * incoherent state.
 565          */
 566         atom_asic_init(rdev->mode_info.atom_context);
 567         rv515_mc_resume(rdev, &save);
 568         return 0;
 569 }
 570
 571 int r600_gpu_reset(struct radeon_device *rdev)
 572 {
 573         return r600_gpu_soft_reset(rdev);
 574 }
 575
 576 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 577                                              u32 num_backends,
 578                                              u32 backend_disable_mask)
 579 {
 580         u32 backend_map = 0;
 581         u32 enabled_backends_mask;
 582         u32 enabled_backends_count;
 583         u32 cur_pipe;
 584         u32 swizzle_pipe[R6XX_MAX_PIPES];
 585         u32 cur_backend;
 586         u32 i;
 587
 588         if (num_tile_pipes > R6XX_MAX_PIPES)
 589                 num_tile_pipes = R6XX_MAX_PIPES;
 590         if (num_tile_pipes < 1)
 591                 num_tile_pipes = 1;
 592         if (num_backends > R6XX_MAX_BACKENDS)
 593                 num_backends = R6XX_MAX_BACKENDS;
 594         if (num_backends < 1)
 595                 num_backends = 1;
 596
 597         enabled_backends_mask = 0;
 598         enabled_backends_count = 0;
 599         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 600                 if (((backend_disable_mask >> i) & 1) == 0) {
 601                         enabled_backends_mask |= (1 << i);
 602                         ++enabled_backends_count;
 603                 }
 604                 if (enabled_backends_count == num_backends)
 605                         break;
 606         }
 607
 608         if (enabled_backends_count == 0) {
 609                 enabled_backends_mask = 1;
 610                 enabled_backends_count = 1;
 611         }
 612
 613         if (enabled_backends_count != num_backends)
 614                 num_backends = enabled_backends_count;
 615
 616         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 617         switch (num_tile_pipes) {
 618         case 1:
 619                 swizzle_pipe[0] = 0;
 620                 break;
 621         case 2:
 622                 swizzle_pipe[0] = 0;
 623                 swizzle_pipe[1] = 1;
 624                 break;
 625         case 3:
 626                 swizzle_pipe[0] = 0;
 627                 swizzle_pipe[1] = 1;
 628                 swizzle_pipe[2] = 2;
 629                 break;
 630         case 4:
 631                 swizzle_pipe[0] = 0;
 632                 swizzle_pipe[1] = 1;
 633                 swizzle_pipe[2] = 2;
 634                 swizzle_pipe[3] = 3;
 635                 break;
 636         case 5:
 637                 swizzle_pipe[0] = 0;
 638                 swizzle_pipe[1] = 1;
 639                 swizzle_pipe[2] = 2;
 640                 swizzle_pipe[3] = 3;
 641                 swizzle_pipe[4] = 4;
 642                 break;
 643         case 6:
 644                 swizzle_pipe[0] = 0;
 645                 swizzle_pipe[1] = 2;
 646                 swizzle_pipe[2] = 4;
 647                 swizzle_pipe[3] = 5;
 648                 swizzle_pipe[4] = 1;
 649                 swizzle_pipe[5] = 3;
 650                 break;
 651         case 7:
 652                 swizzle_pipe[0] = 0;
 653                 swizzle_pipe[1] = 2;
 654                 swizzle_pipe[2] = 4;
 655                 swizzle_pipe[3] = 6;
 656                 swizzle_pipe[4] = 1;
 657                 swizzle_pipe[5] = 3;
 658                 swizzle_pipe[6] = 5;
 659                 break;
 660         case 8:
 661                 swizzle_pipe[0] = 0;
 662                 swizzle_pipe[1] = 2;
 663                 swizzle_pipe[2] = 4;
 664                 swizzle_pipe[3] = 6;
 665                 swizzle_pipe[4] = 1;
 666                 swizzle_pipe[5] = 3;
 667                 swizzle_pipe[6] = 5;
 668                 swizzle_pipe[7] = 7;
 669                 break;
 670         }
 671
 672         cur_backend = 0;
 673         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 674                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 675                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 676
 677                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 678
 679                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 680         }
 681
 682         return backend_map;
 683 }
 684
 685 int r600_count_pipe_bits(uint32_t val)
 686 {
 687         int i, ret = 0;
 688
 689         for (i = 0; i < 32; i++) {
 690                 ret += val & 1;
 691                 val >>= 1;
 692         }
 693         return ret;
 694 }
 695
 696 void r600_gpu_init(struct radeon_device *rdev)
 697 {
 698         u32 tiling_config;
 699         u32 ramcfg;
 700         u32 tmp;
 701         int i, j;
 702         u32 sq_config;
 703         u32 sq_gpr_resource_mgmt_1 = 0;
 704         u32 sq_gpr_resource_mgmt_2 = 0;
 705         u32 sq_thread_resource_mgmt = 0;
 706         u32 sq_stack_resource_mgmt_1 = 0;
 707         u32 sq_stack_resource_mgmt_2 = 0;
 708
 709         /* FIXME: implement */
 710         switch (rdev->family) {
 711         case CHIP_R600:
 712                 rdev->config.r600.max_pipes = 4;
 713                 rdev->config.r600.max_tile_pipes = 8;
 714                 rdev->config.r600.max_simds = 4;
 715                 rdev->config.r600.max_backends = 4;
 716                 rdev->config.r600.max_gprs = 256;
 717                 rdev->config.r600.max_threads = 192;
 718                 rdev->config.r600.max_stack_entries = 256;
 719                 rdev->config.r600.max_hw_contexts = 8;
 720                 rdev->config.r600.max_gs_threads = 16;
 721                 rdev->config.r600.sx_max_export_size = 128;
 722                 rdev->config.r600.sx_max_export_pos_size = 16;
 723                 rdev->config.r600.sx_max_export_smx_size = 128;
 724                 rdev->config.r600.sq_num_cf_insts = 2;
 725                 break;
 726         case CHIP_RV630:
 727         case CHIP_RV635:
 728                 rdev->config.r600.max_pipes = 2;
 729                 rdev->config.r600.max_tile_pipes = 2;
 730                 rdev->config.r600.max_simds = 3;
 731                 rdev->config.r600.max_backends = 1;
 732                 rdev->config.r600.max_gprs = 128;
 733                 rdev->config.r600.max_threads = 192;
 734                 rdev->config.r600.max_stack_entries = 128;
 735                 rdev->config.r600.max_hw_contexts = 8;
 736                 rdev->config.r600.max_gs_threads = 4;
 737                 rdev->config.r600.sx_max_export_size = 128;
 738                 rdev->config.r600.sx_max_export_pos_size = 16;
 739                 rdev->config.r600.sx_max_export_smx_size = 128;
 740                 rdev->config.r600.sq_num_cf_insts = 2;
 741                 break;
 742         case CHIP_RV610:
 743         case CHIP_RV620:
 744         case CHIP_RS780:
 745         case CHIP_RS880:
 746                 rdev->config.r600.max_pipes = 1;
 747                 rdev->config.r600.max_tile_pipes = 1;
 748                 rdev->config.r600.max_simds = 2;
 749                 rdev->config.r600.max_backends = 1;
 750                 rdev->config.r600.max_gprs = 128;
 751                 rdev->config.r600.max_threads = 192;
 752                 rdev->config.r600.max_stack_entries = 128;
 753                 rdev->config.r600.max_hw_contexts = 4;
 754                 rdev->config.r600.max_gs_threads = 4;
 755                 rdev->config.r600.sx_max_export_size = 128;
 756                 rdev->config.r600.sx_max_export_pos_size = 16;
 757                 rdev->config.r600.sx_max_export_smx_size = 128;
 758                 rdev->config.r600.sq_num_cf_insts = 1;
 759                 break;
 760         case CHIP_RV670:
 761                 rdev->config.r600.max_pipes = 4;
 762                 rdev->config.r600.max_tile_pipes = 4;
 763                 rdev->config.r600.max_simds = 4;
 764                 rdev->config.r600.max_backends = 4;
 765                 rdev->config.r600.max_gprs = 192;
 766                 rdev->config.r600.max_threads = 192;
 767                 rdev->config.r600.max_stack_entries = 256;
 768                 rdev->config.r600.max_hw_contexts = 8;
 769                 rdev->config.r600.max_gs_threads = 16;
 770                 rdev->config.r600.sx_max_export_size = 128;
 771                 rdev->config.r600.sx_max_export_pos_size = 16;
 772                 rdev->config.r600.sx_max_export_smx_size = 128;
 773                 rdev->config.r600.sq_num_cf_insts = 2;
 774                 break;
 775         default:
 776                 break;
 777         }
 778
 779         /* Initialize HDP */
 780         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 781                 WREG32((0x2c14 + j), 0x00000000);
 782                 WREG32((0x2c18 + j), 0x00000000);
 783                 WREG32((0x2c1c + j), 0x00000000);
 784                 WREG32((0x2c20 + j), 0x00000000);
 785                 WREG32((0x2c24 + j), 0x00000000);
 786         }
 787
 788         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 789
 790         /* Setup tiling */
 791         tiling_config = 0;
 792         ramcfg = RREG32(RAMCFG);
 793         switch (rdev->config.r600.max_tile_pipes) {
 794         case 1:
 795                 tiling_config |= PIPE_TILING(0);
 796                 break;
 797         case 2:
 798                 tiling_config |= PIPE_TILING(1);
 799                 break;
 800         case 4:
 801                 tiling_config |= PIPE_TILING(2);
 802                 break;
 803         case 8:
 804                 tiling_config |= PIPE_TILING(3);
 805                 break;
 806         default:
 807                 break;
 808         }
 809         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 810         tiling_config |= GROUP_SIZE(0);
 811         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 812         if (tmp > 3) {
 813                 tiling_config |= ROW_TILING(3);
 814                 tiling_config |= SAMPLE_SPLIT(3);
 815         } else {
 816                 tiling_config |= ROW_TILING(tmp);
 817                 tiling_config |= SAMPLE_SPLIT(tmp);
 818         }
 819         tiling_config |= BANK_SWAPS(1);
 820         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
 821                                                 rdev->config.r600.max_backends,
 822                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
 823         tiling_config |= BACKEND_MAP(tmp);
 824         WREG32(GB_TILING_CONFIG, tiling_config);
 825         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
 826         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 827
 828         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
 829         WREG32(CC_RB_BACKEND_DISABLE, tmp);
 830
 831         /* Setup pipes */
 832         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
 833         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
 834         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
 835         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
 836
 837         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
 838         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
 839         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 840
 841         /* Setup some CP states */
 842         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
 843         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
 844
 845         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
 846                              SYNC_WALKER | SYNC_ALIGNER));
 847         /* Setup various GPU states */
 848         if (rdev->family == CHIP_RV670)
 849                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
 850
 851         tmp = RREG32(SX_DEBUG_1);
 852         tmp |= SMX_EVENT_RELEASE;
 853         if ((rdev->family > CHIP_R600))
 854                 tmp |= ENABLE_NEW_SMX_ADDRESS;
 855         WREG32(SX_DEBUG_1, tmp);
 856
 857         if (((rdev->family) == CHIP_R600) ||
 858             ((rdev->family) == CHIP_RV630) ||
 859             ((rdev->family) == CHIP_RV610) ||
 860             ((rdev->family) == CHIP_RV620) ||
 861             ((rdev->family) == CHIP_RS780) ||
 862             ((rdev->family) == CHIP_RS880)) {
 863                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 864         } else {
 865                 WREG32(DB_DEBUG, 0);
 866         }
 867         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
 868                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
 869
 870         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 871         WREG32(VGT_NUM_INSTANCES, 0);
 872
 873         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 874         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 875
 876         tmp = RREG32(SQ_MS_FIFO_SIZES);
 877         if (((rdev->family) == CHIP_RV610) ||
 878             ((rdev->family) == CHIP_RV620) ||
 879             ((rdev->family) == CHIP_RS780) ||
 880             ((rdev->family) == CHIP_RS880)) {
 881                 tmp = (CACHE_FIFO_SIZE(0xa) |
 882                        FETCH_FIFO_HIWATER(0xa) |
 883                        DONE_FIFO_HIWATER(0xe0) |
 884                        ALU_UPDATE_FIFO_HIWATER(0x8));
 885         } else if (((rdev->family) == CHIP_R600) ||
 886                    ((rdev->family) == CHIP_RV630)) {
 887                 tmp &= ~DONE_FIFO_HIWATER(0xff);
 888                 tmp |= DONE_FIFO_HIWATER(0x4);
 889         }
 890         WREG32(SQ_MS_FIFO_SIZES, tmp);
 891
 892         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 893          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 894          */
 895         sq_config = RREG32(SQ_CONFIG);
 896         sq_config &= ~(PS_PRIO(3) |
 897                        VS_PRIO(3) |
 898                        GS_PRIO(3) |
 899                        ES_PRIO(3));
 900         sq_config |= (DX9_CONSTS |
 901                       VC_ENABLE |
 902                       PS_PRIO(0) |
 903                       VS_PRIO(1) |
 904                       GS_PRIO(2) |
 905                       ES_PRIO(3));
 906
 907         if ((rdev->family) == CHIP_R600) {
 908                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
 909                                           NUM_VS_GPRS(124) |
 910                                           NUM_CLAUSE_TEMP_GPRS(4));
 911                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
 912                                           NUM_ES_GPRS(0));
 913                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
 914                                            NUM_VS_THREADS(48) |
 915                                            NUM_GS_THREADS(4) |
 916                                            NUM_ES_THREADS(4));
 917                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
 918                                             NUM_VS_STACK_ENTRIES(128));
 919                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
 920                                             NUM_ES_STACK_ENTRIES(0));
 921         } else if (((rdev->family) == CHIP_RV610) ||
 922                    ((rdev->family) == CHIP_RV620) ||
 923                    ((rdev->family) == CHIP_RS780) ||
 924                    ((rdev->family) == CHIP_RS880)) {
 925                 /* no vertex cache */
 926                 sq_config &= ~VC_ENABLE;
 927
 928                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 929                                           NUM_VS_GPRS(44) |
 930                                           NUM_CLAUSE_TEMP_GPRS(2));
 931                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 932                                           NUM_ES_GPRS(17));
 933                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 934                                            NUM_VS_THREADS(78) |
 935                                            NUM_GS_THREADS(4) |
 936                                            NUM_ES_THREADS(31));
 937                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 938                                             NUM_VS_STACK_ENTRIES(40));
 939                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 940                                             NUM_ES_STACK_ENTRIES(16));
 941         } else if (((rdev->family) == CHIP_RV630) ||
 942                    ((rdev->family) == CHIP_RV635)) {
 943                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 944                                           NUM_VS_GPRS(44) |
 945                                           NUM_CLAUSE_TEMP_GPRS(2));
 946                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
 947                                           NUM_ES_GPRS(18));
 948                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 949                                            NUM_VS_THREADS(78) |
 950                                            NUM_GS_THREADS(4) |
 951                                            NUM_ES_THREADS(31));
 952                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 953                                             NUM_VS_STACK_ENTRIES(40));
 954                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 955                                             NUM_ES_STACK_ENTRIES(16));
 956         } else if ((rdev->family) == CHIP_RV670) {
 957                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 958                                           NUM_VS_GPRS(44) |
 959                                           NUM_CLAUSE_TEMP_GPRS(2));
 960                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 961                                           NUM_ES_GPRS(17));
 962                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 963                                            NUM_VS_THREADS(78) |
 964                                            NUM_GS_THREADS(4) |
 965                                            NUM_ES_THREADS(31));
 966                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
 967                                             NUM_VS_STACK_ENTRIES(64));
 968                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
 969                                             NUM_ES_STACK_ENTRIES(64));
 970         }
 971
 972         WREG32(SQ_CONFIG, sq_config);
 973         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 974         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 975         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 976         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 977         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 978
 979         if (((rdev->family) == CHIP_RV610) ||
 980             ((rdev->family) == CHIP_RV620) ||
 981             ((rdev->family) == CHIP_RS780) ||
 982             ((rdev->family) == CHIP_RS880)) {
 983                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
 984         } else {
 985                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
 986         }
 987
 988         /* More default values. 2D/3D driver should adjust as needed */
 989         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
 990                                          S1_X(0x4) | S1_Y(0xc)));
 991         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
 992                                          S1_X(0x2) | S1_Y(0x2) |
 993                                          S2_X(0xa) | S2_Y(0x6) |
 994                                          S3_X(0x6) | S3_Y(0xa)));
 995         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
 996                                              S1_X(0x4) | S1_Y(0xc) |
 997                                              S2_X(0x1) | S2_Y(0x6) |
 998                                              S3_X(0xa) | S3_Y(0xe)));
 999         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1000                                              S5_X(0x0) | S5_Y(0x0) |
1001                                              S6_X(0xb) | S6_Y(0x4) |
1002                                              S7_X(0x7) | S7_Y(0x8)));
1003
1004         WREG32(VGT_STRMOUT_EN, 0);
1005         tmp = rdev->config.r600.max_pipes * 16;
1006         switch (rdev->family) {
1007         case CHIP_RV610:
1008         case CHIP_RV620:
1009         case CHIP_RS780:
1010         case CHIP_RS880:
1011                 tmp += 32;
1012                 break;
1013         case CHIP_RV670:
1014                 tmp += 128;
1015                 break;
1016         default:
1017                 break;
1018         }
1019         if (tmp > 256) {
1020                 tmp = 256;
1021         }
1022         WREG32(VGT_ES_PER_GS, 128);
1023         WREG32(VGT_GS_PER_ES, tmp);
1024         WREG32(VGT_GS_PER_VS, 2);
1025         WREG32(VGT_GS_VERTEX_REUSE, 16);
1026
1027         /* more default values. 2D/3D driver should adjust as needed */
1028         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1029         WREG32(VGT_STRMOUT_EN, 0);
1030         WREG32(SX_MISC, 0);
1031         WREG32(PA_SC_MODE_CNTL, 0);
1032         WREG32(PA_SC_AA_CONFIG, 0);
1033         WREG32(PA_SC_LINE_STIPPLE, 0);
1034         WREG32(SPI_INPUT_Z, 0);
1035         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1036         WREG32(CB_COLOR7_FRAG, 0);
1037
1038         /* Clear render buffer base addresses */
1039         WREG32(CB_COLOR0_BASE, 0);
1040         WREG32(CB_COLOR1_BASE, 0);
1041         WREG32(CB_COLOR2_BASE, 0);
1042         WREG32(CB_COLOR3_BASE, 0);
1043         WREG32(CB_COLOR4_BASE, 0);
1044         WREG32(CB_COLOR5_BASE, 0);
1045         WREG32(CB_COLOR6_BASE, 0);
1046         WREG32(CB_COLOR7_BASE, 0);
1047         WREG32(CB_COLOR7_FRAG, 0);
1048
1049         switch (rdev->family) {
1050         case CHIP_RV610:
1051         case CHIP_RV620:
1052         case CHIP_RS780:
1053         case CHIP_RS880:
1054                 tmp = TC_L2_SIZE(8);
1055                 break;
1056         case CHIP_RV630:
1057         case CHIP_RV635:
1058                 tmp = TC_L2_SIZE(4);
1059                 break;
1060         case CHIP_R600:
1061                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1062                 break;
1063         default:
1064                 tmp = TC_L2_SIZE(0);
1065                 break;
1066         }
1067         WREG32(TC_CNTL, tmp);
1068
1069         tmp = RREG32(HDP_HOST_PATH_CNTL);
1070         WREG32(HDP_HOST_PATH_CNTL, tmp);
1071
1072         tmp = RREG32(ARB_POP);
1073         tmp |= ENABLE_TC128;
1074         WREG32(ARB_POP, tmp);
1075
1076         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1077         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1078                                NUM_CLIP_SEQ(3)));
1079         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1080 }
1081
1082
1083 /*
1084  * Indirect registers accessor
1085  */
1086 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1087 {
1088         u32 r;
1089
1090         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1091         (void)RREG32(PCIE_PORT_INDEX);
1092         r = RREG32(PCIE_PORT_DATA);
1093         return r;
1094 }
1095
1096 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1097 {
1098         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1099         (void)RREG32(PCIE_PORT_INDEX);
1100         WREG32(PCIE_PORT_DATA, (v));
1101         (void)RREG32(PCIE_PORT_DATA);
1102 }
1103
1104
1105 /*
1106  * CP & Ring
1107  */
1108 void r600_cp_stop(struct radeon_device *rdev)
1109 {
1110         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1111 }
1112
1113 int r600_cp_init_microcode(struct radeon_device *rdev)
1114 {
1115         struct platform_device *pdev;
1116         const char *chip_name;
1117         size_t pfp_req_size, me_req_size;
1118         char fw_name[30];
1119         int err;
1120
1121         DRM_DEBUG("\n");
1122
1123         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1124         err = IS_ERR(pdev);
1125         if (err) {
1126                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1127                 return -EINVAL;
1128         }
1129
1130         switch (rdev->family) {
1131         case CHIP_R600: chip_name = "R600"; break;
1132         case CHIP_RV610: chip_name = "RV610"; break;
1133         case CHIP_RV630: chip_name = "RV630"; break;
1134         case CHIP_RV620: chip_name = "RV620"; break;
1135         case CHIP_RV635: chip_name = "RV635"; break;
1136         case CHIP_RV670: chip_name = "RV670"; break;
1137         case CHIP_RS780:
1138         case CHIP_RS880: chip_name = "RS780"; break;
1139         case CHIP_RV770: chip_name = "RV770"; break;
1140         case CHIP_RV730:
1141         case CHIP_RV740: chip_name = "RV730"; break;
1142         case CHIP_RV710: chip_name = "RV710"; break;
1143         default: BUG();
1144         }
1145
1146         if (rdev->family >= CHIP_RV770) {
1147                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1148                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1149         } else {
1150                 pfp_req_size = PFP_UCODE_SIZE * 4;
1151                 me_req_size = PM4_UCODE_SIZE * 12;
1152         }
1153
1154         DRM_INFO("Loading %s CP Microcode\n", chip_name);
1155
1156         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1157         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1158         if (err)
1159                 goto out;
1160         if (rdev->pfp_fw->size != pfp_req_size) {
1161                 printk(KERN_ERR
1162                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1163                        rdev->pfp_fw->size, fw_name);
1164                 err = -EINVAL;
1165                 goto out;
1166         }
1167
1168         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1169         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1170         if (err)
1171                 goto out;
1172         if (rdev->me_fw->size != me_req_size) {
1173                 printk(KERN_ERR
1174                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1175                        rdev->me_fw->size, fw_name);
1176                 err = -EINVAL;
1177         }
1178 out:
1179         platform_device_unregister(pdev);
1180
1181         if (err) {
1182                 if (err != -EINVAL)
1183                         printk(KERN_ERR
1184                                "r600_cp: Failed to load firmware \"%s\"\n",
1185                                fw_name);
1186                 release_firmware(rdev->pfp_fw);
1187                 rdev->pfp_fw = NULL;
1188                 release_firmware(rdev->me_fw);
1189                 rdev->me_fw = NULL;
1190         }
1191         return err;
1192 }
1193
1194 static int r600_cp_load_microcode(struct radeon_device *rdev)
1195 {
1196         const __be32 *fw_data;
1197         int i;
1198
1199         if (!rdev->me_fw || !rdev->pfp_fw)
1200                 return -EINVAL;
1201
1202         r600_cp_stop(rdev);
1203
1204         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1205
1206         /* Reset cp */
1207         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1208         RREG32(GRBM_SOFT_RESET);
1209         mdelay(15);
1210         WREG32(GRBM_SOFT_RESET, 0);
1211
1212         WREG32(CP_ME_RAM_WADDR, 0);
1213
1214         fw_data = (const __be32 *)rdev->me_fw->data;
1215         WREG32(CP_ME_RAM_WADDR, 0);
1216         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1217                 WREG32(CP_ME_RAM_DATA,
1218                        be32_to_cpup(fw_data++));
1219
1220         fw_data = (const __be32 *)rdev->pfp_fw->data;
1221         WREG32(CP_PFP_UCODE_ADDR, 0);
1222         for (i = 0; i < PFP_UCODE_SIZE; i++)
1223                 WREG32(CP_PFP_UCODE_DATA,
1224                        be32_to_cpup(fw_data++));
1225
1226         WREG32(CP_PFP_UCODE_ADDR, 0);
1227         WREG32(CP_ME_RAM_WADDR, 0);
1228         WREG32(CP_ME_RAM_RADDR, 0);
1229         return 0;
1230 }
1231
1232 int r600_cp_start(struct radeon_device *rdev)
1233 {
1234         int r;
1235         uint32_t cp_me;
1236
1237         r = radeon_ring_lock(rdev, 7);
1238         if (r) {
1239                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1240                 return r;
1241         }
1242         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1243         radeon_ring_write(rdev, 0x1);
1244         if (rdev->family < CHIP_RV770) {
1245                 radeon_ring_write(rdev, 0x3);
1246                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1247         } else {
1248                 radeon_ring_write(rdev, 0x0);
1249                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1250         }
1251         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1252         radeon_ring_write(rdev, 0);
1253         radeon_ring_write(rdev, 0);
1254         radeon_ring_unlock_commit(rdev);
1255
1256         cp_me = 0xff;
1257         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1258         return 0;
1259 }
1260
1261 int r600_cp_resume(struct radeon_device *rdev)
1262 {
1263         u32 tmp;
1264         u32 rb_bufsz;
1265         int r;
1266
1267         /* Reset cp */
1268         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1269         RREG32(GRBM_SOFT_RESET);
1270         mdelay(15);
1271         WREG32(GRBM_SOFT_RESET, 0);
1272
1273         /* Set ring buffer size */
1274         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1275         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1276 #ifdef __BIG_ENDIAN
1277         tmp |= BUF_SWAP_32BIT;
1278 #endif
1279         WREG32(CP_RB_CNTL, tmp);
1280         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1281
1282         /* Set the write pointer delay */
1283         WREG32(CP_RB_WPTR_DELAY, 0);
1284
1285         /* Initialize the ring buffer's read and write pointers */
1286         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1287         WREG32(CP_RB_RPTR_WR, 0);
1288         WREG32(CP_RB_WPTR, 0);
1289         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1290         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1291         mdelay(1);
1292         WREG32(CP_RB_CNTL, tmp);
1293
1294         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1295         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1296
1297         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1298         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1299
1300         r600_cp_start(rdev);
1301         rdev->cp.ready = true;
1302         r = radeon_ring_test(rdev);
1303         if (r) {
1304                 rdev->cp.ready = false;
1305                 return r;
1306         }
1307         return 0;
1308 }
1309
1310 void r600_cp_commit(struct radeon_device *rdev)
1311 {
1312         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1313         (void)RREG32(CP_RB_WPTR);
1314 }
1315
1316 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1317 {
1318         u32 rb_bufsz;
1319
1320         /* Align ring size */
1321         rb_bufsz = drm_order(ring_size / 8);
1322         ring_size = (1 << (rb_bufsz + 1)) * 4;
1323         rdev->cp.ring_size = ring_size;
1324         rdev->cp.align_mask = 16 - 1;
1325 }
1326
1327
1328 /*
1329  * GPU scratch registers helpers function.
1330  */
1331 void r600_scratch_init(struct radeon_device *rdev)
1332 {
1333         int i;
1334
1335         rdev->scratch.num_reg = 7;
1336         for (i = 0; i < rdev->scratch.num_reg; i++) {
1337                 rdev->scratch.free[i] = true;
1338                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1339         }
1340 }
1341
1342 int r600_ring_test(struct radeon_device *rdev)
1343 {
1344         uint32_t scratch;
1345         uint32_t tmp = 0;
1346         unsigned i;
1347         int r;
1348
1349         r = radeon_scratch_get(rdev, &scratch);
1350         if (r) {
1351                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1352                 return r;
1353         }
1354         WREG32(scratch, 0xCAFEDEAD);
1355         r = radeon_ring_lock(rdev, 3);
1356         if (r) {
1357                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1358                 radeon_scratch_free(rdev, scratch);
1359                 return r;
1360         }
1361         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1362         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1363         radeon_ring_write(rdev, 0xDEADBEEF);
1364         radeon_ring_unlock_commit(rdev);
1365         for (i = 0; i < rdev->usec_timeout; i++) {
1366                 tmp = RREG32(scratch);
1367                 if (tmp == 0xDEADBEEF)
1368                         break;
1369                 DRM_UDELAY(1);
1370         }
1371         if (i < rdev->usec_timeout) {
1372                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1373         } else {
1374                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1375                           scratch, tmp);
1376                 r = -EINVAL;
1377         }
1378         radeon_scratch_free(rdev, scratch);
1379         return r;
1380 }
1381
1382 void r600_wb_disable(struct radeon_device *rdev)
1383 {
1384         WREG32(SCRATCH_UMSK, 0);
1385         if (rdev->wb.wb_obj) {
1386                 radeon_object_kunmap(rdev->wb.wb_obj);
1387                 radeon_object_unpin(rdev->wb.wb_obj);
1388         }
1389 }
1390
1391 void r600_wb_fini(struct radeon_device *rdev)
1392 {
1393         r600_wb_disable(rdev);
1394         if (rdev->wb.wb_obj) {
1395                 radeon_object_unref(&rdev->wb.wb_obj);
1396                 rdev->wb.wb = NULL;
1397                 rdev->wb.wb_obj = NULL;
1398         }
1399 }
1400
1401 int r600_wb_enable(struct radeon_device *rdev)
1402 {
1403         int r;
1404
1405         if (rdev->wb.wb_obj == NULL) {
1406                 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1407                                 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
1408                 if (r) {
1409                         dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
1410                         return r;
1411                 }
1412                 r = radeon_object_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1413                                 &rdev->wb.gpu_addr);
1414                 if (r) {
1415                         dev_warn(rdev->dev, "failed to pin WB buffer (%d).\n", r);
1416                         r600_wb_fini(rdev);
1417                         return r;
1418                 }
1419                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1420                 if (r) {
1421                         dev_warn(rdev->dev, "failed to map WB buffer (%d).\n", r);
1422                         r600_wb_fini(rdev);
1423                         return r;
1424                 }
1425         }
1426         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1427         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1428         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1429         WREG32(SCRATCH_UMSK, 0xff);
1430         return 0;
1431 }
1432
1433 void r600_fence_ring_emit(struct radeon_device *rdev,
1434                           struct radeon_fence *fence)
1435 {
1436         /* Emit fence sequence & fire IRQ */
1437         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1438         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1439         radeon_ring_write(rdev, fence->seq);
1440 }
1441
1442 int r600_copy_dma(struct radeon_device *rdev,
1443                   uint64_t src_offset,
1444                   uint64_t dst_offset,
1445                   unsigned num_pages,
1446                   struct radeon_fence *fence)
1447 {
1448         /* FIXME: implement */
1449         return 0;
1450 }
1451
1452 int r600_copy_blit(struct radeon_device *rdev,
1453                    uint64_t src_offset, uint64_t dst_offset,
1454                    unsigned num_pages, struct radeon_fence *fence)
1455 {
1456         r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1457         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1458         r600_blit_done_copy(rdev, fence);
1459         return 0;
1460 }
1461
1462 int r600_irq_process(struct radeon_device *rdev)
1463 {
1464         /* FIXME: implement */
1465         return 0;
1466 }
1467
1468 int r600_irq_set(struct radeon_device *rdev)
1469 {
1470         /* FIXME: implement */
1471         return 0;
1472 }
1473
1474 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1475                          uint32_t tiling_flags, uint32_t pitch,
1476                          uint32_t offset, uint32_t obj_size)
1477 {
1478         /* FIXME: implement */
1479         return 0;
1480 }
1481
1482 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1483 {
1484         /* FIXME: implement */
1485 }
1486
1487
1488 bool r600_card_posted(struct radeon_device *rdev)
1489 {
1490         uint32_t reg;
1491
1492         /* first check CRTCs */
1493         reg = RREG32(D1CRTC_CONTROL) |
1494                 RREG32(D2CRTC_CONTROL);
1495         if (reg & CRTC_EN)
1496                 return true;
1497
1498         /* then check MEM_SIZE, in case the crtcs are off */
1499         if (RREG32(CONFIG_MEMSIZE))
1500                 return true;
1501
1502         return false;
1503 }
1504
1505 int r600_startup(struct radeon_device *rdev)
1506 {
1507         int r;
1508
1509         r600_mc_program(rdev);
1510         if (rdev->flags & RADEON_IS_AGP) {
1511                 r600_agp_enable(rdev);
1512         } else {
1513                 r = r600_pcie_gart_enable(rdev);
1514                 if (r)
1515                         return r;
1516         }
1517         r600_gpu_init(rdev);
1518
1519         r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1520                               &rdev->r600_blit.shader_gpu_addr);
1521         if (r) {
1522                 DRM_ERROR("failed to pin blit object %d\n", r);
1523                 return r;
1524         }
1525
1526         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1527         if (r)
1528                 return r;
1529         r = r600_cp_load_microcode(rdev);
1530         if (r)
1531                 return r;
1532         r = r600_cp_resume(rdev);
1533         if (r)
1534                 return r;
1535         /* write back buffer are not vital so don't worry about failure */
1536         r600_wb_enable(rdev);
1537         return 0;
1538 }
1539
1540 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1541 {
1542         uint32_t temp;
1543
1544         temp = RREG32(CONFIG_CNTL);
1545         if (state == false) {
1546                 temp &= ~(1<<0);
1547                 temp |= (1<<1);
1548         } else {
1549                 temp &= ~(1<<1);
1550         }
1551         WREG32(CONFIG_CNTL, temp);
1552 }
1553
1554 int r600_resume(struct radeon_device *rdev)
1555 {
1556         int r;
1557
1558         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1559          * posting will perform necessary task to bring back GPU into good
1560          * shape.
1561          */
1562         /* post card */
1563         atom_asic_init(rdev->mode_info.atom_context);
1564         /* Initialize clocks */
1565         r = radeon_clocks_init(rdev);
1566         if (r) {
1567                 return r;
1568         }
1569
1570         r = r600_startup(rdev);
1571         if (r) {
1572                 DRM_ERROR("r600 startup failed on resume\n");
1573                 return r;
1574         }
1575
1576         r = r600_ib_test(rdev);
1577         if (r) {
1578                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1579                 return r;
1580         }
1581         return r;
1582 }
1583
1584 int r600_suspend(struct radeon_device *rdev)
1585 {
1586         /* FIXME: we should wait for ring to be empty */
1587         r600_cp_stop(rdev);
1588         rdev->cp.ready = false;
1589         r600_wb_disable(rdev);
1590         r600_pcie_gart_disable(rdev);
1591         /* unpin shaders bo */
1592         radeon_object_unpin(rdev->r600_blit.shader_obj);
1593         return 0;
1594 }
1595
1596 /* Plan is to move initialization in that function and use
1597  * helper function so that radeon_device_init pretty much
1598  * do nothing more than calling asic specific function. This
1599  * should also allow to remove a bunch of callback function
1600  * like vram_info.
1601  */
1602 int r600_init(struct radeon_device *rdev)
1603 {
1604         int r;
1605
1606         r = radeon_dummy_page_init(rdev);
1607         if (r)
1608                 return r;
1609         if (r600_debugfs_mc_info_init(rdev)) {
1610                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1611         }
1612         /* This don't do much */
1613         r = radeon_gem_init(rdev);
1614         if (r)
1615                 return r;
1616         /* Read BIOS */
1617         if (!radeon_get_bios(rdev)) {
1618                 if (ASIC_IS_AVIVO(rdev))
1619                         return -EINVAL;
1620         }
1621         /* Must be an ATOMBIOS */
1622         if (!rdev->is_atom_bios) {
1623                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1624                 return -EINVAL;
1625         }
1626         r = radeon_atombios_init(rdev);
1627         if (r)
1628                 return r;
1629         /* Post card if necessary */
1630         if (!r600_card_posted(rdev) && rdev->bios) {
1631                 DRM_INFO("GPU not posted. posting now...\n");
1632                 atom_asic_init(rdev->mode_info.atom_context);
1633         }
1634         /* Initialize scratch registers */
1635         r600_scratch_init(rdev);
1636         /* Initialize surface registers */
1637         radeon_surface_init(rdev);
1638         /* Initialize clocks */
1639         radeon_get_clock_info(rdev->ddev);
1640         r = radeon_clocks_init(rdev);
1641         if (r)
1642                 return r;
1643         /* Initialize power management */
1644         radeon_pm_init(rdev);
1645         /* Fence driver */
1646         r = radeon_fence_driver_init(rdev);
1647         if (r)
1648                 return r;
1649         r = r600_mc_init(rdev);
1650         if (r)
1651                 return r;
1652         /* Memory manager */
1653         r = radeon_object_init(rdev);
1654         if (r)
1655                 return r;
1656         rdev->cp.ring_obj = NULL;
1657         r600_ring_init(rdev, 1024 * 1024);
1658
1659         if (!rdev->me_fw || !rdev->pfp_fw) {
1660                 r = r600_cp_init_microcode(rdev);
1661                 if (r) {
1662                         DRM_ERROR("Failed to load firmware!\n");
1663                         return r;
1664                 }
1665         }
1666
1667         r = r600_pcie_gart_init(rdev);
1668         if (r)
1669                 return r;
1670
1671         rdev->accel_working = true;
1672         r = r600_blit_init(rdev);
1673         if (r) {
1674                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1675                 return r;
1676         }
1677
1678         r = r600_startup(rdev);
1679         if (r) {
1680                 r600_suspend(rdev);
1681                 r600_wb_fini(rdev);
1682                 radeon_ring_fini(rdev);
1683                 r600_pcie_gart_fini(rdev);
1684                 rdev->accel_working = false;
1685         }
1686         if (rdev->accel_working) {
1687                 r = radeon_ib_pool_init(rdev);
1688                 if (r) {
1689                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1690                         rdev->accel_working = false;
1691                 }
1692                 r = r600_ib_test(rdev);
1693                 if (r) {
1694                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1695                         rdev->accel_working = false;
1696                 }
1697         }
1698         return 0;
1699 }
1700
1701 void r600_fini(struct radeon_device *rdev)
1702 {
1703         /* Suspend operations */
1704         r600_suspend(rdev);
1705
1706         r600_blit_fini(rdev);
1707         radeon_ring_fini(rdev);
1708         r600_wb_fini(rdev);
1709         r600_pcie_gart_fini(rdev);
1710         radeon_gem_fini(rdev);
1711         radeon_fence_driver_fini(rdev);
1712         radeon_clocks_fini(rdev);
1713         if (rdev->flags & RADEON_IS_AGP)
1714                 radeon_agp_fini(rdev);
1715         radeon_object_fini(rdev);
1716         radeon_atombios_fini(rdev);
1717         kfree(rdev->bios);
1718         rdev->bios = NULL;
1719         radeon_dummy_page_fini(rdev);
1720 }
1721
1722
1723 /*
1724  * CS stuff
1725  */
1726 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1727 {
1728         /* FIXME: implement */
1729         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1730         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1731         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1732         radeon_ring_write(rdev, ib->length_dw);
1733 }
1734
1735 int r600_ib_test(struct radeon_device *rdev)
1736 {
1737         struct radeon_ib *ib;
1738         uint32_t scratch;
1739         uint32_t tmp = 0;
1740         unsigned i;
1741         int r;
1742
1743         r = radeon_scratch_get(rdev, &scratch);
1744         if (r) {
1745                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1746                 return r;
1747         }
1748         WREG32(scratch, 0xCAFEDEAD);
1749         r = radeon_ib_get(rdev, &ib);
1750         if (r) {
1751                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1752                 return r;
1753         }
1754         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1755         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1756         ib->ptr[2] = 0xDEADBEEF;
1757         ib->ptr[3] = PACKET2(0);
1758         ib->ptr[4] = PACKET2(0);
1759         ib->ptr[5] = PACKET2(0);
1760         ib->ptr[6] = PACKET2(0);
1761         ib->ptr[7] = PACKET2(0);
1762         ib->ptr[8] = PACKET2(0);
1763         ib->ptr[9] = PACKET2(0);
1764         ib->ptr[10] = PACKET2(0);
1765         ib->ptr[11] = PACKET2(0);
1766         ib->ptr[12] = PACKET2(0);
1767         ib->ptr[13] = PACKET2(0);
1768         ib->ptr[14] = PACKET2(0);
1769         ib->ptr[15] = PACKET2(0);
1770         ib->length_dw = 16;
1771         r = radeon_ib_schedule(rdev, ib);
1772         if (r) {
1773                 radeon_scratch_free(rdev, scratch);
1774                 radeon_ib_free(rdev, &ib);
1775                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1776                 return r;
1777         }
1778         r = radeon_fence_wait(ib->fence, false);
1779         if (r) {
1780                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1781                 return r;
1782         }
1783         for (i = 0; i < rdev->usec_timeout; i++) {
1784                 tmp = RREG32(scratch);
1785                 if (tmp == 0xDEADBEEF)
1786                         break;
1787                 DRM_UDELAY(1);
1788         }
1789         if (i < rdev->usec_timeout) {
1790                 DRM_INFO("ib test succeeded in %u usecs\n", i);
1791         } else {
1792                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1793                           scratch, tmp);
1794                 r = -EINVAL;
1795         }
1796         radeon_scratch_free(rdev, scratch);
1797         radeon_ib_free(rdev, &ib);
1798         return r;
1799 }
1800
1801
1802
1803
1804 /*
1805  * Debugfs info
1806  */
1807 #if defined(CONFIG_DEBUG_FS)
1808
1809 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1810 {
1811         struct drm_info_node *node = (struct drm_info_node *) m->private;
1812         struct drm_device *dev = node->minor->dev;
1813         struct radeon_device *rdev = dev->dev_private;
1814         uint32_t rdp, wdp;
1815         unsigned count, i, j;
1816
1817         radeon_ring_free_size(rdev);
1818         rdp = RREG32(CP_RB_RPTR);
1819         wdp = RREG32(CP_RB_WPTR);
1820         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1821         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1822         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1823         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1824         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1825         seq_printf(m, "%u dwords in ring\n", count);
1826         for (j = 0; j <= count; j++) {
1827                 i = (rdp + j) & rdev->cp.ptr_mask;
1828                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1829         }
1830         return 0;
1831 }
1832
1833 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1834 {
1835         struct drm_info_node *node = (struct drm_info_node *) m->private;
1836         struct drm_device *dev = node->minor->dev;
1837         struct radeon_device *rdev = dev->dev_private;
1838
1839         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1840         DREG32_SYS(m, rdev, VM_L2_STATUS);
1841         return 0;
1842 }
1843
1844 static struct drm_info_list r600_mc_info_list[] = {
1845         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1846         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1847 };
1848 #endif
1849
1850 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1851 {
1852 #if defined(CONFIG_DEBUG_FS)
1853         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1854 #else
1855         return 0;
1856 #endif
1857 }