drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 /*
  36  * BIOS.
  37  */
  38
  39 /* If you boot an IGP board with a discrete card as the primary,
  40  * the IGP rom is not accessible via the rom bar as the IGP rom is
  41  * part of the system bios.  On boot, the system bios puts a
  42  * copy of the igp rom at the start of vram if a discrete card is
  43  * present.
  44  */
  45 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  46 {
  47         uint8_t __iomem *bios;
  48         resource_size_t vram_base;
  49         resource_size_t size = 256 * 1024; /* ??? */
  50
  51         if (!(rdev->flags & RADEON_IS_IGP))
  52                 if (!radeon_card_posted(rdev))
  53                         return false;
  54
  55         rdev->bios = NULL;
  56         vram_base = pci_resource_start(rdev->pdev, 0);
  57         bios = ioremap(vram_base, size);
  58         if (!bios) {
  59                 return false;
  60         }
  61
  62         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  63                 iounmap(bios);
  64                 return false;
  65         }
  66         rdev->bios = kmalloc(size, GFP_KERNEL);
  67         if (rdev->bios == NULL) {
  68                 iounmap(bios);
  69                 return false;
  70         }
  71         memcpy_fromio(rdev->bios, bios, size);
  72         iounmap(bios);
  73         return true;
  74 }
  75
  76 static bool radeon_read_bios(struct radeon_device *rdev)
  77 {
  78         uint8_t __iomem *bios;
  79         size_t size;
  80
  81         rdev->bios = NULL;
  82         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  83         bios = pci_map_rom(rdev->pdev, &size);
  84         if (!bios) {
  85                 return false;
  86         }
  87
  88         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  89                 pci_unmap_rom(rdev->pdev, bios);
  90                 return false;
  91         }
  92         rdev->bios = kmemdup(bios, size, GFP_KERNEL);
  93         if (rdev->bios == NULL) {
  94                 pci_unmap_rom(rdev->pdev, bios);
  95                 return false;
  96         }
  97         pci_unmap_rom(rdev->pdev, bios);
  98         return true;
  99 }
 100
 101 /* ATRM is used to get the BIOS on the discrete cards in
 102  * dual-gpu systems.
 103  */
 104 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 105 {
 106         int ret;
 107         int size = 64 * 1024;
 108         int i;
 109
 110         if (!radeon_atrm_supported(rdev->pdev))
 111                 return false;
 112
 113         rdev->bios = kmalloc(size, GFP_KERNEL);
 114         if (!rdev->bios) {
 115                 DRM_ERROR("Unable to allocate bios\n");
 116                 return false;
 117         }
 118
 119         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 120                 ret = radeon_atrm_get_bios_chunk(rdev->bios,
 121                                                  (i * ATRM_BIOS_PAGE),
 122                                                  ATRM_BIOS_PAGE);
 123                 if (ret <= 0)
 124                         break;
 125         }
 126
 127         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 128                 kfree(rdev->bios);
 129                 return false;
 130         }
 131         return true;
 132 }
 133
 134 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 135 {
 136         uint32_t viph_control;
 137         uint32_t bus_cntl;
 138         uint32_t d1vga_control;
 139         uint32_t d2vga_control;
 140         uint32_t vga_render_control;
 141         uint32_t rom_cntl;
 142         uint32_t cg_spll_func_cntl = 0;
 143         uint32_t cg_spll_status;
 144         bool r;
 145
 146         viph_control = RREG32(RADEON_VIPH_CONTROL);
 147         bus_cntl = RREG32(R600_BUS_CNTL);
 148         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 149         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 150         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 151         rom_cntl = RREG32(R600_ROM_CNTL);
 152
 153         /* disable VIP */
 154         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 155         /* enable the rom */
 156         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 157         /* Disable VGA mode */
 158         WREG32(AVIVO_D1VGA_CONTROL,
 159                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 160                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 161         WREG32(AVIVO_D2VGA_CONTROL,
 162                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 163                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 164         WREG32(AVIVO_VGA_RENDER_CONTROL,
 165                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 166
 167         if (rdev->family == CHIP_RV730) {
 168                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 169
 170                 /* enable bypass mode */
 171                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 172                                                 R600_SPLL_BYPASS_EN));
 173
 174                 /* wait for SPLL_CHG_STATUS to change to 1 */
 175                 cg_spll_status = 0;
 176                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 177                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 178
 179                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 180         } else
 181                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 182
 183         r = radeon_read_bios(rdev);
 184
 185         /* restore regs */
 186         if (rdev->family == CHIP_RV730) {
 187                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 188
 189                 /* wait for SPLL_CHG_STATUS to change to 1 */
 190                 cg_spll_status = 0;
 191                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 192                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 193         }
 194         WREG32(RADEON_VIPH_CONTROL, viph_control);
 195         WREG32(R600_BUS_CNTL, bus_cntl);
 196         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 197         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 198         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 199         WREG32(R600_ROM_CNTL, rom_cntl);
 200         return r;
 201 }
 202
 203 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 204 {
 205         uint32_t viph_control;
 206         uint32_t bus_cntl;
 207         uint32_t d1vga_control;
 208         uint32_t d2vga_control;
 209         uint32_t vga_render_control;
 210         uint32_t rom_cntl;
 211         uint32_t general_pwrmgt;
 212         uint32_t low_vid_lower_gpio_cntl;
 213         uint32_t medium_vid_lower_gpio_cntl;
 214         uint32_t high_vid_lower_gpio_cntl;
 215         uint32_t ctxsw_vid_lower_gpio_cntl;
 216         uint32_t lower_gpio_enable;
 217         bool r;
 218
 219         viph_control = RREG32(RADEON_VIPH_CONTROL);
 220         bus_cntl = RREG32(R600_BUS_CNTL);
 221         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 222         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 223         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 224         rom_cntl = RREG32(R600_ROM_CNTL);
 225         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 226         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 227         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 228         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 229         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 230         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 231
 232         /* disable VIP */
 233         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 234         /* enable the rom */
 235         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 236         /* Disable VGA mode */
 237         WREG32(AVIVO_D1VGA_CONTROL,
 238                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 239                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 240         WREG32(AVIVO_D2VGA_CONTROL,
 241                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 242                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 243         WREG32(AVIVO_VGA_RENDER_CONTROL,
 244                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 245
 246         WREG32(R600_ROM_CNTL,
 247                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 248                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 249                 R600_SCK_OVERWRITE));
 250
 251         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 252         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 253                (low_vid_lower_gpio_cntl & ~0x400));
 254         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 255                (medium_vid_lower_gpio_cntl & ~0x400));
 256         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 257                (high_vid_lower_gpio_cntl & ~0x400));
 258         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 259                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 260         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 261
 262         r = radeon_read_bios(rdev);
 263
 264         /* restore regs */
 265         WREG32(RADEON_VIPH_CONTROL, viph_control);
 266         WREG32(R600_BUS_CNTL, bus_cntl);
 267         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 268         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 269         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 270         WREG32(R600_ROM_CNTL, rom_cntl);
 271         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 272         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 273         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 274         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 275         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 276         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 277         return r;
 278 }
 279
 280 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 281 {
 282         uint32_t seprom_cntl1;
 283         uint32_t viph_control;
 284         uint32_t bus_cntl;
 285         uint32_t d1vga_control;
 286         uint32_t d2vga_control;
 287         uint32_t vga_render_control;
 288         uint32_t gpiopad_a;
 289         uint32_t gpiopad_en;
 290         uint32_t gpiopad_mask;
 291         bool r;
 292
 293         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 294         viph_control = RREG32(RADEON_VIPH_CONTROL);
 295         bus_cntl = RREG32(RADEON_BUS_CNTL);
 296         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 297         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 298         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 299         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 300         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 301         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 302
 303         WREG32(RADEON_SEPROM_CNTL1,
 304                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 305                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 306         WREG32(RADEON_GPIOPAD_A, 0);
 307         WREG32(RADEON_GPIOPAD_EN, 0);
 308         WREG32(RADEON_GPIOPAD_MASK, 0);
 309
 310         /* disable VIP */
 311         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 312
 313         /* enable the rom */
 314         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 315
 316         /* Disable VGA mode */
 317         WREG32(AVIVO_D1VGA_CONTROL,
 318                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 319                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 320         WREG32(AVIVO_D2VGA_CONTROL,
 321                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 322                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 323         WREG32(AVIVO_VGA_RENDER_CONTROL,
 324                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 325
 326         r = radeon_read_bios(rdev);
 327
 328         /* restore regs */
 329         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 330         WREG32(RADEON_VIPH_CONTROL, viph_control);
 331         WREG32(RADEON_BUS_CNTL, bus_cntl);
 332         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 333         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 334         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 335         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 336         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 337         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 338         return r;
 339 }
 340
 341 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 342 {
 343         uint32_t seprom_cntl1;
 344         uint32_t viph_control;
 345         uint32_t bus_cntl;
 346         uint32_t crtc_gen_cntl;
 347         uint32_t crtc2_gen_cntl;
 348         uint32_t crtc_ext_cntl;
 349         uint32_t fp2_gen_cntl;
 350         bool r;
 351
 352         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 353         viph_control = RREG32(RADEON_VIPH_CONTROL);
 354         bus_cntl = RREG32(RADEON_BUS_CNTL);
 355         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 356         crtc2_gen_cntl = 0;
 357         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 358         fp2_gen_cntl = 0;
 359
 360         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 361                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 362         }
 363
 364         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 365                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 366         }
 367
 368         WREG32(RADEON_SEPROM_CNTL1,
 369                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 370                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 371
 372         /* disable VIP */
 373         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 374
 375         /* enable the rom */
 376         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 377
 378         /* Turn off mem requests and CRTC for both controllers */
 379         WREG32(RADEON_CRTC_GEN_CNTL,
 380                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 381                 (RADEON_CRTC_DISP_REQ_EN_B |
 382                  RADEON_CRTC_EXT_DISP_EN)));
 383         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 384                 WREG32(RADEON_CRTC2_GEN_CNTL,
 385                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 386                         RADEON_CRTC2_DISP_REQ_EN_B));
 387         }
 388         /* Turn off CRTC */
 389         WREG32(RADEON_CRTC_EXT_CNTL,
 390                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 391                 (RADEON_CRTC_SYNC_TRISTAT |
 392                  RADEON_CRTC_DISPLAY_DIS)));
 393
 394         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 395                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 396         }
 397
 398         r = radeon_read_bios(rdev);
 399
 400         /* restore regs */
 401         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 402         WREG32(RADEON_VIPH_CONTROL, viph_control);
 403         WREG32(RADEON_BUS_CNTL, bus_cntl);
 404         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 405         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 406                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 407         }
 408         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 409         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 410                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 411         }
 412         return r;
 413 }
 414
 415 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 416 {
 417         if (rdev->flags & RADEON_IS_IGP)
 418                 return igp_read_bios_from_vram(rdev);
 419         else if (rdev->family >= CHIP_RV770)
 420                 return r700_read_disabled_bios(rdev);
 421         else if (rdev->family >= CHIP_R600)
 422                 return r600_read_disabled_bios(rdev);
 423         else if (rdev->family >= CHIP_RS600)
 424                 return avivo_read_disabled_bios(rdev);
 425         else
 426                 return legacy_read_disabled_bios(rdev);
 427 }
 428
 429
 430 bool radeon_get_bios(struct radeon_device *rdev)
 431 {
 432         bool r;
 433         uint16_t tmp;
 434
 435         r = radeon_atrm_get_bios(rdev);
 436         if (r == false)
 437                 r = igp_read_bios_from_vram(rdev);
 438         if (r == false)
 439                 r = radeon_read_bios(rdev);
 440         if (r == false) {
 441                 r = radeon_read_disabled_bios(rdev);
 442         }
 443         if (r == false || rdev->bios == NULL) {
 444                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 445                 rdev->bios = NULL;
 446                 return false;
 447         }
 448         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 449                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 450                 goto free_bios;
 451         }
 452
 453         tmp = RBIOS16(0x18);
 454         if (RBIOS8(tmp + 0x14) != 0x0) {
 455                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 456                 goto free_bios;
 457         }
 458
 459         rdev->bios_header_start = RBIOS16(0x48);
 460         if (!rdev->bios_header_start) {
 461                 goto free_bios;
 462         }
 463         tmp = rdev->bios_header_start + 4;
 464         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 465             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 466                 rdev->is_atom_bios = true;
 467         } else {
 468                 rdev->is_atom_bios = false;
 469         }
 470
 471         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 472         return true;
 473 free_bios:
 474         kfree(rdev->bios);
 475         rdev->bios = NULL;
 476         return false;
 477 }