drivers/gpu/drm/radeon/radeon_kfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <drm/drmP.h>
  27 #include "radeon.h"
  28 #include "cikd.h"
  29 #include "cik_reg.h"
  30 #include "radeon_kfd.h"
  31 #include "radeon_ucode.h"
  32 #include <linux/firmware.h>
  33
  34 #define CIK_PIPE_PER_MEC        (4)
  35
  36 struct kgd_mem {
  37         struct radeon_sa_bo *sa_bo;
  38         uint64_t gpu_addr;
  39         void *ptr;
  40 };
  41
  42 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size);
  43 static void fini_sa_manager(struct kgd_dev *kgd);
  44
  45 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
  46                 enum kgd_memory_pool pool, struct kgd_mem **mem);
  47
  48 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem);
  49
  50 static uint64_t get_vmem_size(struct kgd_dev *kgd);
  51 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
  52
  53 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
  54 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
  55
  56 /*
  57  * Register access functions
  58  */
  59
  60 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  61                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  62                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  63
  64 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  65                                         unsigned int vmid);
  66
  67 static int kgd_init_memory(struct kgd_dev *kgd);
  68
  69 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
  70                                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
  71
  72 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  73                         uint32_t queue_id, uint32_t __user *wptr);
  74
  75 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
  76                                 uint32_t pipe_id, uint32_t queue_id);
  77
  78 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
  79                                 unsigned int timeout, uint32_t pipe_id,
  80                                 uint32_t queue_id);
  81
  82 static const struct kfd2kgd_calls kfd2kgd = {
  83         .init_sa_manager = init_sa_manager,
  84         .fini_sa_manager = fini_sa_manager,
  85         .allocate_mem = allocate_mem,
  86         .free_mem = free_mem,
  87         .get_vmem_size = get_vmem_size,
  88         .get_gpu_clock_counter = get_gpu_clock_counter,
  89         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
  90         .program_sh_mem_settings = kgd_program_sh_mem_settings,
  91         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
  92         .init_memory = kgd_init_memory,
  93         .init_pipeline = kgd_init_pipeline,
  94         .hqd_load = kgd_hqd_load,
  95         .hqd_is_occupies = kgd_hqd_is_occupies,
  96         .hqd_destroy = kgd_hqd_destroy,
  97         .get_fw_version = get_fw_version
  98 };
  99
 100 static const struct kgd2kfd_calls *kgd2kfd;
 101
 102 bool radeon_kfd_init(void)
 103 {
 104         bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
 105                                 const struct kgd2kfd_calls**);
 106
 107         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
 108
 109         if (kgd2kfd_init_p == NULL)
 110                 return false;
 111
 112         if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
 113                 symbol_put(kgd2kfd_init);
 114                 kgd2kfd = NULL;
 115
 116                 return false;
 117         }
 118
 119         return true;
 120 }
 121
 122 void radeon_kfd_fini(void)
 123 {
 124         if (kgd2kfd) {
 125                 kgd2kfd->exit();
 126                 symbol_put(kgd2kfd_init);
 127         }
 128 }
 129
 130 void radeon_kfd_device_probe(struct radeon_device *rdev)
 131 {
 132         if (kgd2kfd)
 133                 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
 134 }
 135
 136 void radeon_kfd_device_init(struct radeon_device *rdev)
 137 {
 138         if (rdev->kfd) {
 139                 struct kgd2kfd_shared_resources gpu_resources = {
 140                         .compute_vmid_bitmap = 0xFF00,
 141
 142                         .first_compute_pipe = 1,
 143                         .compute_pipe_count = 8 - 1,
 144                 };
 145
 146                 radeon_doorbell_get_kfd_info(rdev,
 147                                 &gpu_resources.doorbell_physical_address,
 148                                 &gpu_resources.doorbell_aperture_size,
 149                                 &gpu_resources.doorbell_start_offset);
 150
 151                 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
 152         }
 153 }
 154
 155 void radeon_kfd_device_fini(struct radeon_device *rdev)
 156 {
 157         if (rdev->kfd) {
 158                 kgd2kfd->device_exit(rdev->kfd);
 159                 rdev->kfd = NULL;
 160         }
 161 }
 162
 163 void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
 164 {
 165         if (rdev->kfd)
 166                 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
 167 }
 168
 169 void radeon_kfd_suspend(struct radeon_device *rdev)
 170 {
 171         if (rdev->kfd)
 172                 kgd2kfd->suspend(rdev->kfd);
 173 }
 174
 175 int radeon_kfd_resume(struct radeon_device *rdev)
 176 {
 177         int r = 0;
 178
 179         if (rdev->kfd)
 180                 r = kgd2kfd->resume(rdev->kfd);
 181
 182         return r;
 183 }
 184
 185 static u32 pool_to_domain(enum kgd_memory_pool p)
 186 {
 187         switch (p) {
 188         case KGD_POOL_FRAMEBUFFER: return RADEON_GEM_DOMAIN_VRAM;
 189         default: return RADEON_GEM_DOMAIN_GTT;
 190         }
 191 }
 192
 193 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size)
 194 {
 195         struct radeon_device *rdev = (struct radeon_device *)kgd;
 196         int r;
 197
 198         BUG_ON(kgd == NULL);
 199
 200         r = radeon_sa_bo_manager_init(rdev, &rdev->kfd_bo,
 201                                       size,
 202                                       RADEON_GPU_PAGE_SIZE,
 203                                       RADEON_GEM_DOMAIN_GTT,
 204                                       RADEON_GEM_GTT_WC);
 205
 206         if (r)
 207                 return r;
 208
 209         r = radeon_sa_bo_manager_start(rdev, &rdev->kfd_bo);
 210         if (r)
 211                 radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 212
 213         return r;
 214 }
 215
 216 static void fini_sa_manager(struct kgd_dev *kgd)
 217 {
 218         struct radeon_device *rdev = (struct radeon_device *)kgd;
 219
 220         BUG_ON(kgd == NULL);
 221
 222         radeon_sa_bo_manager_suspend(rdev, &rdev->kfd_bo);
 223         radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 224 }
 225
 226 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
 227                 enum kgd_memory_pool pool, struct kgd_mem **mem)
 228 {
 229         struct radeon_device *rdev = (struct radeon_device *)kgd;
 230         u32 domain;
 231         int r;
 232
 233         BUG_ON(kgd == NULL);
 234
 235         domain = pool_to_domain(pool);
 236         if (domain != RADEON_GEM_DOMAIN_GTT) {
 237                 dev_err(rdev->dev,
 238                         "Only allowed to allocate gart memory for kfd\n");
 239                 return -EINVAL;
 240         }
 241
 242         *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
 243         if ((*mem) == NULL)
 244                 return -ENOMEM;
 245
 246         r = radeon_sa_bo_new(rdev, &rdev->kfd_bo, &(*mem)->sa_bo, size,
 247                                 alignment);
 248         if (r) {
 249                 dev_err(rdev->dev, "failed to get memory for kfd (%d)\n", r);
 250                 return r;
 251         }
 252
 253         (*mem)->ptr = radeon_sa_bo_cpu_addr((*mem)->sa_bo);
 254         (*mem)->gpu_addr = radeon_sa_bo_gpu_addr((*mem)->sa_bo);
 255
 256         return 0;
 257 }
 258
 259 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem)
 260 {
 261         struct radeon_device *rdev = (struct radeon_device *)kgd;
 262
 263         BUG_ON(kgd == NULL);
 264
 265         radeon_sa_bo_free(rdev, &mem->sa_bo, NULL);
 266         kfree(mem);
 267 }
 268
 269 static uint64_t get_vmem_size(struct kgd_dev *kgd)
 270 {
 271         struct radeon_device *rdev = (struct radeon_device *)kgd;
 272
 273         BUG_ON(kgd == NULL);
 274
 275         return rdev->mc.real_vram_size;
 276 }
 277
 278 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 279 {
 280         struct radeon_device *rdev = (struct radeon_device *)kgd;
 281
 282         return rdev->asic->get_gpu_clock_counter(rdev);
 283 }
 284
 285 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 286 {
 287         struct radeon_device *rdev = (struct radeon_device *)kgd;
 288
 289         /* The sclk is in quantas of 10kHz */
 290         return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
 291 }
 292
 293 static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
 294 {
 295         return (struct radeon_device *)kgd;
 296 }
 297
 298 static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
 299 {
 300         struct radeon_device *rdev = get_radeon_device(kgd);
 301
 302         writel(value, (void __iomem *)(rdev->rmmio + offset));
 303 }
 304
 305 static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
 306 {
 307         struct radeon_device *rdev = get_radeon_device(kgd);
 308
 309         return readl((void __iomem *)(rdev->rmmio + offset));
 310 }
 311
 312 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 313                         uint32_t queue, uint32_t vmid)
 314 {
 315         struct radeon_device *rdev = get_radeon_device(kgd);
 316         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 317
 318         mutex_lock(&rdev->srbm_mutex);
 319         write_register(kgd, SRBM_GFX_CNTL, value);
 320 }
 321
 322 static void unlock_srbm(struct kgd_dev *kgd)
 323 {
 324         struct radeon_device *rdev = get_radeon_device(kgd);
 325
 326         write_register(kgd, SRBM_GFX_CNTL, 0);
 327         mutex_unlock(&rdev->srbm_mutex);
 328 }
 329
 330 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 331                                 uint32_t queue_id)
 332 {
 333         uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
 334         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 335
 336         lock_srbm(kgd, mec, pipe, queue_id, 0);
 337 }
 338
 339 static void release_queue(struct kgd_dev *kgd)
 340 {
 341         unlock_srbm(kgd);
 342 }
 343
 344 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 345                                         uint32_t sh_mem_config,
 346                                         uint32_t sh_mem_ape1_base,
 347                                         uint32_t sh_mem_ape1_limit,
 348                                         uint32_t sh_mem_bases)
 349 {
 350         lock_srbm(kgd, 0, 0, 0, vmid);
 351
 352         write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 353         write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
 354         write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 355         write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 356
 357         unlock_srbm(kgd);
 358 }
 359
 360 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 361                                         unsigned int vmid)
 362 {
 363         /*
 364          * We have to assume that there is no outstanding mapping.
 365          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
 366          * because a mapping is in progress or because a mapping finished and
 367          * the SW cleared it.
 368          * So the protocol is to always wait & clear.
 369          */
 370         uint32_t pasid_mapping = (pasid == 0) ? 0 :
 371                                 (uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;
 372
 373         write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
 374                         pasid_mapping);
 375
 376         while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
 377                                                                 (1U << vmid)))
 378                 cpu_relax();
 379         write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 380
 381         return 0;
 382 }
 383
 384 static int kgd_init_memory(struct kgd_dev *kgd)
 385 {
 386         /*
 387          * Configure apertures:
 388          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 389          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 390          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 391          */
 392         int i;
 393         uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);
 394
 395         for (i = 8; i < 16; i++) {
 396                 uint32_t sh_mem_config;
 397
 398                 lock_srbm(kgd, 0, 0, 0, i);
 399
 400                 sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 401                 sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
 402
 403                 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 404
 405                 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 406
 407                 /* Scratch aperture is not supported for now. */
 408                 write_register(kgd, SH_STATIC_MEM_CONFIG, 0);
 409
 410                 /* APE1 disabled for now. */
 411                 write_register(kgd, SH_MEM_APE1_BASE, 1);
 412                 write_register(kgd, SH_MEM_APE1_LIMIT, 0);
 413
 414                 unlock_srbm(kgd);
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 421                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 422 {
 423         uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
 424         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 425
 426         lock_srbm(kgd, mec, pipe, 0, 0);
 427         write_register(kgd, CP_HPD_EOP_BASE_ADDR,
 428                         lower_32_bits(hpd_gpu_addr >> 8));
 429         write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
 430                         upper_32_bits(hpd_gpu_addr >> 8));
 431         write_register(kgd, CP_HPD_EOP_VMID, 0);
 432         write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
 433         unlock_srbm(kgd);
 434
 435         return 0;
 436 }
 437
 438 static inline struct cik_mqd *get_mqd(void *mqd)
 439 {
 440         return (struct cik_mqd *)mqd;
 441 }
 442
 443 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 444                         uint32_t queue_id, uint32_t __user *wptr)
 445 {
 446         uint32_t wptr_shadow, is_wptr_shadow_valid;
 447         struct cik_mqd *m;
 448
 449         m = get_mqd(mqd);
 450
 451         is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
 452
 453         acquire_queue(kgd, pipe_id, queue_id);
 454         write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
 455         write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
 456         write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
 457
 458         write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
 459         write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
 460         write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
 461
 462         write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
 463         write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
 464         write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
 465
 466         write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
 467
 468         write_register(kgd, CP_HQD_PERSISTENT_STATE,
 469                         m->cp_hqd_persistent_state);
 470         write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
 471         write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
 472
 473         write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
 474                         m->cp_hqd_atomic0_preop_lo);
 475
 476         write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
 477                         m->cp_hqd_atomic0_preop_hi);
 478
 479         write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
 480                         m->cp_hqd_atomic1_preop_lo);
 481
 482         write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
 483                         m->cp_hqd_atomic1_preop_hi);
 484
 485         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
 486                         m->cp_hqd_pq_rptr_report_addr_lo);
 487
 488         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 489                         m->cp_hqd_pq_rptr_report_addr_hi);
 490
 491         write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
 492
 493         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
 494                         m->cp_hqd_pq_wptr_poll_addr_lo);
 495
 496         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
 497                         m->cp_hqd_pq_wptr_poll_addr_hi);
 498
 499         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
 500                         m->cp_hqd_pq_doorbell_control);
 501
 502         write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
 503
 504         write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
 505
 506         write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
 507         write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
 508
 509         write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
 510
 511         if (is_wptr_shadow_valid)
 512                 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
 513
 514         write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
 515         release_queue(kgd);
 516
 517         return 0;
 518 }
 519
 520 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
 521                                 uint32_t pipe_id, uint32_t queue_id)
 522 {
 523         uint32_t act;
 524         bool retval = false;
 525         uint32_t low, high;
 526
 527         acquire_queue(kgd, pipe_id, queue_id);
 528         act = read_register(kgd, CP_HQD_ACTIVE);
 529         if (act) {
 530                 low = lower_32_bits(queue_address >> 8);
 531                 high = upper_32_bits(queue_address >> 8);
 532
 533                 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
 534                                 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
 535                         retval = true;
 536         }
 537         release_queue(kgd);
 538         return retval;
 539 }
 540
 541 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
 542                                 unsigned int timeout, uint32_t pipe_id,
 543                                 uint32_t queue_id)
 544 {
 545         uint32_t temp;
 546
 547         acquire_queue(kgd, pipe_id, queue_id);
 548         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
 549
 550         write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
 551
 552         while (true) {
 553                 temp = read_register(kgd, CP_HQD_ACTIVE);
 554                 if (temp & 0x1)
 555                         break;
 556                 if (timeout == 0) {
 557                         pr_err("kfd: cp queue preemption time out (%dms)\n",
 558                                 temp);
 559                         return -ETIME;
 560                 }
 561                 msleep(20);
 562                 timeout -= 20;
 563         }
 564
 565         release_queue(kgd);
 566         return 0;
 567 }
 568
 569 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 570 {
 571         struct radeon_device *rdev = (struct radeon_device *) kgd;
 572         const union radeon_firmware_header *hdr;
 573
 574         BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
 575
 576         switch (type) {
 577         case KGD_ENGINE_PFP:
 578                 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
 579                 break;
 580
 581         case KGD_ENGINE_ME:
 582                 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
 583                 break;
 584
 585         case KGD_ENGINE_CE:
 586                 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
 587                 break;
 588
 589         case KGD_ENGINE_MEC1:
 590                 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
 591                 break;
 592
 593         case KGD_ENGINE_MEC2:
 594                 hdr = (const union radeon_firmware_header *)
 595                                                         rdev->mec2_fw->data;
 596                 break;
 597
 598         case KGD_ENGINE_RLC:
 599                 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
 600                 break;
 601
 602         case KGD_ENGINE_SDMA:
 603                 hdr = (const union radeon_firmware_header *)
 604                                                         rdev->sdma_fw->data;
 605                 break;
 606
 607         default:
 608                 return 0;
 609         }
 610
 611         if (hdr == NULL)
 612                 return 0;
 613
 614         /* Only 12 bit in use*/
 615         return hdr->common.ucode_version;
 616 }