drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_update_memory_usage(struct radeon_bo *bo,
  50                                        unsigned mem_type, int sign)
  51 {
  52         struct radeon_device *rdev = bo->rdev;
  53         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  54
  55         switch (mem_type) {
  56         case TTM_PL_TT:
  57                 if (sign > 0)
  58                         atomic64_add(size, &rdev->gtt_usage);
  59                 else
  60                         atomic64_sub(size, &rdev->gtt_usage);
  61                 break;
  62         case TTM_PL_VRAM:
  63                 if (sign > 0)
  64                         atomic64_add(size, &rdev->vram_usage);
  65                 else
  66                         atomic64_sub(size, &rdev->vram_usage);
  67                 break;
  68         }
  69 }
  70
  71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  72 {
  73         struct radeon_bo *bo;
  74
  75         bo = container_of(tbo, struct radeon_bo, tbo);
  76
  77         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  78         radeon_mn_unregister(bo);
  79
  80         mutex_lock(&bo->rdev->gem.mutex);
  81         list_del_init(&bo->list);
  82         mutex_unlock(&bo->rdev->gem.mutex);
  83         radeon_bo_clear_surface_reg(bo);
  84         WARN_ON(!list_empty(&bo->va));
  85         drm_gem_object_release(&bo->gem_base);
  86         kfree(bo);
  87 }
  88
  89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  90 {
  91         if (bo->destroy == &radeon_ttm_bo_destroy)
  92                 return true;
  93         return false;
  94 }
  95
  96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  97 {
  98         u32 c = 0, i;
  99
 100         rbo->placement.placement = rbo->placements;
 101         rbo->placement.busy_placement = rbo->placements;
 102         if (domain & RADEON_GEM_DOMAIN_VRAM) {
 103                 /* Try placing BOs which don't need CPU access outside of the
 104                  * CPU accessible part of VRAM
 105                  */
 106                 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 107                     rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
 108                         rbo->placements[c].fpfn =
 109                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 110                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 111                                                      TTM_PL_FLAG_UNCACHED |
 112                                                      TTM_PL_FLAG_VRAM;
 113                 }
 114
 115                 rbo->placements[c].fpfn = 0;
 116                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 117                                              TTM_PL_FLAG_UNCACHED |
 118                                              TTM_PL_FLAG_VRAM;
 119         }
 120
 121         if (domain & RADEON_GEM_DOMAIN_GTT) {
 122                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 123                         rbo->placements[c].fpfn = 0;
 124                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 125                                 TTM_PL_FLAG_TT;
 126
 127                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 128                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 129                         rbo->placements[c].fpfn = 0;
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 131                                 TTM_PL_FLAG_UNCACHED |
 132                                 TTM_PL_FLAG_TT;
 133                 } else {
 134                         rbo->placements[c].fpfn = 0;
 135                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 136                                                      TTM_PL_FLAG_TT;
 137                 }
 138         }
 139
 140         if (domain & RADEON_GEM_DOMAIN_CPU) {
 141                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 142                         rbo->placements[c].fpfn = 0;
 143                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 144                                 TTM_PL_FLAG_SYSTEM;
 145
 146                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 147                     rbo->rdev->flags & RADEON_IS_AGP) {
 148                         rbo->placements[c].fpfn = 0;
 149                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 150                                 TTM_PL_FLAG_UNCACHED |
 151                                 TTM_PL_FLAG_SYSTEM;
 152                 } else {
 153                         rbo->placements[c].fpfn = 0;
 154                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 155                                                      TTM_PL_FLAG_SYSTEM;
 156                 }
 157         }
 158         if (!c) {
 159                 rbo->placements[c].fpfn = 0;
 160                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 161                                              TTM_PL_FLAG_SYSTEM;
 162         }
 163
 164         rbo->placement.num_placement = c;
 165         rbo->placement.num_busy_placement = c;
 166
 167         for (i = 0; i < c; ++i) {
 168                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 169                     (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 170                     !rbo->placements[i].fpfn)
 171                         rbo->placements[i].lpfn =
 172                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 173                 else
 174                         rbo->placements[i].lpfn = 0;
 175         }
 176
 177         /*
 178          * Use two-ended allocation depending on the buffer size to
 179          * improve fragmentation quality.
 180          * 512kb was measured as the most optimal number.
 181          */
 182         if (rbo->tbo.mem.size > 512 * 1024) {
 183                 for (i = 0; i < c; i++) {
 184                         rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
 185                 }
 186         }
 187 }
 188
 189 int radeon_bo_create(struct radeon_device *rdev,
 190                      unsigned long size, int byte_align, bool kernel,
 191                      u32 domain, u32 flags, struct sg_table *sg,
 192                      struct reservation_object *resv,
 193                      struct radeon_bo **bo_ptr)
 194 {
 195         struct radeon_bo *bo;
 196         enum ttm_bo_type type;
 197         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 198         size_t acc_size;
 199         int r;
 200
 201         size = ALIGN(size, PAGE_SIZE);
 202
 203         if (kernel) {
 204                 type = ttm_bo_type_kernel;
 205         } else if (sg) {
 206                 type = ttm_bo_type_sg;
 207         } else {
 208                 type = ttm_bo_type_device;
 209         }
 210         *bo_ptr = NULL;
 211
 212         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 213                                        sizeof(struct radeon_bo));
 214
 215         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 216         if (bo == NULL)
 217                 return -ENOMEM;
 218         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 219         if (unlikely(r)) {
 220                 kfree(bo);
 221                 return r;
 222         }
 223         bo->rdev = rdev;
 224         bo->surface_reg = -1;
 225         INIT_LIST_HEAD(&bo->list);
 226         INIT_LIST_HEAD(&bo->va);
 227         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 228                                        RADEON_GEM_DOMAIN_GTT |
 229                                        RADEON_GEM_DOMAIN_CPU);
 230
 231         bo->flags = flags;
 232         /* PCI GART is always snooped */
 233         if (!(rdev->flags & RADEON_IS_PCIE))
 234                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 235
 236         radeon_ttm_placement_from_domain(bo, domain);
 237         /* Kernel allocation are uninterruptible */
 238         down_read(&rdev->pm.mclk_lock);
 239         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 240                         &bo->placement, page_align, !kernel, NULL,
 241                         acc_size, sg, resv, &radeon_ttm_bo_destroy);
 242         up_read(&rdev->pm.mclk_lock);
 243         if (unlikely(r != 0)) {
 244                 return r;
 245         }
 246         *bo_ptr = bo;
 247
 248         trace_radeon_bo_create(bo);
 249
 250         return 0;
 251 }
 252
 253 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 254 {
 255         bool is_iomem;
 256         int r;
 257
 258         if (bo->kptr) {
 259                 if (ptr) {
 260                         *ptr = bo->kptr;
 261                 }
 262                 return 0;
 263         }
 264         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 265         if (r) {
 266                 return r;
 267         }
 268         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 269         if (ptr) {
 270                 *ptr = bo->kptr;
 271         }
 272         radeon_bo_check_tiling(bo, 0, 0);
 273         return 0;
 274 }
 275
 276 void radeon_bo_kunmap(struct radeon_bo *bo)
 277 {
 278         if (bo->kptr == NULL)
 279                 return;
 280         bo->kptr = NULL;
 281         radeon_bo_check_tiling(bo, 0, 0);
 282         ttm_bo_kunmap(&bo->kmap);
 283 }
 284
 285 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 286 {
 287         if (bo == NULL)
 288                 return NULL;
 289
 290         ttm_bo_reference(&bo->tbo);
 291         return bo;
 292 }
 293
 294 void radeon_bo_unref(struct radeon_bo **bo)
 295 {
 296         struct ttm_buffer_object *tbo;
 297         struct radeon_device *rdev;
 298
 299         if ((*bo) == NULL)
 300                 return;
 301         rdev = (*bo)->rdev;
 302         tbo = &((*bo)->tbo);
 303         ttm_bo_unref(&tbo);
 304         if (tbo == NULL)
 305                 *bo = NULL;
 306 }
 307
 308 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 309                              u64 *gpu_addr)
 310 {
 311         int r, i;
 312
 313         if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
 314                 return -EPERM;
 315
 316         if (bo->pin_count) {
 317                 bo->pin_count++;
 318                 if (gpu_addr)
 319                         *gpu_addr = radeon_bo_gpu_offset(bo);
 320
 321                 if (max_offset != 0) {
 322                         u64 domain_start;
 323
 324                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 325                                 domain_start = bo->rdev->mc.vram_start;
 326                         else
 327                                 domain_start = bo->rdev->mc.gtt_start;
 328                         WARN_ON_ONCE(max_offset <
 329                                      (radeon_bo_gpu_offset(bo) - domain_start));
 330                 }
 331
 332                 return 0;
 333         }
 334         radeon_ttm_placement_from_domain(bo, domain);
 335         for (i = 0; i < bo->placement.num_placement; i++) {
 336                 /* force to pin into visible video ram */
 337                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 338                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 339                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 340                         bo->placements[i].lpfn =
 341                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 342                 else
 343                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 344
 345                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 346         }
 347
 348         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 349         if (likely(r == 0)) {
 350                 bo->pin_count = 1;
 351                 if (gpu_addr != NULL)
 352                         *gpu_addr = radeon_bo_gpu_offset(bo);
 353                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 354                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 355                 else
 356                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 357         } else {
 358                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 359         }
 360         return r;
 361 }
 362
 363 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 364 {
 365         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 366 }
 367
 368 int radeon_bo_unpin(struct radeon_bo *bo)
 369 {
 370         int r, i;
 371
 372         if (!bo->pin_count) {
 373                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 374                 return 0;
 375         }
 376         bo->pin_count--;
 377         if (bo->pin_count)
 378                 return 0;
 379         for (i = 0; i < bo->placement.num_placement; i++) {
 380                 bo->placements[i].lpfn = 0;
 381                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 382         }
 383         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 384         if (likely(r == 0)) {
 385                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 386                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 387                 else
 388                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 389         } else {
 390                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 391         }
 392         return r;
 393 }
 394
 395 int radeon_bo_evict_vram(struct radeon_device *rdev)
 396 {
 397         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 398         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 399                 if (rdev->mc.igp_sideport_enabled == false)
 400                         /* Useless to evict on IGP chips */
 401                         return 0;
 402         }
 403         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 404 }
 405
 406 void radeon_bo_force_delete(struct radeon_device *rdev)
 407 {
 408         struct radeon_bo *bo, *n;
 409
 410         if (list_empty(&rdev->gem.objects)) {
 411                 return;
 412         }
 413         dev_err(rdev->dev, "Userspace still has active objects !\n");
 414         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 415                 mutex_lock(&rdev->ddev->struct_mutex);
 416                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 417                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 418                         *((unsigned long *)&bo->gem_base.refcount));
 419                 mutex_lock(&bo->rdev->gem.mutex);
 420                 list_del_init(&bo->list);
 421                 mutex_unlock(&bo->rdev->gem.mutex);
 422                 /* this should unref the ttm bo */
 423                 drm_gem_object_unreference(&bo->gem_base);
 424                 mutex_unlock(&rdev->ddev->struct_mutex);
 425         }
 426 }
 427
 428 int radeon_bo_init(struct radeon_device *rdev)
 429 {
 430         /* Add an MTRR for the VRAM */
 431         if (!rdev->fastfb_working) {
 432                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 433                                                       rdev->mc.aper_size);
 434         }
 435         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 436                 rdev->mc.mc_vram_size >> 20,
 437                 (unsigned long long)rdev->mc.aper_size >> 20);
 438         DRM_INFO("RAM width %dbits %cDR\n",
 439                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 440         return radeon_ttm_init(rdev);
 441 }
 442
 443 void radeon_bo_fini(struct radeon_device *rdev)
 444 {
 445         radeon_ttm_fini(rdev);
 446         arch_phys_wc_del(rdev->mc.vram_mtrr);
 447 }
 448
 449 /* Returns how many bytes TTM can move per IB.
 450  */
 451 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 452 {
 453         u64 real_vram_size = rdev->mc.real_vram_size;
 454         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 455
 456         /* This function is based on the current VRAM usage.
 457          *
 458          * - If all of VRAM is free, allow relocating the number of bytes that
 459          *   is equal to 1/4 of the size of VRAM for this IB.
 460
 461          * - If more than one half of VRAM is occupied, only allow relocating
 462          *   1 MB of data for this IB.
 463          *
 464          * - From 0 to one half of used VRAM, the threshold decreases
 465          *   linearly.
 466          *         __________________
 467          * 1/4 of -|\               |
 468          * VRAM    | \              |
 469          *         |  \             |
 470          *         |   \            |
 471          *         |    \           |
 472          *         |     \          |
 473          *         |      \         |
 474          *         |       \________|1 MB
 475          *         |----------------|
 476          *    VRAM 0 %             100 %
 477          *         used            used
 478          *
 479          * Note: It's a threshold, not a limit. The threshold must be crossed
 480          * for buffer relocations to stop, so any buffer of an arbitrary size
 481          * can be moved as long as the threshold isn't crossed before
 482          * the relocation takes place. We don't want to disable buffer
 483          * relocations completely.
 484          *
 485          * The idea is that buffers should be placed in VRAM at creation time
 486          * and TTM should only do a minimum number of relocations during
 487          * command submission. In practice, you need to submit at least
 488          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 489          *
 490          * Also, things can get pretty crazy under memory pressure and actual
 491          * VRAM usage can change a lot, so playing safe even at 50% does
 492          * consistently increase performance.
 493          */
 494
 495         u64 half_vram = real_vram_size >> 1;
 496         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 497         u64 bytes_moved_threshold = half_free_vram >> 1;
 498         return max(bytes_moved_threshold, 1024*1024ull);
 499 }
 500
 501 int radeon_bo_list_validate(struct radeon_device *rdev,
 502                             struct ww_acquire_ctx *ticket,
 503                             struct list_head *head, int ring)
 504 {
 505         struct radeon_cs_reloc *lobj;
 506         struct radeon_bo *bo;
 507         int r;
 508         u64 bytes_moved = 0, initial_bytes_moved;
 509         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 510
 511         r = ttm_eu_reserve_buffers(ticket, head, true);
 512         if (unlikely(r != 0)) {
 513                 return r;
 514         }
 515
 516         list_for_each_entry(lobj, head, tv.head) {
 517                 bo = lobj->robj;
 518                 if (!bo->pin_count) {
 519                         u32 domain = lobj->prefered_domains;
 520                         u32 allowed = lobj->allowed_domains;
 521                         u32 current_domain =
 522                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 523
 524                         WARN_ONCE(bo->gem_base.dumb,
 525                                   "GPU use of dumb buffer is illegal.\n");
 526
 527                         /* Check if this buffer will be moved and don't move it
 528                          * if we have moved too many buffers for this IB already.
 529                          *
 530                          * Note that this allows moving at least one buffer of
 531                          * any size, because it doesn't take the current "bo"
 532                          * into account. We don't want to disallow buffer moves
 533                          * completely.
 534                          */
 535                         if ((allowed & current_domain) != 0 &&
 536                             (domain & current_domain) == 0 && /* will be moved */
 537                             bytes_moved > bytes_moved_threshold) {
 538                                 /* don't move it */
 539                                 domain = current_domain;
 540                         }
 541
 542                 retry:
 543                         radeon_ttm_placement_from_domain(bo, domain);
 544                         if (ring == R600_RING_TYPE_UVD_INDEX)
 545                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 546
 547                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 548                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 549                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 550                                        initial_bytes_moved;
 551
 552                         if (unlikely(r)) {
 553                                 if (r != -ERESTARTSYS &&
 554                                     domain != lobj->allowed_domains) {
 555                                         domain = lobj->allowed_domains;
 556                                         goto retry;
 557                                 }
 558                                 ttm_eu_backoff_reservation(ticket, head);
 559                                 return r;
 560                         }
 561                 }
 562                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 563                 lobj->tiling_flags = bo->tiling_flags;
 564         }
 565         return 0;
 566 }
 567
 568 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 569                              struct vm_area_struct *vma)
 570 {
 571         return ttm_fbdev_mmap(vma, &bo->tbo);
 572 }
 573
 574 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 575 {
 576         struct radeon_device *rdev = bo->rdev;
 577         struct radeon_surface_reg *reg;
 578         struct radeon_bo *old_object;
 579         int steal;
 580         int i;
 581
 582         lockdep_assert_held(&bo->tbo.resv->lock.base);
 583
 584         if (!bo->tiling_flags)
 585                 return 0;
 586
 587         if (bo->surface_reg >= 0) {
 588                 reg = &rdev->surface_regs[bo->surface_reg];
 589                 i = bo->surface_reg;
 590                 goto out;
 591         }
 592
 593         steal = -1;
 594         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 595
 596                 reg = &rdev->surface_regs[i];
 597                 if (!reg->bo)
 598                         break;
 599
 600                 old_object = reg->bo;
 601                 if (old_object->pin_count == 0)
 602                         steal = i;
 603         }
 604
 605         /* if we are all out */
 606         if (i == RADEON_GEM_MAX_SURFACES) {
 607                 if (steal == -1)
 608                         return -ENOMEM;
 609                 /* find someone with a surface reg and nuke their BO */
 610                 reg = &rdev->surface_regs[steal];
 611                 old_object = reg->bo;
 612                 /* blow away the mapping */
 613                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 614                 ttm_bo_unmap_virtual(&old_object->tbo);
 615                 old_object->surface_reg = -1;
 616                 i = steal;
 617         }
 618
 619         bo->surface_reg = i;
 620         reg->bo = bo;
 621
 622 out:
 623         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 624                                bo->tbo.mem.start << PAGE_SHIFT,
 625                                bo->tbo.num_pages << PAGE_SHIFT);
 626         return 0;
 627 }
 628
 629 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 630 {
 631         struct radeon_device *rdev = bo->rdev;
 632         struct radeon_surface_reg *reg;
 633
 634         if (bo->surface_reg == -1)
 635                 return;
 636
 637         reg = &rdev->surface_regs[bo->surface_reg];
 638         radeon_clear_surface_reg(rdev, bo->surface_reg);
 639
 640         reg->bo = NULL;
 641         bo->surface_reg = -1;
 642 }
 643
 644 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 645                                 uint32_t tiling_flags, uint32_t pitch)
 646 {
 647         struct radeon_device *rdev = bo->rdev;
 648         int r;
 649
 650         if (rdev->family >= CHIP_CEDAR) {
 651                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 652
 653                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 654                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 655                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 656                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 657                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 658                 switch (bankw) {
 659                 case 0:
 660                 case 1:
 661                 case 2:
 662                 case 4:
 663                 case 8:
 664                         break;
 665                 default:
 666                         return -EINVAL;
 667                 }
 668                 switch (bankh) {
 669                 case 0:
 670                 case 1:
 671                 case 2:
 672                 case 4:
 673                 case 8:
 674                         break;
 675                 default:
 676                         return -EINVAL;
 677                 }
 678                 switch (mtaspect) {
 679                 case 0:
 680                 case 1:
 681                 case 2:
 682                 case 4:
 683                 case 8:
 684                         break;
 685                 default:
 686                         return -EINVAL;
 687                 }
 688                 if (tilesplit > 6) {
 689                         return -EINVAL;
 690                 }
 691                 if (stilesplit > 6) {
 692                         return -EINVAL;
 693                 }
 694         }
 695         r = radeon_bo_reserve(bo, false);
 696         if (unlikely(r != 0))
 697                 return r;
 698         bo->tiling_flags = tiling_flags;
 699         bo->pitch = pitch;
 700         radeon_bo_unreserve(bo);
 701         return 0;
 702 }
 703
 704 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 705                                 uint32_t *tiling_flags,
 706                                 uint32_t *pitch)
 707 {
 708         lockdep_assert_held(&bo->tbo.resv->lock.base);
 709
 710         if (tiling_flags)
 711                 *tiling_flags = bo->tiling_flags;
 712         if (pitch)
 713                 *pitch = bo->pitch;
 714 }
 715
 716 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 717                                 bool force_drop)
 718 {
 719         if (!force_drop)
 720                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 721
 722         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 723                 return 0;
 724
 725         if (force_drop) {
 726                 radeon_bo_clear_surface_reg(bo);
 727                 return 0;
 728         }
 729
 730         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 731                 if (!has_moved)
 732                         return 0;
 733
 734                 if (bo->surface_reg >= 0)
 735                         radeon_bo_clear_surface_reg(bo);
 736                 return 0;
 737         }
 738
 739         if ((bo->surface_reg >= 0) && !has_moved)
 740                 return 0;
 741
 742         return radeon_bo_get_surface_reg(bo);
 743 }
 744
 745 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 746                            struct ttm_mem_reg *new_mem)
 747 {
 748         struct radeon_bo *rbo;
 749
 750         if (!radeon_ttm_bo_is_radeon_bo(bo))
 751                 return;
 752
 753         rbo = container_of(bo, struct radeon_bo, tbo);
 754         radeon_bo_check_tiling(rbo, 0, 1);
 755         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 756
 757         /* update statistics */
 758         if (!new_mem)
 759                 return;
 760
 761         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 762         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 763 }
 764
 765 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 766 {
 767         struct radeon_device *rdev;
 768         struct radeon_bo *rbo;
 769         unsigned long offset, size, lpfn;
 770         int i, r;
 771
 772         if (!radeon_ttm_bo_is_radeon_bo(bo))
 773                 return 0;
 774         rbo = container_of(bo, struct radeon_bo, tbo);
 775         radeon_bo_check_tiling(rbo, 0, 0);
 776         rdev = rbo->rdev;
 777         if (bo->mem.mem_type != TTM_PL_VRAM)
 778                 return 0;
 779
 780         size = bo->mem.num_pages << PAGE_SHIFT;
 781         offset = bo->mem.start << PAGE_SHIFT;
 782         if ((offset + size) <= rdev->mc.visible_vram_size)
 783                 return 0;
 784
 785         /* hurrah the memory is not visible ! */
 786         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 787         lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
 788         for (i = 0; i < rbo->placement.num_placement; i++) {
 789                 /* Force into visible VRAM */
 790                 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 791                     (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
 792                         rbo->placements[i].lpfn = lpfn;
 793         }
 794         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 795         if (unlikely(r == -ENOMEM)) {
 796                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 797                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 798         } else if (unlikely(r != 0)) {
 799                 return r;
 800         }
 801
 802         offset = bo->mem.start << PAGE_SHIFT;
 803         /* this should never happen */
 804         if ((offset + size) > rdev->mc.visible_vram_size)
 805                 return -EINVAL;
 806
 807         return 0;
 808 }
 809
 810 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 811 {
 812         int r;
 813
 814         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 815         if (unlikely(r != 0))
 816                 return r;
 817         if (mem_type)
 818                 *mem_type = bo->tbo.mem.mem_type;
 819
 820         r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 821         ttm_bo_unreserve(&bo->tbo);
 822         return r;
 823 }