drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_update_memory_usage(struct radeon_bo *bo,
  50                                        unsigned mem_type, int sign)
  51 {
  52         struct radeon_device *rdev = bo->rdev;
  53         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  54
  55         switch (mem_type) {
  56         case TTM_PL_TT:
  57                 if (sign > 0)
  58                         atomic64_add(size, &rdev->gtt_usage);
  59                 else
  60                         atomic64_sub(size, &rdev->gtt_usage);
  61                 break;
  62         case TTM_PL_VRAM:
  63                 if (sign > 0)
  64                         atomic64_add(size, &rdev->vram_usage);
  65                 else
  66                         atomic64_sub(size, &rdev->vram_usage);
  67                 break;
  68         }
  69 }
  70
  71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  72 {
  73         struct radeon_bo *bo;
  74
  75         bo = container_of(tbo, struct radeon_bo, tbo);
  76
  77         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  78         radeon_mn_unregister(bo);
  79
  80         mutex_lock(&bo->rdev->gem.mutex);
  81         list_del_init(&bo->list);
  82         mutex_unlock(&bo->rdev->gem.mutex);
  83         radeon_bo_clear_surface_reg(bo);
  84         WARN_ON(!list_empty(&bo->va));
  85         drm_gem_object_release(&bo->gem_base);
  86         kfree(bo);
  87 }
  88
  89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  90 {
  91         if (bo->destroy == &radeon_ttm_bo_destroy)
  92                 return true;
  93         return false;
  94 }
  95
  96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  97 {
  98         u32 c = 0, i;
  99
 100         rbo->placement.placement = rbo->placements;
 101         rbo->placement.busy_placement = rbo->placements;
 102         if (domain & RADEON_GEM_DOMAIN_VRAM)
 103                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 104                                              TTM_PL_FLAG_UNCACHED |
 105                                              TTM_PL_FLAG_VRAM;
 106
 107         if (domain & RADEON_GEM_DOMAIN_GTT) {
 108                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 109                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 110                                 TTM_PL_FLAG_TT;
 111
 112                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 113                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 114                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 115                                 TTM_PL_FLAG_UNCACHED |
 116                                 TTM_PL_FLAG_TT;
 117                 } else {
 118                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 119                                                      TTM_PL_FLAG_TT;
 120                 }
 121         }
 122
 123         if (domain & RADEON_GEM_DOMAIN_CPU) {
 124                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 125                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 126                                 TTM_PL_FLAG_SYSTEM;
 127
 128                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 129                     rbo->rdev->flags & RADEON_IS_AGP) {
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 131                                 TTM_PL_FLAG_UNCACHED |
 132                                 TTM_PL_FLAG_SYSTEM;
 133                 } else {
 134                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 135                                                      TTM_PL_FLAG_SYSTEM;
 136                 }
 137         }
 138         if (!c)
 139                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 140                                              TTM_PL_FLAG_SYSTEM;
 141
 142         rbo->placement.num_placement = c;
 143         rbo->placement.num_busy_placement = c;
 144
 145         for (i = 0; i < c; ++i) {
 146                 rbo->placements[i].fpfn = 0;
 147                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 148                     (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
 149                         rbo->placements[i].lpfn =
 150                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 151                 else
 152                         rbo->placements[i].lpfn = 0;
 153         }
 154
 155         /*
 156          * Use two-ended allocation depending on the buffer size to
 157          * improve fragmentation quality.
 158          * 512kb was measured as the most optimal number.
 159          */
 160         if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 161               (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
 162             rbo->tbo.mem.size > 512 * 1024) {
 163                 for (i = 0; i < c; i++) {
 164                         rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
 165                 }
 166         }
 167 }
 168
 169 int radeon_bo_create(struct radeon_device *rdev,
 170                      unsigned long size, int byte_align, bool kernel,
 171                      u32 domain, u32 flags, struct sg_table *sg,
 172                      struct reservation_object *resv,
 173                      struct radeon_bo **bo_ptr)
 174 {
 175         struct radeon_bo *bo;
 176         enum ttm_bo_type type;
 177         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 178         size_t acc_size;
 179         int r;
 180
 181         size = ALIGN(size, PAGE_SIZE);
 182
 183         if (kernel) {
 184                 type = ttm_bo_type_kernel;
 185         } else if (sg) {
 186                 type = ttm_bo_type_sg;
 187         } else {
 188                 type = ttm_bo_type_device;
 189         }
 190         *bo_ptr = NULL;
 191
 192         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 193                                        sizeof(struct radeon_bo));
 194
 195         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 196         if (bo == NULL)
 197                 return -ENOMEM;
 198         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 199         if (unlikely(r)) {
 200                 kfree(bo);
 201                 return r;
 202         }
 203         bo->rdev = rdev;
 204         bo->surface_reg = -1;
 205         INIT_LIST_HEAD(&bo->list);
 206         INIT_LIST_HEAD(&bo->va);
 207         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 208                                        RADEON_GEM_DOMAIN_GTT |
 209                                        RADEON_GEM_DOMAIN_CPU);
 210
 211         bo->flags = flags;
 212         /* PCI GART is always snooped */
 213         if (!(rdev->flags & RADEON_IS_PCIE))
 214                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 215
 216 #ifdef CONFIG_X86_32
 217         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 218          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 219          */
 220         bo->flags &= ~RADEON_GEM_GTT_WC;
 221 #endif
 222
 223         radeon_ttm_placement_from_domain(bo, domain);
 224         /* Kernel allocation are uninterruptible */
 225         down_read(&rdev->pm.mclk_lock);
 226         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 227                         &bo->placement, page_align, !kernel, NULL,
 228                         acc_size, sg, resv, &radeon_ttm_bo_destroy);
 229         up_read(&rdev->pm.mclk_lock);
 230         if (unlikely(r != 0)) {
 231                 return r;
 232         }
 233         *bo_ptr = bo;
 234
 235         trace_radeon_bo_create(bo);
 236
 237         return 0;
 238 }
 239
 240 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 241 {
 242         bool is_iomem;
 243         int r;
 244
 245         if (bo->kptr) {
 246                 if (ptr) {
 247                         *ptr = bo->kptr;
 248                 }
 249                 return 0;
 250         }
 251         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 252         if (r) {
 253                 return r;
 254         }
 255         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 256         if (ptr) {
 257                 *ptr = bo->kptr;
 258         }
 259         radeon_bo_check_tiling(bo, 0, 0);
 260         return 0;
 261 }
 262
 263 void radeon_bo_kunmap(struct radeon_bo *bo)
 264 {
 265         if (bo->kptr == NULL)
 266                 return;
 267         bo->kptr = NULL;
 268         radeon_bo_check_tiling(bo, 0, 0);
 269         ttm_bo_kunmap(&bo->kmap);
 270 }
 271
 272 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 273 {
 274         if (bo == NULL)
 275                 return NULL;
 276
 277         ttm_bo_reference(&bo->tbo);
 278         return bo;
 279 }
 280
 281 void radeon_bo_unref(struct radeon_bo **bo)
 282 {
 283         struct ttm_buffer_object *tbo;
 284         struct radeon_device *rdev;
 285
 286         if ((*bo) == NULL)
 287                 return;
 288         rdev = (*bo)->rdev;
 289         tbo = &((*bo)->tbo);
 290         ttm_bo_unref(&tbo);
 291         if (tbo == NULL)
 292                 *bo = NULL;
 293 }
 294
 295 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 296                              u64 *gpu_addr)
 297 {
 298         int r, i;
 299
 300         if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
 301                 return -EPERM;
 302
 303         if (bo->pin_count) {
 304                 bo->pin_count++;
 305                 if (gpu_addr)
 306                         *gpu_addr = radeon_bo_gpu_offset(bo);
 307
 308                 if (max_offset != 0) {
 309                         u64 domain_start;
 310
 311                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 312                                 domain_start = bo->rdev->mc.vram_start;
 313                         else
 314                                 domain_start = bo->rdev->mc.gtt_start;
 315                         WARN_ON_ONCE(max_offset <
 316                                      (radeon_bo_gpu_offset(bo) - domain_start));
 317                 }
 318
 319                 return 0;
 320         }
 321         radeon_ttm_placement_from_domain(bo, domain);
 322         for (i = 0; i < bo->placement.num_placement; i++) {
 323                 /* force to pin into visible video ram */
 324                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 325                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 326                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 327                         bo->placements[i].lpfn =
 328                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 329                 else
 330                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 331
 332                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 333         }
 334
 335         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 336         if (likely(r == 0)) {
 337                 bo->pin_count = 1;
 338                 if (gpu_addr != NULL)
 339                         *gpu_addr = radeon_bo_gpu_offset(bo);
 340                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 341                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 342                 else
 343                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 344         } else {
 345                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 346         }
 347         return r;
 348 }
 349
 350 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 351 {
 352         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 353 }
 354
 355 int radeon_bo_unpin(struct radeon_bo *bo)
 356 {
 357         int r, i;
 358
 359         if (!bo->pin_count) {
 360                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 361                 return 0;
 362         }
 363         bo->pin_count--;
 364         if (bo->pin_count)
 365                 return 0;
 366         for (i = 0; i < bo->placement.num_placement; i++) {
 367                 bo->placements[i].lpfn = 0;
 368                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 369         }
 370         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 371         if (likely(r == 0)) {
 372                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 373                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 374                 else
 375                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 376         } else {
 377                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 378         }
 379         return r;
 380 }
 381
 382 int radeon_bo_evict_vram(struct radeon_device *rdev)
 383 {
 384         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 385         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 386                 if (rdev->mc.igp_sideport_enabled == false)
 387                         /* Useless to evict on IGP chips */
 388                         return 0;
 389         }
 390         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 391 }
 392
 393 void radeon_bo_force_delete(struct radeon_device *rdev)
 394 {
 395         struct radeon_bo *bo, *n;
 396
 397         if (list_empty(&rdev->gem.objects)) {
 398                 return;
 399         }
 400         dev_err(rdev->dev, "Userspace still has active objects !\n");
 401         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 402                 mutex_lock(&rdev->ddev->struct_mutex);
 403                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 404                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 405                         *((unsigned long *)&bo->gem_base.refcount));
 406                 mutex_lock(&bo->rdev->gem.mutex);
 407                 list_del_init(&bo->list);
 408                 mutex_unlock(&bo->rdev->gem.mutex);
 409                 /* this should unref the ttm bo */
 410                 drm_gem_object_unreference(&bo->gem_base);
 411                 mutex_unlock(&rdev->ddev->struct_mutex);
 412         }
 413 }
 414
 415 int radeon_bo_init(struct radeon_device *rdev)
 416 {
 417         /* Add an MTRR for the VRAM */
 418         if (!rdev->fastfb_working) {
 419                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 420                                                       rdev->mc.aper_size);
 421         }
 422         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 423                 rdev->mc.mc_vram_size >> 20,
 424                 (unsigned long long)rdev->mc.aper_size >> 20);
 425         DRM_INFO("RAM width %dbits %cDR\n",
 426                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 427         return radeon_ttm_init(rdev);
 428 }
 429
 430 void radeon_bo_fini(struct radeon_device *rdev)
 431 {
 432         radeon_ttm_fini(rdev);
 433         arch_phys_wc_del(rdev->mc.vram_mtrr);
 434 }
 435
 436 /* Returns how many bytes TTM can move per IB.
 437  */
 438 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 439 {
 440         u64 real_vram_size = rdev->mc.real_vram_size;
 441         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 442
 443         /* This function is based on the current VRAM usage.
 444          *
 445          * - If all of VRAM is free, allow relocating the number of bytes that
 446          *   is equal to 1/4 of the size of VRAM for this IB.
 447
 448          * - If more than one half of VRAM is occupied, only allow relocating
 449          *   1 MB of data for this IB.
 450          *
 451          * - From 0 to one half of used VRAM, the threshold decreases
 452          *   linearly.
 453          *         __________________
 454          * 1/4 of -|\               |
 455          * VRAM    | \              |
 456          *         |  \             |
 457          *         |   \            |
 458          *         |    \           |
 459          *         |     \          |
 460          *         |      \         |
 461          *         |       \________|1 MB
 462          *         |----------------|
 463          *    VRAM 0 %             100 %
 464          *         used            used
 465          *
 466          * Note: It's a threshold, not a limit. The threshold must be crossed
 467          * for buffer relocations to stop, so any buffer of an arbitrary size
 468          * can be moved as long as the threshold isn't crossed before
 469          * the relocation takes place. We don't want to disable buffer
 470          * relocations completely.
 471          *
 472          * The idea is that buffers should be placed in VRAM at creation time
 473          * and TTM should only do a minimum number of relocations during
 474          * command submission. In practice, you need to submit at least
 475          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 476          *
 477          * Also, things can get pretty crazy under memory pressure and actual
 478          * VRAM usage can change a lot, so playing safe even at 50% does
 479          * consistently increase performance.
 480          */
 481
 482         u64 half_vram = real_vram_size >> 1;
 483         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 484         u64 bytes_moved_threshold = half_free_vram >> 1;
 485         return max(bytes_moved_threshold, 1024*1024ull);
 486 }
 487
 488 int radeon_bo_list_validate(struct radeon_device *rdev,
 489                             struct ww_acquire_ctx *ticket,
 490                             struct list_head *head, int ring)
 491 {
 492         struct radeon_cs_reloc *lobj;
 493         struct radeon_bo *bo;
 494         int r;
 495         u64 bytes_moved = 0, initial_bytes_moved;
 496         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 497
 498         r = ttm_eu_reserve_buffers(ticket, head, true);
 499         if (unlikely(r != 0)) {
 500                 return r;
 501         }
 502
 503         list_for_each_entry(lobj, head, tv.head) {
 504                 bo = lobj->robj;
 505                 if (!bo->pin_count) {
 506                         u32 domain = lobj->prefered_domains;
 507                         u32 allowed = lobj->allowed_domains;
 508                         u32 current_domain =
 509                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 510
 511                         /* Check if this buffer will be moved and don't move it
 512                          * if we have moved too many buffers for this IB already.
 513                          *
 514                          * Note that this allows moving at least one buffer of
 515                          * any size, because it doesn't take the current "bo"
 516                          * into account. We don't want to disallow buffer moves
 517                          * completely.
 518                          */
 519                         if ((allowed & current_domain) != 0 &&
 520                             (domain & current_domain) == 0 && /* will be moved */
 521                             bytes_moved > bytes_moved_threshold) {
 522                                 /* don't move it */
 523                                 domain = current_domain;
 524                         }
 525
 526                 retry:
 527                         radeon_ttm_placement_from_domain(bo, domain);
 528                         if (ring == R600_RING_TYPE_UVD_INDEX)
 529                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 530
 531                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 532                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 533                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 534                                        initial_bytes_moved;
 535
 536                         if (unlikely(r)) {
 537                                 if (r != -ERESTARTSYS &&
 538                                     domain != lobj->allowed_domains) {
 539                                         domain = lobj->allowed_domains;
 540                                         goto retry;
 541                                 }
 542                                 ttm_eu_backoff_reservation(ticket, head);
 543                                 return r;
 544                         }
 545                 }
 546                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 547                 lobj->tiling_flags = bo->tiling_flags;
 548         }
 549         return 0;
 550 }
 551
 552 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 553                              struct vm_area_struct *vma)
 554 {
 555         return ttm_fbdev_mmap(vma, &bo->tbo);
 556 }
 557
 558 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 559 {
 560         struct radeon_device *rdev = bo->rdev;
 561         struct radeon_surface_reg *reg;
 562         struct radeon_bo *old_object;
 563         int steal;
 564         int i;
 565
 566         lockdep_assert_held(&bo->tbo.resv->lock.base);
 567
 568         if (!bo->tiling_flags)
 569                 return 0;
 570
 571         if (bo->surface_reg >= 0) {
 572                 reg = &rdev->surface_regs[bo->surface_reg];
 573                 i = bo->surface_reg;
 574                 goto out;
 575         }
 576
 577         steal = -1;
 578         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 579
 580                 reg = &rdev->surface_regs[i];
 581                 if (!reg->bo)
 582                         break;
 583
 584                 old_object = reg->bo;
 585                 if (old_object->pin_count == 0)
 586                         steal = i;
 587         }
 588
 589         /* if we are all out */
 590         if (i == RADEON_GEM_MAX_SURFACES) {
 591                 if (steal == -1)
 592                         return -ENOMEM;
 593                 /* find someone with a surface reg and nuke their BO */
 594                 reg = &rdev->surface_regs[steal];
 595                 old_object = reg->bo;
 596                 /* blow away the mapping */
 597                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 598                 ttm_bo_unmap_virtual(&old_object->tbo);
 599                 old_object->surface_reg = -1;
 600                 i = steal;
 601         }
 602
 603         bo->surface_reg = i;
 604         reg->bo = bo;
 605
 606 out:
 607         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 608                                bo->tbo.mem.start << PAGE_SHIFT,
 609                                bo->tbo.num_pages << PAGE_SHIFT);
 610         return 0;
 611 }
 612
 613 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 614 {
 615         struct radeon_device *rdev = bo->rdev;
 616         struct radeon_surface_reg *reg;
 617
 618         if (bo->surface_reg == -1)
 619                 return;
 620
 621         reg = &rdev->surface_regs[bo->surface_reg];
 622         radeon_clear_surface_reg(rdev, bo->surface_reg);
 623
 624         reg->bo = NULL;
 625         bo->surface_reg = -1;
 626 }
 627
 628 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 629                                 uint32_t tiling_flags, uint32_t pitch)
 630 {
 631         struct radeon_device *rdev = bo->rdev;
 632         int r;
 633
 634         if (rdev->family >= CHIP_CEDAR) {
 635                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 636
 637                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 638                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 639                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 640                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 641                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 642                 switch (bankw) {
 643                 case 0:
 644                 case 1:
 645                 case 2:
 646                 case 4:
 647                 case 8:
 648                         break;
 649                 default:
 650                         return -EINVAL;
 651                 }
 652                 switch (bankh) {
 653                 case 0:
 654                 case 1:
 655                 case 2:
 656                 case 4:
 657                 case 8:
 658                         break;
 659                 default:
 660                         return -EINVAL;
 661                 }
 662                 switch (mtaspect) {
 663                 case 0:
 664                 case 1:
 665                 case 2:
 666                 case 4:
 667                 case 8:
 668                         break;
 669                 default:
 670                         return -EINVAL;
 671                 }
 672                 if (tilesplit > 6) {
 673                         return -EINVAL;
 674                 }
 675                 if (stilesplit > 6) {
 676                         return -EINVAL;
 677                 }
 678         }
 679         r = radeon_bo_reserve(bo, false);
 680         if (unlikely(r != 0))
 681                 return r;
 682         bo->tiling_flags = tiling_flags;
 683         bo->pitch = pitch;
 684         radeon_bo_unreserve(bo);
 685         return 0;
 686 }
 687
 688 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 689                                 uint32_t *tiling_flags,
 690                                 uint32_t *pitch)
 691 {
 692         lockdep_assert_held(&bo->tbo.resv->lock.base);
 693
 694         if (tiling_flags)
 695                 *tiling_flags = bo->tiling_flags;
 696         if (pitch)
 697                 *pitch = bo->pitch;
 698 }
 699
 700 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 701                                 bool force_drop)
 702 {
 703         if (!force_drop)
 704                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 705
 706         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 707                 return 0;
 708
 709         if (force_drop) {
 710                 radeon_bo_clear_surface_reg(bo);
 711                 return 0;
 712         }
 713
 714         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 715                 if (!has_moved)
 716                         return 0;
 717
 718                 if (bo->surface_reg >= 0)
 719                         radeon_bo_clear_surface_reg(bo);
 720                 return 0;
 721         }
 722
 723         if ((bo->surface_reg >= 0) && !has_moved)
 724                 return 0;
 725
 726         return radeon_bo_get_surface_reg(bo);
 727 }
 728
 729 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 730                            struct ttm_mem_reg *new_mem)
 731 {
 732         struct radeon_bo *rbo;
 733
 734         if (!radeon_ttm_bo_is_radeon_bo(bo))
 735                 return;
 736
 737         rbo = container_of(bo, struct radeon_bo, tbo);
 738         radeon_bo_check_tiling(rbo, 0, 1);
 739         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 740
 741         /* update statistics */
 742         if (!new_mem)
 743                 return;
 744
 745         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 746         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 747 }
 748
 749 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 750 {
 751         struct radeon_device *rdev;
 752         struct radeon_bo *rbo;
 753         unsigned long offset, size;
 754         int r;
 755
 756         if (!radeon_ttm_bo_is_radeon_bo(bo))
 757                 return 0;
 758         rbo = container_of(bo, struct radeon_bo, tbo);
 759         radeon_bo_check_tiling(rbo, 0, 0);
 760         rdev = rbo->rdev;
 761         if (bo->mem.mem_type != TTM_PL_VRAM)
 762                 return 0;
 763
 764         size = bo->mem.num_pages << PAGE_SHIFT;
 765         offset = bo->mem.start << PAGE_SHIFT;
 766         if ((offset + size) <= rdev->mc.visible_vram_size)
 767                 return 0;
 768
 769         /* hurrah the memory is not visible ! */
 770         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 771         rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 772         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 773         if (unlikely(r == -ENOMEM)) {
 774                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 775                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 776         } else if (unlikely(r != 0)) {
 777                 return r;
 778         }
 779
 780         offset = bo->mem.start << PAGE_SHIFT;
 781         /* this should never happen */
 782         if ((offset + size) > rdev->mc.visible_vram_size)
 783                 return -EINVAL;
 784
 785         return 0;
 786 }
 787
 788 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 789 {
 790         int r;
 791
 792         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 793         if (unlikely(r != 0))
 794                 return r;
 795         if (mem_type)
 796                 *mem_type = bo->tbo.mem.mem_type;
 797
 798         r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 799         ttm_bo_unreserve(&bo->tbo);
 800         return r;
 801 }