drivers/gpu/drm/radeon/radeon_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/radeon_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "radeon_reg.h"
  46 #include "radeon.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  52
  53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  54 {
  55         struct radeon_mman *mman;
  56         struct radeon_device *rdev;
  57
  58         mman = container_of(bdev, struct radeon_mman, bdev);
  59         rdev = container_of(mman, struct radeon_device, mman);
  60         return rdev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int radeon_ttm_global_init(struct radeon_device *rdev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         int r;
  81
  82         rdev->mman.mem_global_referenced = false;
  83         global_ref = &rdev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &radeon_ttm_mem_global_init;
  87         global_ref->release = &radeon_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r != 0) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 return r;
  93         }
  94
  95         rdev->mman.bo_global_ref.mem_glob =
  96                 rdev->mman.mem_global_ref.object;
  97         global_ref = &rdev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r != 0) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 106                 return r;
 107         }
 108
 109         rdev->mman.mem_global_referenced = true;
 110         return 0;
 111 }
 112
 113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 114 {
 115         if (rdev->mman.mem_global_referenced) {
 116                 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 117                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 118                 rdev->mman.mem_global_referenced = false;
 119         }
 120 }
 121
 122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123 {
 124         return 0;
 125 }
 126
 127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                 struct ttm_mem_type_manager *man)
 129 {
 130         struct radeon_device *rdev;
 131
 132         rdev = radeon_get_rdev(bdev);
 133
 134         switch (type) {
 135         case TTM_PL_SYSTEM:
 136                 /* System memory */
 137                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                 man->available_caching = TTM_PL_MASK_CACHING;
 139                 man->default_caching = TTM_PL_FLAG_CACHED;
 140                 break;
 141         case TTM_PL_TT:
 142                 man->func = &ttm_bo_manager_func;
 143                 man->gpu_offset = rdev->mc.gtt_start;
 144                 man->available_caching = TTM_PL_MASK_CACHING;
 145                 man->default_caching = TTM_PL_FLAG_CACHED;
 146                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147 #if IS_ENABLED(CONFIG_AGP)
 148                 if (rdev->flags & RADEON_IS_AGP) {
 149                         if (!rdev->ddev->agp) {
 150                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 151                                           (unsigned)type);
 152                                 return -EINVAL;
 153                         }
 154                         if (!rdev->ddev->agp->cant_use_aperture)
 155                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 157                                                  TTM_PL_FLAG_WC;
 158                         man->default_caching = TTM_PL_FLAG_WC;
 159                 }
 160 #endif
 161                 break;
 162         case TTM_PL_VRAM:
 163                 /* "On-card" video ram */
 164                 man->func = &ttm_bo_manager_func;
 165                 man->gpu_offset = rdev->mc.vram_start;
 166                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 167                              TTM_MEMTYPE_FLAG_MAPPABLE;
 168                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 169                 man->default_caching = TTM_PL_FLAG_WC;
 170                 break;
 171         default:
 172                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 173                 return -EINVAL;
 174         }
 175         return 0;
 176 }
 177
 178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
 179                                 struct ttm_placement *placement)
 180 {
 181         static struct ttm_place placements = {
 182                 .fpfn = 0,
 183                 .lpfn = 0,
 184                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 185         };
 186
 187         struct radeon_bo *rbo;
 188
 189         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 190                 placement->placement = &placements;
 191                 placement->busy_placement = &placements;
 192                 placement->num_placement = 1;
 193                 placement->num_busy_placement = 1;
 194                 return;
 195         }
 196         rbo = container_of(bo, struct radeon_bo, tbo);
 197         switch (bo->mem.mem_type) {
 198         case TTM_PL_VRAM:
 199                 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 200                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 201                 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
 202                          bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
 203                         unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 204                         int i;
 205
 206                         /* Try evicting to the CPU inaccessible part of VRAM
 207                          * first, but only set GTT as busy placement, so this
 208                          * BO will be evicted to GTT rather than causing other
 209                          * BOs to be evicted from VRAM
 210                          */
 211                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
 212                                                          RADEON_GEM_DOMAIN_GTT);
 213                         rbo->placement.num_busy_placement = 0;
 214                         for (i = 0; i < rbo->placement.num_placement; i++) {
 215                                 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
 216                                         if (rbo->placements[0].fpfn < fpfn)
 217                                                 rbo->placements[0].fpfn = fpfn;
 218                                 } else {
 219                                         rbo->placement.busy_placement =
 220                                                 &rbo->placements[i];
 221                                         rbo->placement.num_busy_placement = 1;
 222                                 }
 223                         }
 224                 } else
 225                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 226                 break;
 227         case TTM_PL_TT:
 228         default:
 229                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 230         }
 231         *placement = rbo->placement;
 232 }
 233
 234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 235 {
 236         struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 237
 238         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 239 }
 240
 241 static void radeon_move_null(struct ttm_buffer_object *bo,
 242                              struct ttm_mem_reg *new_mem)
 243 {
 244         struct ttm_mem_reg *old_mem = &bo->mem;
 245
 246         BUG_ON(old_mem->mm_node != NULL);
 247         *old_mem = *new_mem;
 248         new_mem->mm_node = NULL;
 249 }
 250
 251 static int radeon_move_blit(struct ttm_buffer_object *bo,
 252                         bool evict, bool no_wait_gpu,
 253                         struct ttm_mem_reg *new_mem,
 254                         struct ttm_mem_reg *old_mem)
 255 {
 256         struct radeon_device *rdev;
 257         uint64_t old_start, new_start;
 258         struct radeon_fence *fence;
 259         unsigned num_pages;
 260         int r, ridx;
 261
 262         rdev = radeon_get_rdev(bo->bdev);
 263         ridx = radeon_copy_ring_index(rdev);
 264         old_start = old_mem->start << PAGE_SHIFT;
 265         new_start = new_mem->start << PAGE_SHIFT;
 266
 267         switch (old_mem->mem_type) {
 268         case TTM_PL_VRAM:
 269                 old_start += rdev->mc.vram_start;
 270                 break;
 271         case TTM_PL_TT:
 272                 old_start += rdev->mc.gtt_start;
 273                 break;
 274         default:
 275                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 276                 return -EINVAL;
 277         }
 278         switch (new_mem->mem_type) {
 279         case TTM_PL_VRAM:
 280                 new_start += rdev->mc.vram_start;
 281                 break;
 282         case TTM_PL_TT:
 283                 new_start += rdev->mc.gtt_start;
 284                 break;
 285         default:
 286                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 287                 return -EINVAL;
 288         }
 289         if (!rdev->ring[ridx].ready) {
 290                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 291                 return -EINVAL;
 292         }
 293
 294         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 295
 296         num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 297         fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
 298         if (IS_ERR(fence))
 299                 return PTR_ERR(fence);
 300
 301         r = ttm_bo_move_accel_cleanup(bo, &fence->base,
 302                                       evict, no_wait_gpu, new_mem);
 303         radeon_fence_unref(&fence);
 304         return r;
 305 }
 306
 307 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 308                                 bool evict, bool interruptible,
 309                                 bool no_wait_gpu,
 310                                 struct ttm_mem_reg *new_mem)
 311 {
 312         struct radeon_device *rdev;
 313         struct ttm_mem_reg *old_mem = &bo->mem;
 314         struct ttm_mem_reg tmp_mem;
 315         struct ttm_place placements;
 316         struct ttm_placement placement;
 317         int r;
 318
 319         rdev = radeon_get_rdev(bo->bdev);
 320         tmp_mem = *new_mem;
 321         tmp_mem.mm_node = NULL;
 322         placement.num_placement = 1;
 323         placement.placement = &placements;
 324         placement.num_busy_placement = 1;
 325         placement.busy_placement = &placements;
 326         placements.fpfn = 0;
 327         placements.lpfn = 0;
 328         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 329         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 330                              interruptible, no_wait_gpu);
 331         if (unlikely(r)) {
 332                 return r;
 333         }
 334
 335         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 336         if (unlikely(r)) {
 337                 goto out_cleanup;
 338         }
 339
 340         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 341         if (unlikely(r)) {
 342                 goto out_cleanup;
 343         }
 344         r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 345         if (unlikely(r)) {
 346                 goto out_cleanup;
 347         }
 348         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 349 out_cleanup:
 350         ttm_bo_mem_put(bo, &tmp_mem);
 351         return r;
 352 }
 353
 354 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 355                                 bool evict, bool interruptible,
 356                                 bool no_wait_gpu,
 357                                 struct ttm_mem_reg *new_mem)
 358 {
 359         struct radeon_device *rdev;
 360         struct ttm_mem_reg *old_mem = &bo->mem;
 361         struct ttm_mem_reg tmp_mem;
 362         struct ttm_placement placement;
 363         struct ttm_place placements;
 364         int r;
 365
 366         rdev = radeon_get_rdev(bo->bdev);
 367         tmp_mem = *new_mem;
 368         tmp_mem.mm_node = NULL;
 369         placement.num_placement = 1;
 370         placement.placement = &placements;
 371         placement.num_busy_placement = 1;
 372         placement.busy_placement = &placements;
 373         placements.fpfn = 0;
 374         placements.lpfn = 0;
 375         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 376         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 377                              interruptible, no_wait_gpu);
 378         if (unlikely(r)) {
 379                 return r;
 380         }
 381         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 382         if (unlikely(r)) {
 383                 goto out_cleanup;
 384         }
 385         r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 386         if (unlikely(r)) {
 387                 goto out_cleanup;
 388         }
 389 out_cleanup:
 390         ttm_bo_mem_put(bo, &tmp_mem);
 391         return r;
 392 }
 393
 394 static int radeon_bo_move(struct ttm_buffer_object *bo,
 395                         bool evict, bool interruptible,
 396                         bool no_wait_gpu,
 397                         struct ttm_mem_reg *new_mem)
 398 {
 399         struct radeon_device *rdev;
 400         struct ttm_mem_reg *old_mem = &bo->mem;
 401         int r;
 402
 403         rdev = radeon_get_rdev(bo->bdev);
 404         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 405                 radeon_move_null(bo, new_mem);
 406                 return 0;
 407         }
 408         if ((old_mem->mem_type == TTM_PL_TT &&
 409              new_mem->mem_type == TTM_PL_SYSTEM) ||
 410             (old_mem->mem_type == TTM_PL_SYSTEM &&
 411              new_mem->mem_type == TTM_PL_TT)) {
 412                 /* bind is enough */
 413                 radeon_move_null(bo, new_mem);
 414                 return 0;
 415         }
 416         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 417             rdev->asic->copy.copy == NULL) {
 418                 /* use memcpy */
 419                 goto memcpy;
 420         }
 421
 422         if (old_mem->mem_type == TTM_PL_VRAM &&
 423             new_mem->mem_type == TTM_PL_SYSTEM) {
 424                 r = radeon_move_vram_ram(bo, evict, interruptible,
 425                                         no_wait_gpu, new_mem);
 426         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 427                    new_mem->mem_type == TTM_PL_VRAM) {
 428                 r = radeon_move_ram_vram(bo, evict, interruptible,
 429                                             no_wait_gpu, new_mem);
 430         } else {
 431                 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 432         }
 433
 434         if (r) {
 435 memcpy:
 436                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 437                 if (r) {
 438                         return r;
 439                 }
 440         }
 441
 442         /* update statistics */
 443         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
 444         return 0;
 445 }
 446
 447 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 448 {
 449         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 450         struct radeon_device *rdev = radeon_get_rdev(bdev);
 451
 452         mem->bus.addr = NULL;
 453         mem->bus.offset = 0;
 454         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 455         mem->bus.base = 0;
 456         mem->bus.is_iomem = false;
 457         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 458                 return -EINVAL;
 459         switch (mem->mem_type) {
 460         case TTM_PL_SYSTEM:
 461                 /* system memory */
 462                 return 0;
 463         case TTM_PL_TT:
 464 #if IS_ENABLED(CONFIG_AGP)
 465                 if (rdev->flags & RADEON_IS_AGP) {
 466                         /* RADEON_IS_AGP is set only if AGP is active */
 467                         mem->bus.offset = mem->start << PAGE_SHIFT;
 468                         mem->bus.base = rdev->mc.agp_base;
 469                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 470                 }
 471 #endif
 472                 break;
 473         case TTM_PL_VRAM:
 474                 mem->bus.offset = mem->start << PAGE_SHIFT;
 475                 /* check if it's visible */
 476                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 477                         return -EINVAL;
 478                 mem->bus.base = rdev->mc.aper_base;
 479                 mem->bus.is_iomem = true;
 480 #ifdef __alpha__
 481                 /*
 482                  * Alpha: use bus.addr to hold the ioremap() return,
 483                  * so we can modify bus.base below.
 484                  */
 485                 if (mem->placement & TTM_PL_FLAG_WC)
 486                         mem->bus.addr =
 487                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 488                                            mem->bus.size);
 489                 else
 490                         mem->bus.addr =
 491                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 492                                                 mem->bus.size);
 493
 494                 /*
 495                  * Alpha: Use just the bus offset plus
 496                  * the hose/domain memory base for bus.base.
 497                  * It then can be used to build PTEs for VRAM
 498                  * access, as done in ttm_bo_vm_fault().
 499                  */
 500                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 501                         rdev->ddev->hose->dense_mem_base;
 502 #endif
 503                 break;
 504         default:
 505                 return -EINVAL;
 506         }
 507         return 0;
 508 }
 509
 510 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 511 {
 512 }
 513
 514 /*
 515  * TTM backend functions.
 516  */
 517 struct radeon_ttm_tt {
 518         struct ttm_dma_tt               ttm;
 519         struct radeon_device            *rdev;
 520         u64                             offset;
 521
 522         uint64_t                        userptr;
 523         struct mm_struct                *usermm;
 524         uint32_t                        userflags;
 525 };
 526
 527 /* prepare the sg table with the user pages */
 528 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 529 {
 530         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 531         struct radeon_ttm_tt *gtt = (void *)ttm;
 532         unsigned pinned = 0, nents;
 533         int r;
 534
 535         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 536         enum dma_data_direction direction = write ?
 537                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 538
 539         if (current->mm != gtt->usermm)
 540                 return -EPERM;
 541
 542         if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
 543                 /* check that we only pin down anonymous memory
 544                    to prevent problems with writeback */
 545                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 546                 struct vm_area_struct *vma;
 547                 vma = find_vma(gtt->usermm, gtt->userptr);
 548                 if (!vma || vma->vm_file || vma->vm_end < end)
 549                         return -EPERM;
 550         }
 551
 552         do {
 553                 unsigned num_pages = ttm->num_pages - pinned;
 554                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 555                 struct page **pages = ttm->pages + pinned;
 556
 557                 r = get_user_pages(userptr, num_pages, write, 0, pages, NULL);
 558                 if (r < 0)
 559                         goto release_pages;
 560
 561                 pinned += r;
 562
 563         } while (pinned < ttm->num_pages);
 564
 565         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 566                                       ttm->num_pages << PAGE_SHIFT,
 567                                       GFP_KERNEL);
 568         if (r)
 569                 goto release_sg;
 570
 571         r = -ENOMEM;
 572         nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 573         if (nents != ttm->sg->nents)
 574                 goto release_sg;
 575
 576         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 577                                          gtt->ttm.dma_address, ttm->num_pages);
 578
 579         return 0;
 580
 581 release_sg:
 582         kfree(ttm->sg);
 583
 584 release_pages:
 585         release_pages(ttm->pages, pinned, 0);
 586         return r;
 587 }
 588
 589 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 590 {
 591         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 592         struct radeon_ttm_tt *gtt = (void *)ttm;
 593         struct sg_page_iter sg_iter;
 594
 595         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 596         enum dma_data_direction direction = write ?
 597                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 598
 599         /* double check that we don't free the table twice */
 600         if (!ttm->sg->sgl)
 601                 return;
 602
 603         /* free the sg table and pages again */
 604         dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 605
 606         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 607                 struct page *page = sg_page_iter_page(&sg_iter);
 608                 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
 609                         set_page_dirty(page);
 610
 611                 mark_page_accessed(page);
 612                 page_cache_release(page);
 613         }
 614
 615         sg_free_table(ttm->sg);
 616 }
 617
 618 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 619                                    struct ttm_mem_reg *bo_mem)
 620 {
 621         struct radeon_ttm_tt *gtt = (void*)ttm;
 622         uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
 623                 RADEON_GART_PAGE_WRITE;
 624         int r;
 625
 626         if (gtt->userptr) {
 627                 radeon_ttm_tt_pin_userptr(ttm);
 628                 flags &= ~RADEON_GART_PAGE_WRITE;
 629         }
 630
 631         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 632         if (!ttm->num_pages) {
 633                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 634                      ttm->num_pages, bo_mem, ttm);
 635         }
 636         if (ttm->caching_state == tt_cached)
 637                 flags |= RADEON_GART_PAGE_SNOOP;
 638         r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
 639                              ttm->pages, gtt->ttm.dma_address, flags);
 640         if (r) {
 641                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 642                           ttm->num_pages, (unsigned)gtt->offset);
 643                 return r;
 644         }
 645         return 0;
 646 }
 647
 648 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 649 {
 650         struct radeon_ttm_tt *gtt = (void *)ttm;
 651
 652         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 653
 654         if (gtt->userptr)
 655                 radeon_ttm_tt_unpin_userptr(ttm);
 656
 657         return 0;
 658 }
 659
 660 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 661 {
 662         struct radeon_ttm_tt *gtt = (void *)ttm;
 663
 664         ttm_dma_tt_fini(&gtt->ttm);
 665         kfree(gtt);
 666 }
 667
 668 static struct ttm_backend_func radeon_backend_func = {
 669         .bind = &radeon_ttm_backend_bind,
 670         .unbind = &radeon_ttm_backend_unbind,
 671         .destroy = &radeon_ttm_backend_destroy,
 672 };
 673
 674 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 675                                     unsigned long size, uint32_t page_flags,
 676                                     struct page *dummy_read_page)
 677 {
 678         struct radeon_device *rdev;
 679         struct radeon_ttm_tt *gtt;
 680
 681         rdev = radeon_get_rdev(bdev);
 682 #if IS_ENABLED(CONFIG_AGP)
 683         if (rdev->flags & RADEON_IS_AGP) {
 684                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
 685                                          size, page_flags, dummy_read_page);
 686         }
 687 #endif
 688
 689         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 690         if (gtt == NULL) {
 691                 return NULL;
 692         }
 693         gtt->ttm.ttm.func = &radeon_backend_func;
 694         gtt->rdev = rdev;
 695         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 696                 kfree(gtt);
 697                 return NULL;
 698         }
 699         return &gtt->ttm.ttm;
 700 }
 701
 702 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
 703 {
 704         if (!ttm || ttm->func != &radeon_backend_func)
 705                 return NULL;
 706         return (struct radeon_ttm_tt *)ttm;
 707 }
 708
 709 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
 710 {
 711         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 712         struct radeon_device *rdev;
 713         unsigned i;
 714         int r;
 715         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 716
 717         if (ttm->state != tt_unpopulated)
 718                 return 0;
 719
 720         if (gtt && gtt->userptr) {
 721                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 722                 if (!ttm->sg)
 723                         return -ENOMEM;
 724
 725                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 726                 ttm->state = tt_unbound;
 727                 return 0;
 728         }
 729
 730         if (slave && ttm->sg) {
 731                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 732                                                  gtt->ttm.dma_address, ttm->num_pages);
 733                 ttm->state = tt_unbound;
 734                 return 0;
 735         }
 736
 737         rdev = radeon_get_rdev(ttm->bdev);
 738 #if IS_ENABLED(CONFIG_AGP)
 739         if (rdev->flags & RADEON_IS_AGP) {
 740                 return ttm_agp_tt_populate(ttm);
 741         }
 742 #endif
 743
 744 #ifdef CONFIG_SWIOTLB
 745         if (swiotlb_nr_tbl()) {
 746                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
 747         }
 748 #endif
 749
 750         r = ttm_pool_populate(ttm);
 751         if (r) {
 752                 return r;
 753         }
 754
 755         for (i = 0; i < ttm->num_pages; i++) {
 756                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
 757                                                        0, PAGE_SIZE,
 758                                                        PCI_DMA_BIDIRECTIONAL);
 759                 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
 760                         while (--i) {
 761                                 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 762                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 763                                 gtt->ttm.dma_address[i] = 0;
 764                         }
 765                         ttm_pool_unpopulate(ttm);
 766                         return -EFAULT;
 767                 }
 768         }
 769         return 0;
 770 }
 771
 772 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 773 {
 774         struct radeon_device *rdev;
 775         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 776         unsigned i;
 777         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 778
 779         if (gtt && gtt->userptr) {
 780                 kfree(ttm->sg);
 781                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 782                 return;
 783         }
 784
 785         if (slave)
 786                 return;
 787
 788         rdev = radeon_get_rdev(ttm->bdev);
 789 #if IS_ENABLED(CONFIG_AGP)
 790         if (rdev->flags & RADEON_IS_AGP) {
 791                 ttm_agp_tt_unpopulate(ttm);
 792                 return;
 793         }
 794 #endif
 795
 796 #ifdef CONFIG_SWIOTLB
 797         if (swiotlb_nr_tbl()) {
 798                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 799                 return;
 800         }
 801 #endif
 802
 803         for (i = 0; i < ttm->num_pages; i++) {
 804                 if (gtt->ttm.dma_address[i]) {
 805                         pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 806                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 807                 }
 808         }
 809
 810         ttm_pool_unpopulate(ttm);
 811 }
 812
 813 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 814                               uint32_t flags)
 815 {
 816         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 817
 818         if (gtt == NULL)
 819                 return -EINVAL;
 820
 821         gtt->userptr = addr;
 822         gtt->usermm = current->mm;
 823         gtt->userflags = flags;
 824         return 0;
 825 }
 826
 827 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
 828 {
 829         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 830
 831         if (gtt == NULL)
 832                 return false;
 833
 834         return !!gtt->userptr;
 835 }
 836
 837 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
 838 {
 839         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 840
 841         if (gtt == NULL)
 842                 return false;
 843
 844         return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 845 }
 846
 847 static struct ttm_bo_driver radeon_bo_driver = {
 848         .ttm_tt_create = &radeon_ttm_tt_create,
 849         .ttm_tt_populate = &radeon_ttm_tt_populate,
 850         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 851         .invalidate_caches = &radeon_invalidate_caches,
 852         .init_mem_type = &radeon_init_mem_type,
 853         .evict_flags = &radeon_evict_flags,
 854         .move = &radeon_bo_move,
 855         .verify_access = &radeon_verify_access,
 856         .move_notify = &radeon_bo_move_notify,
 857         .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 858         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 859         .io_mem_free = &radeon_ttm_io_mem_free,
 860 };
 861
 862 int radeon_ttm_init(struct radeon_device *rdev)
 863 {
 864         int r;
 865
 866         r = radeon_ttm_global_init(rdev);
 867         if (r) {
 868                 return r;
 869         }
 870         /* No others user of address space so set it to 0 */
 871         r = ttm_bo_device_init(&rdev->mman.bdev,
 872                                rdev->mman.bo_global_ref.ref.object,
 873                                &radeon_bo_driver,
 874                                rdev->ddev->anon_inode->i_mapping,
 875                                DRM_FILE_PAGE_OFFSET,
 876                                rdev->need_dma32);
 877         if (r) {
 878                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 879                 return r;
 880         }
 881         rdev->mman.initialized = true;
 882         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 883                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
 884         if (r) {
 885                 DRM_ERROR("Failed initializing VRAM heap.\n");
 886                 return r;
 887         }
 888         /* Change the size here instead of the init above so only lpfn is affected */
 889         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 890
 891         r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 892                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 893                              NULL, &rdev->stollen_vga_memory);
 894         if (r) {
 895                 return r;
 896         }
 897         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 898         if (r)
 899                 return r;
 900         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 901         radeon_bo_unreserve(rdev->stollen_vga_memory);
 902         if (r) {
 903                 radeon_bo_unref(&rdev->stollen_vga_memory);
 904                 return r;
 905         }
 906         DRM_INFO("radeon: %uM of VRAM memory ready\n",
 907                  (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
 908         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 909                                 rdev->mc.gtt_size >> PAGE_SHIFT);
 910         if (r) {
 911                 DRM_ERROR("Failed initializing GTT heap.\n");
 912                 return r;
 913         }
 914         DRM_INFO("radeon: %uM of GTT memory ready.\n",
 915                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 916
 917         r = radeon_ttm_debugfs_init(rdev);
 918         if (r) {
 919                 DRM_ERROR("Failed to init debugfs\n");
 920                 return r;
 921         }
 922         return 0;
 923 }
 924
 925 void radeon_ttm_fini(struct radeon_device *rdev)
 926 {
 927         int r;
 928
 929         if (!rdev->mman.initialized)
 930                 return;
 931         radeon_ttm_debugfs_fini(rdev);
 932         if (rdev->stollen_vga_memory) {
 933                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 934                 if (r == 0) {
 935                         radeon_bo_unpin(rdev->stollen_vga_memory);
 936                         radeon_bo_unreserve(rdev->stollen_vga_memory);
 937                 }
 938                 radeon_bo_unref(&rdev->stollen_vga_memory);
 939         }
 940         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 941         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 942         ttm_bo_device_release(&rdev->mman.bdev);
 943         radeon_gart_fini(rdev);
 944         radeon_ttm_global_fini(rdev);
 945         rdev->mman.initialized = false;
 946         DRM_INFO("radeon: ttm finalized\n");
 947 }
 948
 949 /* this should only be called at bootup or when userspace
 950  * isn't running */
 951 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 952 {
 953         struct ttm_mem_type_manager *man;
 954
 955         if (!rdev->mman.initialized)
 956                 return;
 957
 958         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 959         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 960         man->size = size >> PAGE_SHIFT;
 961 }
 962
 963 static struct vm_operations_struct radeon_ttm_vm_ops;
 964 static const struct vm_operations_struct *ttm_vm_ops = NULL;
 965
 966 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 967 {
 968         struct ttm_buffer_object *bo;
 969         struct radeon_device *rdev;
 970         int r;
 971
 972         bo = (struct ttm_buffer_object *)vma->vm_private_data;
 973         if (bo == NULL) {
 974                 return VM_FAULT_NOPAGE;
 975         }
 976         rdev = radeon_get_rdev(bo->bdev);
 977         down_read(&rdev->pm.mclk_lock);
 978         r = ttm_vm_ops->fault(vma, vmf);
 979         up_read(&rdev->pm.mclk_lock);
 980         return r;
 981 }
 982
 983 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
 984 {
 985         struct drm_file *file_priv;
 986         struct radeon_device *rdev;
 987         int r;
 988
 989         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
 990                 return -EINVAL;
 991         }
 992
 993         file_priv = filp->private_data;
 994         rdev = file_priv->minor->dev->dev_private;
 995         if (rdev == NULL) {
 996                 return -EINVAL;
 997         }
 998         r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
 999         if (unlikely(r != 0)) {
1000                 return r;
1001         }
1002         if (unlikely(ttm_vm_ops == NULL)) {
1003                 ttm_vm_ops = vma->vm_ops;
1004                 radeon_ttm_vm_ops = *ttm_vm_ops;
1005                 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1006         }
1007         vma->vm_ops = &radeon_ttm_vm_ops;
1008         return 0;
1009 }
1010
1011 #if defined(CONFIG_DEBUG_FS)
1012
1013 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1014 {
1015         struct drm_info_node *node = (struct drm_info_node *)m->private;
1016         unsigned ttm_pl = *(int *)node->info_ent->data;
1017         struct drm_device *dev = node->minor->dev;
1018         struct radeon_device *rdev = dev->dev_private;
1019         struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1020         int ret;
1021         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1022
1023         spin_lock(&glob->lru_lock);
1024         ret = drm_mm_dump_table(m, mm);
1025         spin_unlock(&glob->lru_lock);
1026         return ret;
1027 }
1028
1029 static int ttm_pl_vram = TTM_PL_VRAM;
1030 static int ttm_pl_tt = TTM_PL_TT;
1031
1032 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1033         {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1034         {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1035         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1036 #ifdef CONFIG_SWIOTLB
1037         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1038 #endif
1039 };
1040
1041 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1042 {
1043         struct radeon_device *rdev = inode->i_private;
1044         i_size_write(inode, rdev->mc.mc_vram_size);
1045         filep->private_data = inode->i_private;
1046         return 0;
1047 }
1048
1049 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1050                                     size_t size, loff_t *pos)
1051 {
1052         struct radeon_device *rdev = f->private_data;
1053         ssize_t result = 0;
1054         int r;
1055
1056         if (size & 0x3 || *pos & 0x3)
1057                 return -EINVAL;
1058
1059         while (size) {
1060                 unsigned long flags;
1061                 uint32_t value;
1062
1063                 if (*pos >= rdev->mc.mc_vram_size)
1064                         return result;
1065
1066                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1067                 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1068                 if (rdev->family >= CHIP_CEDAR)
1069                         WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1070                 value = RREG32(RADEON_MM_DATA);
1071                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1072
1073                 r = put_user(value, (uint32_t *)buf);
1074                 if (r)
1075                         return r;
1076
1077                 result += 4;
1078                 buf += 4;
1079                 *pos += 4;
1080                 size -= 4;
1081         }
1082
1083         return result;
1084 }
1085
1086 static const struct file_operations radeon_ttm_vram_fops = {
1087         .owner = THIS_MODULE,
1088         .open = radeon_ttm_vram_open,
1089         .read = radeon_ttm_vram_read,
1090         .llseek = default_llseek
1091 };
1092
1093 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1094 {
1095         struct radeon_device *rdev = inode->i_private;
1096         i_size_write(inode, rdev->mc.gtt_size);
1097         filep->private_data = inode->i_private;
1098         return 0;
1099 }
1100
1101 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1102                                    size_t size, loff_t *pos)
1103 {
1104         struct radeon_device *rdev = f->private_data;
1105         ssize_t result = 0;
1106         int r;
1107
1108         while (size) {
1109                 loff_t p = *pos / PAGE_SIZE;
1110                 unsigned off = *pos & ~PAGE_MASK;
1111                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1112                 struct page *page;
1113                 void *ptr;
1114
1115                 if (p >= rdev->gart.num_cpu_pages)
1116                         return result;
1117
1118                 page = rdev->gart.pages[p];
1119                 if (page) {
1120                         ptr = kmap(page);
1121                         ptr += off;
1122
1123                         r = copy_to_user(buf, ptr, cur_size);
1124                         kunmap(rdev->gart.pages[p]);
1125                 } else
1126                         r = clear_user(buf, cur_size);
1127
1128                 if (r)
1129                         return -EFAULT;
1130
1131                 result += cur_size;
1132                 buf += cur_size;
1133                 *pos += cur_size;
1134                 size -= cur_size;
1135         }
1136
1137         return result;
1138 }
1139
1140 static const struct file_operations radeon_ttm_gtt_fops = {
1141         .owner = THIS_MODULE,
1142         .open = radeon_ttm_gtt_open,
1143         .read = radeon_ttm_gtt_read,
1144         .llseek = default_llseek
1145 };
1146
1147 #endif
1148
1149 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1150 {
1151 #if defined(CONFIG_DEBUG_FS)
1152         unsigned count;
1153
1154         struct drm_minor *minor = rdev->ddev->primary;
1155         struct dentry *ent, *root = minor->debugfs_root;
1156
1157         ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1158                                   rdev, &radeon_ttm_vram_fops);
1159         if (IS_ERR(ent))
1160                 return PTR_ERR(ent);
1161         rdev->mman.vram = ent;
1162
1163         ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1164                                   rdev, &radeon_ttm_gtt_fops);
1165         if (IS_ERR(ent))
1166                 return PTR_ERR(ent);
1167         rdev->mman.gtt = ent;
1168
1169         count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1170
1171 #ifdef CONFIG_SWIOTLB
1172         if (!swiotlb_nr_tbl())
1173                 --count;
1174 #endif
1175
1176         return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1177 #else
1178
1179         return 0;
1180 #endif
1181 }
1182
1183 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1184 {
1185 #if defined(CONFIG_DEBUG_FS)
1186
1187         debugfs_remove(rdev->mman.vram);
1188         rdev->mman.vram = NULL;
1189
1190         debugfs_remove(rdev->mman.gtt);
1191         rdev->mman.gtt = NULL;
1192 #endif
1193 }