drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <drm/drmP.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include <drm/radeon_drm.h>
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  46
  47 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  48 {
  49         unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  50         int r;
  51
  52         /* RV740 uses evergreen uvd clk programming */
  53         if (rdev->family == CHIP_RV740)
  54                 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
  55
  56         /* bypass vclk and dclk with bclk */
  57         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  58                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  59                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  60
  61         if (!vclk || !dclk) {
  62                 /* keep the Bypass mode, put PLL to sleep */
  63                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  64                 return 0;
  65         }
  66
  67         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
  68                                           43663, 0x03FFFFFE, 1, 30, ~0,
  69                                           &fb_div, &vclk_div, &dclk_div);
  70         if (r)
  71                 return r;
  72
  73         fb_div |= 1;
  74         vclk_div -= 1;
  75         dclk_div -= 1;
  76
  77         /* set UPLL_FB_DIV to 0x50000 */
  78         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
  79
  80         /* deassert UPLL_RESET and UPLL_SLEEP */
  81         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
  82
  83         /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
  84         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  85         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
  86
  87         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  88         if (r)
  89                 return r;
  90
  91         /* assert PLL_RESET */
  92         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  93
  94         /* set the required FB_DIV, REF_DIV, Post divder values */
  95         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
  96         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  97                  UPLL_SW_HILEN(vclk_div >> 1) |
  98                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
  99                  UPLL_SW_HILEN2(dclk_div >> 1) |
 100                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
 101                  ~UPLL_SW_MASK);
 102
 103         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
 104                  ~UPLL_FB_DIV_MASK);
 105
 106         /* give the PLL some time to settle */
 107         mdelay(15);
 108
 109         /* deassert PLL_RESET */
 110         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 111
 112         mdelay(15);
 113
 114         /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
 115         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 116         WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
 117
 118         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 119         if (r)
 120                 return r;
 121
 122         /* switch VCLK and DCLK selection */
 123         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 124                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 125                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 126
 127         mdelay(100);
 128
 129         return 0;
 130 }
 131
 132 static const u32 r7xx_golden_registers[] =
 133 {
 134         0x8d00, 0xffffffff, 0x0e0e0074,
 135         0x8d04, 0xffffffff, 0x013a2b34,
 136         0x9508, 0xffffffff, 0x00000002,
 137         0x8b20, 0xffffffff, 0,
 138         0x88c4, 0xffffffff, 0x000000c2,
 139         0x28350, 0xffffffff, 0,
 140         0x9058, 0xffffffff, 0x0fffc40f,
 141         0x240c, 0xffffffff, 0x00000380,
 142         0x733c, 0xffffffff, 0x00000002,
 143         0x2650, 0x00040000, 0,
 144         0x20bc, 0x00040000, 0,
 145         0x7300, 0xffffffff, 0x001000f0
 146 };
 147
 148 static const u32 r7xx_golden_dyn_gpr_registers[] =
 149 {
 150         0x8db0, 0xffffffff, 0x98989898,
 151         0x8db4, 0xffffffff, 0x98989898,
 152         0x8db8, 0xffffffff, 0x98989898,
 153         0x8dbc, 0xffffffff, 0x98989898,
 154         0x8dc0, 0xffffffff, 0x98989898,
 155         0x8dc4, 0xffffffff, 0x98989898,
 156         0x8dc8, 0xffffffff, 0x98989898,
 157         0x8dcc, 0xffffffff, 0x98989898,
 158         0x88c4, 0xffffffff, 0x00000082
 159 };
 160
 161 static const u32 rv770_golden_registers[] =
 162 {
 163         0x562c, 0xffffffff, 0,
 164         0x3f90, 0xffffffff, 0,
 165         0x9148, 0xffffffff, 0,
 166         0x3f94, 0xffffffff, 0,
 167         0x914c, 0xffffffff, 0,
 168         0x9698, 0x18000000, 0x18000000
 169 };
 170
 171 static const u32 rv770ce_golden_registers[] =
 172 {
 173         0x562c, 0xffffffff, 0,
 174         0x3f90, 0xffffffff, 0x00cc0000,
 175         0x9148, 0xffffffff, 0x00cc0000,
 176         0x3f94, 0xffffffff, 0x00cc0000,
 177         0x914c, 0xffffffff, 0x00cc0000,
 178         0x9b7c, 0xffffffff, 0x00fa0000,
 179         0x3f8c, 0xffffffff, 0x00fa0000,
 180         0x9698, 0x18000000, 0x18000000
 181 };
 182
 183 static const u32 rv770_mgcg_init[] =
 184 {
 185         0x8bcc, 0xffffffff, 0x130300f9,
 186         0x5448, 0xffffffff, 0x100,
 187         0x55e4, 0xffffffff, 0x100,
 188         0x160c, 0xffffffff, 0x100,
 189         0x5644, 0xffffffff, 0x100,
 190         0xc164, 0xffffffff, 0x100,
 191         0x8a18, 0xffffffff, 0x100,
 192         0x897c, 0xffffffff, 0x8000100,
 193         0x8b28, 0xffffffff, 0x3c000100,
 194         0x9144, 0xffffffff, 0x100,
 195         0x9a1c, 0xffffffff, 0x10000,
 196         0x9a50, 0xffffffff, 0x100,
 197         0x9a1c, 0xffffffff, 0x10001,
 198         0x9a50, 0xffffffff, 0x100,
 199         0x9a1c, 0xffffffff, 0x10002,
 200         0x9a50, 0xffffffff, 0x100,
 201         0x9a1c, 0xffffffff, 0x10003,
 202         0x9a50, 0xffffffff, 0x100,
 203         0x9a1c, 0xffffffff, 0x0,
 204         0x9870, 0xffffffff, 0x100,
 205         0x8d58, 0xffffffff, 0x100,
 206         0x9500, 0xffffffff, 0x0,
 207         0x9510, 0xffffffff, 0x100,
 208         0x9500, 0xffffffff, 0x1,
 209         0x9510, 0xffffffff, 0x100,
 210         0x9500, 0xffffffff, 0x2,
 211         0x9510, 0xffffffff, 0x100,
 212         0x9500, 0xffffffff, 0x3,
 213         0x9510, 0xffffffff, 0x100,
 214         0x9500, 0xffffffff, 0x4,
 215         0x9510, 0xffffffff, 0x100,
 216         0x9500, 0xffffffff, 0x5,
 217         0x9510, 0xffffffff, 0x100,
 218         0x9500, 0xffffffff, 0x6,
 219         0x9510, 0xffffffff, 0x100,
 220         0x9500, 0xffffffff, 0x7,
 221         0x9510, 0xffffffff, 0x100,
 222         0x9500, 0xffffffff, 0x8,
 223         0x9510, 0xffffffff, 0x100,
 224         0x9500, 0xffffffff, 0x9,
 225         0x9510, 0xffffffff, 0x100,
 226         0x9500, 0xffffffff, 0x8000,
 227         0x9490, 0xffffffff, 0x0,
 228         0x949c, 0xffffffff, 0x100,
 229         0x9490, 0xffffffff, 0x1,
 230         0x949c, 0xffffffff, 0x100,
 231         0x9490, 0xffffffff, 0x2,
 232         0x949c, 0xffffffff, 0x100,
 233         0x9490, 0xffffffff, 0x3,
 234         0x949c, 0xffffffff, 0x100,
 235         0x9490, 0xffffffff, 0x4,
 236         0x949c, 0xffffffff, 0x100,
 237         0x9490, 0xffffffff, 0x5,
 238         0x949c, 0xffffffff, 0x100,
 239         0x9490, 0xffffffff, 0x6,
 240         0x949c, 0xffffffff, 0x100,
 241         0x9490, 0xffffffff, 0x7,
 242         0x949c, 0xffffffff, 0x100,
 243         0x9490, 0xffffffff, 0x8,
 244         0x949c, 0xffffffff, 0x100,
 245         0x9490, 0xffffffff, 0x9,
 246         0x949c, 0xffffffff, 0x100,
 247         0x9490, 0xffffffff, 0x8000,
 248         0x9604, 0xffffffff, 0x0,
 249         0x9654, 0xffffffff, 0x100,
 250         0x9604, 0xffffffff, 0x1,
 251         0x9654, 0xffffffff, 0x100,
 252         0x9604, 0xffffffff, 0x2,
 253         0x9654, 0xffffffff, 0x100,
 254         0x9604, 0xffffffff, 0x3,
 255         0x9654, 0xffffffff, 0x100,
 256         0x9604, 0xffffffff, 0x4,
 257         0x9654, 0xffffffff, 0x100,
 258         0x9604, 0xffffffff, 0x5,
 259         0x9654, 0xffffffff, 0x100,
 260         0x9604, 0xffffffff, 0x6,
 261         0x9654, 0xffffffff, 0x100,
 262         0x9604, 0xffffffff, 0x7,
 263         0x9654, 0xffffffff, 0x100,
 264         0x9604, 0xffffffff, 0x8,
 265         0x9654, 0xffffffff, 0x100,
 266         0x9604, 0xffffffff, 0x9,
 267         0x9654, 0xffffffff, 0x100,
 268         0x9604, 0xffffffff, 0x80000000,
 269         0x9030, 0xffffffff, 0x100,
 270         0x9034, 0xffffffff, 0x100,
 271         0x9038, 0xffffffff, 0x100,
 272         0x903c, 0xffffffff, 0x100,
 273         0x9040, 0xffffffff, 0x100,
 274         0xa200, 0xffffffff, 0x100,
 275         0xa204, 0xffffffff, 0x100,
 276         0xa208, 0xffffffff, 0x100,
 277         0xa20c, 0xffffffff, 0x100,
 278         0x971c, 0xffffffff, 0x100,
 279         0x915c, 0xffffffff, 0x00020001,
 280         0x9160, 0xffffffff, 0x00040003,
 281         0x916c, 0xffffffff, 0x00060005,
 282         0x9170, 0xffffffff, 0x00080007,
 283         0x9174, 0xffffffff, 0x000a0009,
 284         0x9178, 0xffffffff, 0x000c000b,
 285         0x917c, 0xffffffff, 0x000e000d,
 286         0x9180, 0xffffffff, 0x0010000f,
 287         0x918c, 0xffffffff, 0x00120011,
 288         0x9190, 0xffffffff, 0x00140013,
 289         0x9194, 0xffffffff, 0x00020001,
 290         0x9198, 0xffffffff, 0x00040003,
 291         0x919c, 0xffffffff, 0x00060005,
 292         0x91a8, 0xffffffff, 0x00080007,
 293         0x91ac, 0xffffffff, 0x000a0009,
 294         0x91b0, 0xffffffff, 0x000c000b,
 295         0x91b4, 0xffffffff, 0x000e000d,
 296         0x91b8, 0xffffffff, 0x0010000f,
 297         0x91c4, 0xffffffff, 0x00120011,
 298         0x91c8, 0xffffffff, 0x00140013,
 299         0x91cc, 0xffffffff, 0x00020001,
 300         0x91d0, 0xffffffff, 0x00040003,
 301         0x91d4, 0xffffffff, 0x00060005,
 302         0x91e0, 0xffffffff, 0x00080007,
 303         0x91e4, 0xffffffff, 0x000a0009,
 304         0x91e8, 0xffffffff, 0x000c000b,
 305         0x91ec, 0xffffffff, 0x00020001,
 306         0x91f0, 0xffffffff, 0x00040003,
 307         0x91f4, 0xffffffff, 0x00060005,
 308         0x9200, 0xffffffff, 0x00080007,
 309         0x9204, 0xffffffff, 0x000a0009,
 310         0x9208, 0xffffffff, 0x000c000b,
 311         0x920c, 0xffffffff, 0x000e000d,
 312         0x9210, 0xffffffff, 0x0010000f,
 313         0x921c, 0xffffffff, 0x00120011,
 314         0x9220, 0xffffffff, 0x00140013,
 315         0x9224, 0xffffffff, 0x00020001,
 316         0x9228, 0xffffffff, 0x00040003,
 317         0x922c, 0xffffffff, 0x00060005,
 318         0x9238, 0xffffffff, 0x00080007,
 319         0x923c, 0xffffffff, 0x000a0009,
 320         0x9240, 0xffffffff, 0x000c000b,
 321         0x9244, 0xffffffff, 0x000e000d,
 322         0x9248, 0xffffffff, 0x0010000f,
 323         0x9254, 0xffffffff, 0x00120011,
 324         0x9258, 0xffffffff, 0x00140013,
 325         0x925c, 0xffffffff, 0x00020001,
 326         0x9260, 0xffffffff, 0x00040003,
 327         0x9264, 0xffffffff, 0x00060005,
 328         0x9270, 0xffffffff, 0x00080007,
 329         0x9274, 0xffffffff, 0x000a0009,
 330         0x9278, 0xffffffff, 0x000c000b,
 331         0x927c, 0xffffffff, 0x000e000d,
 332         0x9280, 0xffffffff, 0x0010000f,
 333         0x928c, 0xffffffff, 0x00120011,
 334         0x9290, 0xffffffff, 0x00140013,
 335         0x9294, 0xffffffff, 0x00020001,
 336         0x929c, 0xffffffff, 0x00040003,
 337         0x92a0, 0xffffffff, 0x00060005,
 338         0x92a4, 0xffffffff, 0x00080007
 339 };
 340
 341 static const u32 rv710_golden_registers[] =
 342 {
 343         0x3f90, 0x00ff0000, 0x00fc0000,
 344         0x9148, 0x00ff0000, 0x00fc0000,
 345         0x3f94, 0x00ff0000, 0x00fc0000,
 346         0x914c, 0x00ff0000, 0x00fc0000,
 347         0xb4c, 0x00000020, 0x00000020,
 348         0xa180, 0xffffffff, 0x00003f3f
 349 };
 350
 351 static const u32 rv710_mgcg_init[] =
 352 {
 353         0x8bcc, 0xffffffff, 0x13030040,
 354         0x5448, 0xffffffff, 0x100,
 355         0x55e4, 0xffffffff, 0x100,
 356         0x160c, 0xffffffff, 0x100,
 357         0x5644, 0xffffffff, 0x100,
 358         0xc164, 0xffffffff, 0x100,
 359         0x8a18, 0xffffffff, 0x100,
 360         0x897c, 0xffffffff, 0x8000100,
 361         0x8b28, 0xffffffff, 0x3c000100,
 362         0x9144, 0xffffffff, 0x100,
 363         0x9a1c, 0xffffffff, 0x10000,
 364         0x9a50, 0xffffffff, 0x100,
 365         0x9a1c, 0xffffffff, 0x0,
 366         0x9870, 0xffffffff, 0x100,
 367         0x8d58, 0xffffffff, 0x100,
 368         0x9500, 0xffffffff, 0x0,
 369         0x9510, 0xffffffff, 0x100,
 370         0x9500, 0xffffffff, 0x1,
 371         0x9510, 0xffffffff, 0x100,
 372         0x9500, 0xffffffff, 0x8000,
 373         0x9490, 0xffffffff, 0x0,
 374         0x949c, 0xffffffff, 0x100,
 375         0x9490, 0xffffffff, 0x1,
 376         0x949c, 0xffffffff, 0x100,
 377         0x9490, 0xffffffff, 0x8000,
 378         0x9604, 0xffffffff, 0x0,
 379         0x9654, 0xffffffff, 0x100,
 380         0x9604, 0xffffffff, 0x1,
 381         0x9654, 0xffffffff, 0x100,
 382         0x9604, 0xffffffff, 0x80000000,
 383         0x9030, 0xffffffff, 0x100,
 384         0x9034, 0xffffffff, 0x100,
 385         0x9038, 0xffffffff, 0x100,
 386         0x903c, 0xffffffff, 0x100,
 387         0x9040, 0xffffffff, 0x100,
 388         0xa200, 0xffffffff, 0x100,
 389         0xa204, 0xffffffff, 0x100,
 390         0xa208, 0xffffffff, 0x100,
 391         0xa20c, 0xffffffff, 0x100,
 392         0x971c, 0xffffffff, 0x100,
 393         0x915c, 0xffffffff, 0x00020001,
 394         0x9174, 0xffffffff, 0x00000003,
 395         0x9178, 0xffffffff, 0x00050001,
 396         0x917c, 0xffffffff, 0x00030002,
 397         0x918c, 0xffffffff, 0x00000004,
 398         0x9190, 0xffffffff, 0x00070006,
 399         0x9194, 0xffffffff, 0x00050001,
 400         0x9198, 0xffffffff, 0x00030002,
 401         0x91a8, 0xffffffff, 0x00000004,
 402         0x91ac, 0xffffffff, 0x00070006,
 403         0x91e8, 0xffffffff, 0x00000001,
 404         0x9294, 0xffffffff, 0x00000001,
 405         0x929c, 0xffffffff, 0x00000002,
 406         0x92a0, 0xffffffff, 0x00040003,
 407         0x9150, 0xffffffff, 0x4d940000
 408 };
 409
 410 static const u32 rv730_golden_registers[] =
 411 {
 412         0x3f90, 0x00ff0000, 0x00f00000,
 413         0x9148, 0x00ff0000, 0x00f00000,
 414         0x3f94, 0x00ff0000, 0x00f00000,
 415         0x914c, 0x00ff0000, 0x00f00000,
 416         0x900c, 0xffffffff, 0x003b033f,
 417         0xb4c, 0x00000020, 0x00000020,
 418         0xa180, 0xffffffff, 0x00003f3f
 419 };
 420
 421 static const u32 rv730_mgcg_init[] =
 422 {
 423         0x8bcc, 0xffffffff, 0x130300f9,
 424         0x5448, 0xffffffff, 0x100,
 425         0x55e4, 0xffffffff, 0x100,
 426         0x160c, 0xffffffff, 0x100,
 427         0x5644, 0xffffffff, 0x100,
 428         0xc164, 0xffffffff, 0x100,
 429         0x8a18, 0xffffffff, 0x100,
 430         0x897c, 0xffffffff, 0x8000100,
 431         0x8b28, 0xffffffff, 0x3c000100,
 432         0x9144, 0xffffffff, 0x100,
 433         0x9a1c, 0xffffffff, 0x10000,
 434         0x9a50, 0xffffffff, 0x100,
 435         0x9a1c, 0xffffffff, 0x10001,
 436         0x9a50, 0xffffffff, 0x100,
 437         0x9a1c, 0xffffffff, 0x0,
 438         0x9870, 0xffffffff, 0x100,
 439         0x8d58, 0xffffffff, 0x100,
 440         0x9500, 0xffffffff, 0x0,
 441         0x9510, 0xffffffff, 0x100,
 442         0x9500, 0xffffffff, 0x1,
 443         0x9510, 0xffffffff, 0x100,
 444         0x9500, 0xffffffff, 0x2,
 445         0x9510, 0xffffffff, 0x100,
 446         0x9500, 0xffffffff, 0x3,
 447         0x9510, 0xffffffff, 0x100,
 448         0x9500, 0xffffffff, 0x4,
 449         0x9510, 0xffffffff, 0x100,
 450         0x9500, 0xffffffff, 0x5,
 451         0x9510, 0xffffffff, 0x100,
 452         0x9500, 0xffffffff, 0x6,
 453         0x9510, 0xffffffff, 0x100,
 454         0x9500, 0xffffffff, 0x7,
 455         0x9510, 0xffffffff, 0x100,
 456         0x9500, 0xffffffff, 0x8000,
 457         0x9490, 0xffffffff, 0x0,
 458         0x949c, 0xffffffff, 0x100,
 459         0x9490, 0xffffffff, 0x1,
 460         0x949c, 0xffffffff, 0x100,
 461         0x9490, 0xffffffff, 0x2,
 462         0x949c, 0xffffffff, 0x100,
 463         0x9490, 0xffffffff, 0x3,
 464         0x949c, 0xffffffff, 0x100,
 465         0x9490, 0xffffffff, 0x4,
 466         0x949c, 0xffffffff, 0x100,
 467         0x9490, 0xffffffff, 0x5,
 468         0x949c, 0xffffffff, 0x100,
 469         0x9490, 0xffffffff, 0x6,
 470         0x949c, 0xffffffff, 0x100,
 471         0x9490, 0xffffffff, 0x7,
 472         0x949c, 0xffffffff, 0x100,
 473         0x9490, 0xffffffff, 0x8000,
 474         0x9604, 0xffffffff, 0x0,
 475         0x9654, 0xffffffff, 0x100,
 476         0x9604, 0xffffffff, 0x1,
 477         0x9654, 0xffffffff, 0x100,
 478         0x9604, 0xffffffff, 0x2,
 479         0x9654, 0xffffffff, 0x100,
 480         0x9604, 0xffffffff, 0x3,
 481         0x9654, 0xffffffff, 0x100,
 482         0x9604, 0xffffffff, 0x4,
 483         0x9654, 0xffffffff, 0x100,
 484         0x9604, 0xffffffff, 0x5,
 485         0x9654, 0xffffffff, 0x100,
 486         0x9604, 0xffffffff, 0x6,
 487         0x9654, 0xffffffff, 0x100,
 488         0x9604, 0xffffffff, 0x7,
 489         0x9654, 0xffffffff, 0x100,
 490         0x9604, 0xffffffff, 0x80000000,
 491         0x9030, 0xffffffff, 0x100,
 492         0x9034, 0xffffffff, 0x100,
 493         0x9038, 0xffffffff, 0x100,
 494         0x903c, 0xffffffff, 0x100,
 495         0x9040, 0xffffffff, 0x100,
 496         0xa200, 0xffffffff, 0x100,
 497         0xa204, 0xffffffff, 0x100,
 498         0xa208, 0xffffffff, 0x100,
 499         0xa20c, 0xffffffff, 0x100,
 500         0x971c, 0xffffffff, 0x100,
 501         0x915c, 0xffffffff, 0x00020001,
 502         0x916c, 0xffffffff, 0x00040003,
 503         0x9170, 0xffffffff, 0x00000005,
 504         0x9178, 0xffffffff, 0x00050001,
 505         0x917c, 0xffffffff, 0x00030002,
 506         0x918c, 0xffffffff, 0x00000004,
 507         0x9190, 0xffffffff, 0x00070006,
 508         0x9194, 0xffffffff, 0x00050001,
 509         0x9198, 0xffffffff, 0x00030002,
 510         0x91a8, 0xffffffff, 0x00000004,
 511         0x91ac, 0xffffffff, 0x00070006,
 512         0x91b0, 0xffffffff, 0x00050001,
 513         0x91b4, 0xffffffff, 0x00030002,
 514         0x91c4, 0xffffffff, 0x00000004,
 515         0x91c8, 0xffffffff, 0x00070006,
 516         0x91cc, 0xffffffff, 0x00050001,
 517         0x91d0, 0xffffffff, 0x00030002,
 518         0x91e0, 0xffffffff, 0x00000004,
 519         0x91e4, 0xffffffff, 0x00070006,
 520         0x91e8, 0xffffffff, 0x00000001,
 521         0x91ec, 0xffffffff, 0x00050001,
 522         0x91f0, 0xffffffff, 0x00030002,
 523         0x9200, 0xffffffff, 0x00000004,
 524         0x9204, 0xffffffff, 0x00070006,
 525         0x9208, 0xffffffff, 0x00050001,
 526         0x920c, 0xffffffff, 0x00030002,
 527         0x921c, 0xffffffff, 0x00000004,
 528         0x9220, 0xffffffff, 0x00070006,
 529         0x9224, 0xffffffff, 0x00050001,
 530         0x9228, 0xffffffff, 0x00030002,
 531         0x9238, 0xffffffff, 0x00000004,
 532         0x923c, 0xffffffff, 0x00070006,
 533         0x9240, 0xffffffff, 0x00050001,
 534         0x9244, 0xffffffff, 0x00030002,
 535         0x9254, 0xffffffff, 0x00000004,
 536         0x9258, 0xffffffff, 0x00070006,
 537         0x9294, 0xffffffff, 0x00000001,
 538         0x929c, 0xffffffff, 0x00000002,
 539         0x92a0, 0xffffffff, 0x00040003,
 540         0x92a4, 0xffffffff, 0x00000005
 541 };
 542
 543 static const u32 rv740_golden_registers[] =
 544 {
 545         0x88c4, 0xffffffff, 0x00000082,
 546         0x28a50, 0xfffffffc, 0x00000004,
 547         0x2650, 0x00040000, 0,
 548         0x20bc, 0x00040000, 0,
 549         0x733c, 0xffffffff, 0x00000002,
 550         0x7300, 0xffffffff, 0x001000f0,
 551         0x3f90, 0x00ff0000, 0,
 552         0x9148, 0x00ff0000, 0,
 553         0x3f94, 0x00ff0000, 0,
 554         0x914c, 0x00ff0000, 0,
 555         0x240c, 0xffffffff, 0x00000380,
 556         0x8a14, 0x00000007, 0x00000007,
 557         0x8b24, 0xffffffff, 0x00ff0fff,
 558         0x28a4c, 0xffffffff, 0x00004000,
 559         0xa180, 0xffffffff, 0x00003f3f,
 560         0x8d00, 0xffffffff, 0x0e0e003a,
 561         0x8d04, 0xffffffff, 0x013a0e2a,
 562         0x8c00, 0xffffffff, 0xe400000f,
 563         0x8db0, 0xffffffff, 0x98989898,
 564         0x8db4, 0xffffffff, 0x98989898,
 565         0x8db8, 0xffffffff, 0x98989898,
 566         0x8dbc, 0xffffffff, 0x98989898,
 567         0x8dc0, 0xffffffff, 0x98989898,
 568         0x8dc4, 0xffffffff, 0x98989898,
 569         0x8dc8, 0xffffffff, 0x98989898,
 570         0x8dcc, 0xffffffff, 0x98989898,
 571         0x9058, 0xffffffff, 0x0fffc40f,
 572         0x900c, 0xffffffff, 0x003b033f,
 573         0x28350, 0xffffffff, 0,
 574         0x8cf0, 0x1fffffff, 0x08e00420,
 575         0x9508, 0xffffffff, 0x00000002,
 576         0x88c4, 0xffffffff, 0x000000c2,
 577         0x9698, 0x18000000, 0x18000000
 578 };
 579
 580 static const u32 rv740_mgcg_init[] =
 581 {
 582         0x8bcc, 0xffffffff, 0x13030100,
 583         0x5448, 0xffffffff, 0x100,
 584         0x55e4, 0xffffffff, 0x100,
 585         0x160c, 0xffffffff, 0x100,
 586         0x5644, 0xffffffff, 0x100,
 587         0xc164, 0xffffffff, 0x100,
 588         0x8a18, 0xffffffff, 0x100,
 589         0x897c, 0xffffffff, 0x100,
 590         0x8b28, 0xffffffff, 0x100,
 591         0x9144, 0xffffffff, 0x100,
 592         0x9a1c, 0xffffffff, 0x10000,
 593         0x9a50, 0xffffffff, 0x100,
 594         0x9a1c, 0xffffffff, 0x10001,
 595         0x9a50, 0xffffffff, 0x100,
 596         0x9a1c, 0xffffffff, 0x10002,
 597         0x9a50, 0xffffffff, 0x100,
 598         0x9a1c, 0xffffffff, 0x10003,
 599         0x9a50, 0xffffffff, 0x100,
 600         0x9a1c, 0xffffffff, 0x0,
 601         0x9870, 0xffffffff, 0x100,
 602         0x8d58, 0xffffffff, 0x100,
 603         0x9500, 0xffffffff, 0x0,
 604         0x9510, 0xffffffff, 0x100,
 605         0x9500, 0xffffffff, 0x1,
 606         0x9510, 0xffffffff, 0x100,
 607         0x9500, 0xffffffff, 0x2,
 608         0x9510, 0xffffffff, 0x100,
 609         0x9500, 0xffffffff, 0x3,
 610         0x9510, 0xffffffff, 0x100,
 611         0x9500, 0xffffffff, 0x4,
 612         0x9510, 0xffffffff, 0x100,
 613         0x9500, 0xffffffff, 0x5,
 614         0x9510, 0xffffffff, 0x100,
 615         0x9500, 0xffffffff, 0x6,
 616         0x9510, 0xffffffff, 0x100,
 617         0x9500, 0xffffffff, 0x7,
 618         0x9510, 0xffffffff, 0x100,
 619         0x9500, 0xffffffff, 0x8000,
 620         0x9490, 0xffffffff, 0x0,
 621         0x949c, 0xffffffff, 0x100,
 622         0x9490, 0xffffffff, 0x1,
 623         0x949c, 0xffffffff, 0x100,
 624         0x9490, 0xffffffff, 0x2,
 625         0x949c, 0xffffffff, 0x100,
 626         0x9490, 0xffffffff, 0x3,
 627         0x949c, 0xffffffff, 0x100,
 628         0x9490, 0xffffffff, 0x4,
 629         0x949c, 0xffffffff, 0x100,
 630         0x9490, 0xffffffff, 0x5,
 631         0x949c, 0xffffffff, 0x100,
 632         0x9490, 0xffffffff, 0x6,
 633         0x949c, 0xffffffff, 0x100,
 634         0x9490, 0xffffffff, 0x7,
 635         0x949c, 0xffffffff, 0x100,
 636         0x9490, 0xffffffff, 0x8000,
 637         0x9604, 0xffffffff, 0x0,
 638         0x9654, 0xffffffff, 0x100,
 639         0x9604, 0xffffffff, 0x1,
 640         0x9654, 0xffffffff, 0x100,
 641         0x9604, 0xffffffff, 0x2,
 642         0x9654, 0xffffffff, 0x100,
 643         0x9604, 0xffffffff, 0x3,
 644         0x9654, 0xffffffff, 0x100,
 645         0x9604, 0xffffffff, 0x4,
 646         0x9654, 0xffffffff, 0x100,
 647         0x9604, 0xffffffff, 0x5,
 648         0x9654, 0xffffffff, 0x100,
 649         0x9604, 0xffffffff, 0x6,
 650         0x9654, 0xffffffff, 0x100,
 651         0x9604, 0xffffffff, 0x7,
 652         0x9654, 0xffffffff, 0x100,
 653         0x9604, 0xffffffff, 0x80000000,
 654         0x9030, 0xffffffff, 0x100,
 655         0x9034, 0xffffffff, 0x100,
 656         0x9038, 0xffffffff, 0x100,
 657         0x903c, 0xffffffff, 0x100,
 658         0x9040, 0xffffffff, 0x100,
 659         0xa200, 0xffffffff, 0x100,
 660         0xa204, 0xffffffff, 0x100,
 661         0xa208, 0xffffffff, 0x100,
 662         0xa20c, 0xffffffff, 0x100,
 663         0x971c, 0xffffffff, 0x100,
 664         0x915c, 0xffffffff, 0x00020001,
 665         0x9160, 0xffffffff, 0x00040003,
 666         0x916c, 0xffffffff, 0x00060005,
 667         0x9170, 0xffffffff, 0x00080007,
 668         0x9174, 0xffffffff, 0x000a0009,
 669         0x9178, 0xffffffff, 0x000c000b,
 670         0x917c, 0xffffffff, 0x000e000d,
 671         0x9180, 0xffffffff, 0x0010000f,
 672         0x918c, 0xffffffff, 0x00120011,
 673         0x9190, 0xffffffff, 0x00140013,
 674         0x9194, 0xffffffff, 0x00020001,
 675         0x9198, 0xffffffff, 0x00040003,
 676         0x919c, 0xffffffff, 0x00060005,
 677         0x91a8, 0xffffffff, 0x00080007,
 678         0x91ac, 0xffffffff, 0x000a0009,
 679         0x91b0, 0xffffffff, 0x000c000b,
 680         0x91b4, 0xffffffff, 0x000e000d,
 681         0x91b8, 0xffffffff, 0x0010000f,
 682         0x91c4, 0xffffffff, 0x00120011,
 683         0x91c8, 0xffffffff, 0x00140013,
 684         0x91cc, 0xffffffff, 0x00020001,
 685         0x91d0, 0xffffffff, 0x00040003,
 686         0x91d4, 0xffffffff, 0x00060005,
 687         0x91e0, 0xffffffff, 0x00080007,
 688         0x91e4, 0xffffffff, 0x000a0009,
 689         0x91e8, 0xffffffff, 0x000c000b,
 690         0x91ec, 0xffffffff, 0x00020001,
 691         0x91f0, 0xffffffff, 0x00040003,
 692         0x91f4, 0xffffffff, 0x00060005,
 693         0x9200, 0xffffffff, 0x00080007,
 694         0x9204, 0xffffffff, 0x000a0009,
 695         0x9208, 0xffffffff, 0x000c000b,
 696         0x920c, 0xffffffff, 0x000e000d,
 697         0x9210, 0xffffffff, 0x0010000f,
 698         0x921c, 0xffffffff, 0x00120011,
 699         0x9220, 0xffffffff, 0x00140013,
 700         0x9224, 0xffffffff, 0x00020001,
 701         0x9228, 0xffffffff, 0x00040003,
 702         0x922c, 0xffffffff, 0x00060005,
 703         0x9238, 0xffffffff, 0x00080007,
 704         0x923c, 0xffffffff, 0x000a0009,
 705         0x9240, 0xffffffff, 0x000c000b,
 706         0x9244, 0xffffffff, 0x000e000d,
 707         0x9248, 0xffffffff, 0x0010000f,
 708         0x9254, 0xffffffff, 0x00120011,
 709         0x9258, 0xffffffff, 0x00140013,
 710         0x9294, 0xffffffff, 0x00020001,
 711         0x929c, 0xffffffff, 0x00040003,
 712         0x92a0, 0xffffffff, 0x00060005,
 713         0x92a4, 0xffffffff, 0x00080007
 714 };
 715
 716 static void rv770_init_golden_registers(struct radeon_device *rdev)
 717 {
 718         switch (rdev->family) {
 719         case CHIP_RV770:
 720                 radeon_program_register_sequence(rdev,
 721                                                  r7xx_golden_registers,
 722                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 723                 radeon_program_register_sequence(rdev,
 724                                                  r7xx_golden_dyn_gpr_registers,
 725                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 726                 if (rdev->pdev->device == 0x994e)
 727                         radeon_program_register_sequence(rdev,
 728                                                          rv770ce_golden_registers,
 729                                                          (const u32)ARRAY_SIZE(rv770ce_golden_registers));
 730                 else
 731                         radeon_program_register_sequence(rdev,
 732                                                          rv770_golden_registers,
 733                                                          (const u32)ARRAY_SIZE(rv770_golden_registers));
 734                 radeon_program_register_sequence(rdev,
 735                                                  rv770_mgcg_init,
 736                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 737                 break;
 738         case CHIP_RV730:
 739                 radeon_program_register_sequence(rdev,
 740                                                  r7xx_golden_registers,
 741                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 742                 radeon_program_register_sequence(rdev,
 743                                                  r7xx_golden_dyn_gpr_registers,
 744                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 745                 radeon_program_register_sequence(rdev,
 746                                                  rv730_golden_registers,
 747                                                  (const u32)ARRAY_SIZE(rv730_golden_registers));
 748                 radeon_program_register_sequence(rdev,
 749                                                  rv730_mgcg_init,
 750                                                  (const u32)ARRAY_SIZE(rv730_mgcg_init));
 751                 break;
 752         case CHIP_RV710:
 753                 radeon_program_register_sequence(rdev,
 754                                                  r7xx_golden_registers,
 755                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 756                 radeon_program_register_sequence(rdev,
 757                                                  r7xx_golden_dyn_gpr_registers,
 758                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 759                 radeon_program_register_sequence(rdev,
 760                                                  rv710_golden_registers,
 761                                                  (const u32)ARRAY_SIZE(rv710_golden_registers));
 762                 radeon_program_register_sequence(rdev,
 763                                                  rv710_mgcg_init,
 764                                                  (const u32)ARRAY_SIZE(rv710_mgcg_init));
 765                 break;
 766         case CHIP_RV740:
 767                 radeon_program_register_sequence(rdev,
 768                                                  rv740_golden_registers,
 769                                                  (const u32)ARRAY_SIZE(rv740_golden_registers));
 770                 radeon_program_register_sequence(rdev,
 771                                                  rv740_mgcg_init,
 772                                                  (const u32)ARRAY_SIZE(rv740_mgcg_init));
 773                 break;
 774         default:
 775                 break;
 776         }
 777 }
 778
 779 #define PCIE_BUS_CLK                10000
 780 #define TCLK                        (PCIE_BUS_CLK / 10)
 781
 782 /**
 783  * rv770_get_xclk - get the xclk
 784  *
 785  * @rdev: radeon_device pointer
 786  *
 787  * Returns the reference clock used by the gfx engine
 788  * (r7xx-cayman).
 789  */
 790 u32 rv770_get_xclk(struct radeon_device *rdev)
 791 {
 792         u32 reference_clock = rdev->clock.spll.reference_freq;
 793         u32 tmp = RREG32(CG_CLKPIN_CNTL);
 794
 795         if (tmp & MUX_TCLK_TO_XCLK)
 796                 return TCLK;
 797
 798         if (tmp & XTALIN_DIVIDE)
 799                 return reference_clock / 4;
 800
 801         return reference_clock;
 802 }
 803
 804 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 805 {
 806         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 807         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 808         int i;
 809
 810         /* Lock the graphics update lock */
 811         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 812         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 813
 814         /* update the scanout addresses */
 815         if (radeon_crtc->crtc_id) {
 816                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 817                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 818         } else {
 819                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 820                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 821         }
 822         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 823                (u32)crtc_base);
 824         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 825                (u32)crtc_base);
 826
 827         /* Wait for update_pending to go high. */
 828         for (i = 0; i < rdev->usec_timeout; i++) {
 829                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 830                         break;
 831                 udelay(1);
 832         }
 833         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 834
 835         /* Unlock the lock, so double-buffering can take place inside vblank */
 836         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 837         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 838
 839         /* Return current update_pending status: */
 840         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 841 }
 842
 843 /* get temperature in millidegrees */
 844 int rv770_get_temp(struct radeon_device *rdev)
 845 {
 846         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 847                 ASIC_T_SHIFT;
 848         int actual_temp;
 849
 850         if (temp & 0x400)
 851                 actual_temp = -256;
 852         else if (temp & 0x200)
 853                 actual_temp = 255;
 854         else if (temp & 0x100) {
 855                 actual_temp = temp & 0x1ff;
 856                 actual_temp |= ~0x1ff;
 857         } else
 858                 actual_temp = temp & 0xff;
 859
 860         return (actual_temp * 1000) / 2;
 861 }
 862
 863 void rv770_pm_misc(struct radeon_device *rdev)
 864 {
 865         int req_ps_idx = rdev->pm.requested_power_state_index;
 866         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 867         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 868         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 869
 870         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 871                 /* 0xff01 is a flag rather then an actual voltage */
 872                 if (voltage->voltage == 0xff01)
 873                         return;
 874                 if (voltage->voltage != rdev->pm.current_vddc) {
 875                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 876                         rdev->pm.current_vddc = voltage->voltage;
 877                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 878                 }
 879         }
 880 }
 881
 882 /*
 883  * GART
 884  */
 885 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
 886 {
 887         u32 tmp;
 888         int r, i;
 889
 890         if (rdev->gart.robj == NULL) {
 891                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 892                 return -EINVAL;
 893         }
 894         r = radeon_gart_table_vram_pin(rdev);
 895         if (r)
 896                 return r;
 897         radeon_gart_restore(rdev);
 898         /* Setup L2 cache */
 899         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 900                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 901                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 902         WREG32(VM_L2_CNTL2, 0);
 903         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 904         /* Setup TLB control */
 905         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 906                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 907                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 908                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 909         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 910         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 911         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 912         if (rdev->family == CHIP_RV740)
 913                 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
 914         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 915         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 916         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 917         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 918         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 919         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 920         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 921         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 922                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 923         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 924                         (u32)(rdev->dummy_page.addr >> 12));
 925         for (i = 1; i < 7; i++)
 926                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 927
 928         r600_pcie_gart_tlb_flush(rdev);
 929         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 930                  (unsigned)(rdev->mc.gtt_size >> 20),
 931                  (unsigned long long)rdev->gart.table_addr);
 932         rdev->gart.ready = true;
 933         return 0;
 934 }
 935
 936 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
 937 {
 938         u32 tmp;
 939         int i;
 940
 941         /* Disable all tables */
 942         for (i = 0; i < 7; i++)
 943                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 944
 945         /* Setup L2 cache */
 946         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 947                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 948         WREG32(VM_L2_CNTL2, 0);
 949         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 950         /* Setup TLB control */
 951         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 952         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 953         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 954         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 955         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 956         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 957         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 958         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 959         radeon_gart_table_vram_unpin(rdev);
 960 }
 961
 962 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
 963 {
 964         radeon_gart_fini(rdev);
 965         rv770_pcie_gart_disable(rdev);
 966         radeon_gart_table_vram_free(rdev);
 967 }
 968
 969
 970 static void rv770_agp_enable(struct radeon_device *rdev)
 971 {
 972         u32 tmp;
 973         int i;
 974
 975         /* Setup L2 cache */
 976         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 977                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 978                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 979         WREG32(VM_L2_CNTL2, 0);
 980         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 981         /* Setup TLB control */
 982         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 983                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 984                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 985                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 986         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 987         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 988         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 989         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 990         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 991         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 992         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 993         for (i = 0; i < 7; i++)
 994                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 995 }
 996
 997 static void rv770_mc_program(struct radeon_device *rdev)
 998 {
 999         struct rv515_mc_save save;
1000         u32 tmp;
1001         int i, j;
1002
1003         /* Initialize HDP */
1004         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1005                 WREG32((0x2c14 + j), 0x00000000);
1006                 WREG32((0x2c18 + j), 0x00000000);
1007                 WREG32((0x2c1c + j), 0x00000000);
1008                 WREG32((0x2c20 + j), 0x00000000);
1009                 WREG32((0x2c24 + j), 0x00000000);
1010         }
1011         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
1012          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1013          */
1014         tmp = RREG32(HDP_DEBUG1);
1015
1016         rv515_mc_stop(rdev, &save);
1017         if (r600_mc_wait_for_idle(rdev)) {
1018                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1019         }
1020         /* Lockout access through VGA aperture*/
1021         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1022         /* Update configuration */
1023         if (rdev->flags & RADEON_IS_AGP) {
1024                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1025                         /* VRAM before AGP */
1026                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1027                                 rdev->mc.vram_start >> 12);
1028                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1029                                 rdev->mc.gtt_end >> 12);
1030                 } else {
1031                         /* VRAM after AGP */
1032                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1033                                 rdev->mc.gtt_start >> 12);
1034                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1035                                 rdev->mc.vram_end >> 12);
1036                 }
1037         } else {
1038                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1039                         rdev->mc.vram_start >> 12);
1040                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1041                         rdev->mc.vram_end >> 12);
1042         }
1043         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1044         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1045         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1046         WREG32(MC_VM_FB_LOCATION, tmp);
1047         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1048         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1049         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1050         if (rdev->flags & RADEON_IS_AGP) {
1051                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1052                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1053                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1054         } else {
1055                 WREG32(MC_VM_AGP_BASE, 0);
1056                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1057                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1058         }
1059         if (r600_mc_wait_for_idle(rdev)) {
1060                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1061         }
1062         rv515_mc_resume(rdev, &save);
1063         /* we need to own VRAM, so turn off the VGA renderer here
1064          * to stop it overwriting our objects */
1065         rv515_vga_render_disable(rdev);
1066 }
1067
1068
1069 /*
1070  * CP.
1071  */
1072 void r700_cp_stop(struct radeon_device *rdev)
1073 {
1074         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1075                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1076         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1077         WREG32(SCRATCH_UMSK, 0);
1078         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1079 }
1080
1081 static int rv770_cp_load_microcode(struct radeon_device *rdev)
1082 {
1083         const __be32 *fw_data;
1084         int i;
1085
1086         if (!rdev->me_fw || !rdev->pfp_fw)
1087                 return -EINVAL;
1088
1089         r700_cp_stop(rdev);
1090         WREG32(CP_RB_CNTL,
1091 #ifdef __BIG_ENDIAN
1092                BUF_SWAP_32BIT |
1093 #endif
1094                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1095
1096         /* Reset cp */
1097         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1098         RREG32(GRBM_SOFT_RESET);
1099         mdelay(15);
1100         WREG32(GRBM_SOFT_RESET, 0);
1101
1102         fw_data = (const __be32 *)rdev->pfp_fw->data;
1103         WREG32(CP_PFP_UCODE_ADDR, 0);
1104         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1105                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1106         WREG32(CP_PFP_UCODE_ADDR, 0);
1107
1108         fw_data = (const __be32 *)rdev->me_fw->data;
1109         WREG32(CP_ME_RAM_WADDR, 0);
1110         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1111                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1112
1113         WREG32(CP_PFP_UCODE_ADDR, 0);
1114         WREG32(CP_ME_RAM_WADDR, 0);
1115         WREG32(CP_ME_RAM_RADDR, 0);
1116         return 0;
1117 }
1118
1119 void r700_cp_fini(struct radeon_device *rdev)
1120 {
1121         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1122         r700_cp_stop(rdev);
1123         radeon_ring_fini(rdev, ring);
1124         radeon_scratch_free(rdev, ring->rptr_save_reg);
1125 }
1126
1127 void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1128 {
1129         u32 tmp, i;
1130
1131         if (rdev->flags & RADEON_IS_IGP)
1132                 return;
1133
1134         tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1135         tmp &= SCLK_MUX_SEL_MASK;
1136         tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1137         WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1138
1139         for (i = 0; i < rdev->usec_timeout; i++) {
1140                 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
1141                         break;
1142                 udelay(1);
1143         }
1144
1145         tmp &= ~SCLK_MUX_UPDATE;
1146         WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1147
1148         tmp = RREG32(MPLL_CNTL_MODE);
1149         if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1150                 tmp &= ~RV730_MPLL_MCLK_SEL;
1151         else
1152                 tmp &= ~MPLL_MCLK_SEL;
1153         WREG32(MPLL_CNTL_MODE, tmp);
1154 }
1155
1156 /*
1157  * Core functions
1158  */
1159 static void rv770_gpu_init(struct radeon_device *rdev)
1160 {
1161         int i, j, num_qd_pipes;
1162         u32 ta_aux_cntl;
1163         u32 sx_debug_1;
1164         u32 smx_dc_ctl0;
1165         u32 db_debug3;
1166         u32 num_gs_verts_per_thread;
1167         u32 vgt_gs_per_es;
1168         u32 gs_prim_buffer_depth = 0;
1169         u32 sq_ms_fifo_sizes;
1170         u32 sq_config;
1171         u32 sq_thread_resource_mgmt;
1172         u32 hdp_host_path_cntl;
1173         u32 sq_dyn_gpr_size_simd_ab_0;
1174         u32 gb_tiling_config = 0;
1175         u32 cc_rb_backend_disable = 0;
1176         u32 cc_gc_shader_pipe_config = 0;
1177         u32 mc_arb_ramcfg;
1178         u32 db_debug4, tmp;
1179         u32 inactive_pipes, shader_pipe_config;
1180         u32 disabled_rb_mask;
1181         unsigned active_number;
1182
1183         /* setup chip specs */
1184         rdev->config.rv770.tiling_group_size = 256;
1185         switch (rdev->family) {
1186         case CHIP_RV770:
1187                 rdev->config.rv770.max_pipes = 4;
1188                 rdev->config.rv770.max_tile_pipes = 8;
1189                 rdev->config.rv770.max_simds = 10;
1190                 rdev->config.rv770.max_backends = 4;
1191                 rdev->config.rv770.max_gprs = 256;
1192                 rdev->config.rv770.max_threads = 248;
1193                 rdev->config.rv770.max_stack_entries = 512;
1194                 rdev->config.rv770.max_hw_contexts = 8;
1195                 rdev->config.rv770.max_gs_threads = 16 * 2;
1196                 rdev->config.rv770.sx_max_export_size = 128;
1197                 rdev->config.rv770.sx_max_export_pos_size = 16;
1198                 rdev->config.rv770.sx_max_export_smx_size = 112;
1199                 rdev->config.rv770.sq_num_cf_insts = 2;
1200
1201                 rdev->config.rv770.sx_num_of_sets = 7;
1202                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1203                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1204                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1205                 break;
1206         case CHIP_RV730:
1207                 rdev->config.rv770.max_pipes = 2;
1208                 rdev->config.rv770.max_tile_pipes = 4;
1209                 rdev->config.rv770.max_simds = 8;
1210                 rdev->config.rv770.max_backends = 2;
1211                 rdev->config.rv770.max_gprs = 128;
1212                 rdev->config.rv770.max_threads = 248;
1213                 rdev->config.rv770.max_stack_entries = 256;
1214                 rdev->config.rv770.max_hw_contexts = 8;
1215                 rdev->config.rv770.max_gs_threads = 16 * 2;
1216                 rdev->config.rv770.sx_max_export_size = 256;
1217                 rdev->config.rv770.sx_max_export_pos_size = 32;
1218                 rdev->config.rv770.sx_max_export_smx_size = 224;
1219                 rdev->config.rv770.sq_num_cf_insts = 2;
1220
1221                 rdev->config.rv770.sx_num_of_sets = 7;
1222                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1223                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1224                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1225                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1226                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1227                         rdev->config.rv770.sx_max_export_smx_size += 16;
1228                 }
1229                 break;
1230         case CHIP_RV710:
1231                 rdev->config.rv770.max_pipes = 2;
1232                 rdev->config.rv770.max_tile_pipes = 2;
1233                 rdev->config.rv770.max_simds = 2;
1234                 rdev->config.rv770.max_backends = 1;
1235                 rdev->config.rv770.max_gprs = 256;
1236                 rdev->config.rv770.max_threads = 192;
1237                 rdev->config.rv770.max_stack_entries = 256;
1238                 rdev->config.rv770.max_hw_contexts = 4;
1239                 rdev->config.rv770.max_gs_threads = 8 * 2;
1240                 rdev->config.rv770.sx_max_export_size = 128;
1241                 rdev->config.rv770.sx_max_export_pos_size = 16;
1242                 rdev->config.rv770.sx_max_export_smx_size = 112;
1243                 rdev->config.rv770.sq_num_cf_insts = 1;
1244
1245                 rdev->config.rv770.sx_num_of_sets = 7;
1246                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1247                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1248                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1249                 break;
1250         case CHIP_RV740:
1251                 rdev->config.rv770.max_pipes = 4;
1252                 rdev->config.rv770.max_tile_pipes = 4;
1253                 rdev->config.rv770.max_simds = 8;
1254                 rdev->config.rv770.max_backends = 4;
1255                 rdev->config.rv770.max_gprs = 256;
1256                 rdev->config.rv770.max_threads = 248;
1257                 rdev->config.rv770.max_stack_entries = 512;
1258                 rdev->config.rv770.max_hw_contexts = 8;
1259                 rdev->config.rv770.max_gs_threads = 16 * 2;
1260                 rdev->config.rv770.sx_max_export_size = 256;
1261                 rdev->config.rv770.sx_max_export_pos_size = 32;
1262                 rdev->config.rv770.sx_max_export_smx_size = 224;
1263                 rdev->config.rv770.sq_num_cf_insts = 2;
1264
1265                 rdev->config.rv770.sx_num_of_sets = 7;
1266                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1267                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1268                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1269
1270                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1271                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1272                         rdev->config.rv770.sx_max_export_smx_size += 16;
1273                 }
1274                 break;
1275         default:
1276                 break;
1277         }
1278
1279         /* Initialize HDP */
1280         j = 0;
1281         for (i = 0; i < 32; i++) {
1282                 WREG32((0x2c14 + j), 0x00000000);
1283                 WREG32((0x2c18 + j), 0x00000000);
1284                 WREG32((0x2c1c + j), 0x00000000);
1285                 WREG32((0x2c20 + j), 0x00000000);
1286                 WREG32((0x2c24 + j), 0x00000000);
1287                 j += 0x18;
1288         }
1289
1290         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1291
1292         /* setup tiling, simd, pipe config */
1293         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1294
1295         shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1296         inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1297         for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1298                 if (!(inactive_pipes & tmp)) {
1299                         active_number++;
1300                 }
1301                 tmp <<= 1;
1302         }
1303         if (active_number == 1) {
1304                 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1305         } else {
1306                 WREG32(SPI_CONFIG_CNTL, 0);
1307         }
1308
1309         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1310         tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
1311         if (tmp < rdev->config.rv770.max_backends) {
1312                 rdev->config.rv770.max_backends = tmp;
1313         }
1314
1315         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1316         tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
1317         if (tmp < rdev->config.rv770.max_pipes) {
1318                 rdev->config.rv770.max_pipes = tmp;
1319         }
1320         tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1321         if (tmp < rdev->config.rv770.max_simds) {
1322                 rdev->config.rv770.max_simds = tmp;
1323         }
1324
1325         switch (rdev->config.rv770.max_tile_pipes) {
1326         case 1:
1327         default:
1328                 gb_tiling_config = PIPE_TILING(0);
1329                 break;
1330         case 2:
1331                 gb_tiling_config = PIPE_TILING(1);
1332                 break;
1333         case 4:
1334                 gb_tiling_config = PIPE_TILING(2);
1335                 break;
1336         case 8:
1337                 gb_tiling_config = PIPE_TILING(3);
1338                 break;
1339         }
1340         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1341
1342         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1343         tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1344         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1345                                         R7XX_MAX_BACKENDS, disabled_rb_mask);
1346         gb_tiling_config |= tmp << 16;
1347         rdev->config.rv770.backend_map = tmp;
1348
1349         if (rdev->family == CHIP_RV770)
1350                 gb_tiling_config |= BANK_TILING(1);
1351         else {
1352                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1353                         gb_tiling_config |= BANK_TILING(1);
1354                 else
1355                         gb_tiling_config |= BANK_TILING(0);
1356         }
1357         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1358         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1359         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1360                 gb_tiling_config |= ROW_TILING(3);
1361                 gb_tiling_config |= SAMPLE_SPLIT(3);
1362         } else {
1363                 gb_tiling_config |=
1364                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1365                 gb_tiling_config |=
1366                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1367         }
1368
1369         gb_tiling_config |= BANK_SWAPS(1);
1370         rdev->config.rv770.tile_config = gb_tiling_config;
1371
1372         WREG32(GB_TILING_CONFIG, gb_tiling_config);
1373         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1374         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1375         WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1376         WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1377         if (rdev->family == CHIP_RV730) {
1378                 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1379                 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1380                 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1381         }
1382
1383         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1384         WREG32(CGTS_TCC_DISABLE, 0);
1385         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1386         WREG32(CGTS_USER_TCC_DISABLE, 0);
1387
1388
1389         num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1390         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1391         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1392
1393         /* set HW defaults for 3D engine */
1394         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1395                                      ROQ_IB2_START(0x2b)));
1396
1397         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1398
1399         ta_aux_cntl = RREG32(TA_CNTL_AUX);
1400         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1401
1402         sx_debug_1 = RREG32(SX_DEBUG_1);
1403         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1404         WREG32(SX_DEBUG_1, sx_debug_1);
1405
1406         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1407         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1408         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1409         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1410
1411         if (rdev->family != CHIP_RV740)
1412                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1413                                        GS_FLUSH_CTL(4) |
1414                                        ACK_FLUSH_CTL(3) |
1415                                        SYNC_FLUSH_CTL));
1416
1417         if (rdev->family != CHIP_RV770)
1418                 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1419
1420         db_debug3 = RREG32(DB_DEBUG3);
1421         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1422         switch (rdev->family) {
1423         case CHIP_RV770:
1424         case CHIP_RV740:
1425                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1426                 break;
1427         case CHIP_RV710:
1428         case CHIP_RV730:
1429         default:
1430                 db_debug3 |= DB_CLK_OFF_DELAY(2);
1431                 break;
1432         }
1433         WREG32(DB_DEBUG3, db_debug3);
1434
1435         if (rdev->family != CHIP_RV770) {
1436                 db_debug4 = RREG32(DB_DEBUG4);
1437                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1438                 WREG32(DB_DEBUG4, db_debug4);
1439         }
1440
1441         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1442                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1443                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1444
1445         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1446                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1447                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1448
1449         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1450
1451         WREG32(VGT_NUM_INSTANCES, 1);
1452
1453         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1454
1455         WREG32(CP_PERFMON_CNTL, 0);
1456
1457         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1458                             DONE_FIFO_HIWATER(0xe0) |
1459                             ALU_UPDATE_FIFO_HIWATER(0x8));
1460         switch (rdev->family) {
1461         case CHIP_RV770:
1462         case CHIP_RV730:
1463         case CHIP_RV710:
1464                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1465                 break;
1466         case CHIP_RV740:
1467         default:
1468                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1469                 break;
1470         }
1471         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1472
1473         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1474          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1475          */
1476         sq_config = RREG32(SQ_CONFIG);
1477         sq_config &= ~(PS_PRIO(3) |
1478                        VS_PRIO(3) |
1479                        GS_PRIO(3) |
1480                        ES_PRIO(3));
1481         sq_config |= (DX9_CONSTS |
1482                       VC_ENABLE |
1483                       EXPORT_SRC_C |
1484                       PS_PRIO(0) |
1485                       VS_PRIO(1) |
1486                       GS_PRIO(2) |
1487                       ES_PRIO(3));
1488         if (rdev->family == CHIP_RV710)
1489                 /* no vertex cache */
1490                 sq_config &= ~VC_ENABLE;
1491
1492         WREG32(SQ_CONFIG, sq_config);
1493
1494         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1495                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1496                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1497
1498         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1499                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1500
1501         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1502                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1503                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1504         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1505                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1506         else
1507                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1508         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1509
1510         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1511                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1512
1513         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1514                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1515
1516         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1517                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1518                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1519                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1520
1521         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1522         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1523         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1524         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1525         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1526         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1527         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1528         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1529
1530         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1531                                           FORCE_EOV_MAX_REZ_CNT(255)));
1532
1533         if (rdev->family == CHIP_RV710)
1534                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1535                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1536         else
1537                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1538                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1539
1540         switch (rdev->family) {
1541         case CHIP_RV770:
1542         case CHIP_RV730:
1543         case CHIP_RV740:
1544                 gs_prim_buffer_depth = 384;
1545                 break;
1546         case CHIP_RV710:
1547                 gs_prim_buffer_depth = 128;
1548                 break;
1549         default:
1550                 break;
1551         }
1552
1553         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1554         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1555         /* Max value for this is 256 */
1556         if (vgt_gs_per_es > 256)
1557                 vgt_gs_per_es = 256;
1558
1559         WREG32(VGT_ES_PER_GS, 128);
1560         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1561         WREG32(VGT_GS_PER_VS, 2);
1562
1563         /* more default values. 2D/3D driver should adjust as needed */
1564         WREG32(VGT_GS_VERTEX_REUSE, 16);
1565         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1566         WREG32(VGT_STRMOUT_EN, 0);
1567         WREG32(SX_MISC, 0);
1568         WREG32(PA_SC_MODE_CNTL, 0);
1569         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1570         WREG32(PA_SC_AA_CONFIG, 0);
1571         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1572         WREG32(PA_SC_LINE_STIPPLE, 0);
1573         WREG32(SPI_INPUT_Z, 0);
1574         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1575         WREG32(CB_COLOR7_FRAG, 0);
1576
1577         /* clear render buffer base addresses */
1578         WREG32(CB_COLOR0_BASE, 0);
1579         WREG32(CB_COLOR1_BASE, 0);
1580         WREG32(CB_COLOR2_BASE, 0);
1581         WREG32(CB_COLOR3_BASE, 0);
1582         WREG32(CB_COLOR4_BASE, 0);
1583         WREG32(CB_COLOR5_BASE, 0);
1584         WREG32(CB_COLOR6_BASE, 0);
1585         WREG32(CB_COLOR7_BASE, 0);
1586
1587         WREG32(TCP_CNTL, 0);
1588
1589         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1590         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1591
1592         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1593
1594         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1595                                           NUM_CLIP_SEQ(3)));
1596         WREG32(VC_ENHANCE, 0);
1597 }
1598
1599 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1600 {
1601         u64 size_bf, size_af;
1602
1603         if (mc->mc_vram_size > 0xE0000000) {
1604                 /* leave room for at least 512M GTT */
1605                 dev_warn(rdev->dev, "limiting VRAM\n");
1606                 mc->real_vram_size = 0xE0000000;
1607                 mc->mc_vram_size = 0xE0000000;
1608         }
1609         if (rdev->flags & RADEON_IS_AGP) {
1610                 size_bf = mc->gtt_start;
1611                 size_af = mc->mc_mask - mc->gtt_end;
1612                 if (size_bf > size_af) {
1613                         if (mc->mc_vram_size > size_bf) {
1614                                 dev_warn(rdev->dev, "limiting VRAM\n");
1615                                 mc->real_vram_size = size_bf;
1616                                 mc->mc_vram_size = size_bf;
1617                         }
1618                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1619                 } else {
1620                         if (mc->mc_vram_size > size_af) {
1621                                 dev_warn(rdev->dev, "limiting VRAM\n");
1622                                 mc->real_vram_size = size_af;
1623                                 mc->mc_vram_size = size_af;
1624                         }
1625                         mc->vram_start = mc->gtt_end + 1;
1626                 }
1627                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1628                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1629                                 mc->mc_vram_size >> 20, mc->vram_start,
1630                                 mc->vram_end, mc->real_vram_size >> 20);
1631         } else {
1632                 radeon_vram_location(rdev, &rdev->mc, 0);
1633                 rdev->mc.gtt_base_align = 0;
1634                 radeon_gtt_location(rdev, mc);
1635         }
1636 }
1637
1638 static int rv770_mc_init(struct radeon_device *rdev)
1639 {
1640         u32 tmp;
1641         int chansize, numchan;
1642
1643         /* Get VRAM informations */
1644         rdev->mc.vram_is_ddr = true;
1645         tmp = RREG32(MC_ARB_RAMCFG);
1646         if (tmp & CHANSIZE_OVERRIDE) {
1647                 chansize = 16;
1648         } else if (tmp & CHANSIZE_MASK) {
1649                 chansize = 64;
1650         } else {
1651                 chansize = 32;
1652         }
1653         tmp = RREG32(MC_SHARED_CHMAP);
1654         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1655         case 0:
1656         default:
1657                 numchan = 1;
1658                 break;
1659         case 1:
1660                 numchan = 2;
1661                 break;
1662         case 2:
1663                 numchan = 4;
1664                 break;
1665         case 3:
1666                 numchan = 8;
1667                 break;
1668         }
1669         rdev->mc.vram_width = numchan * chansize;
1670         /* Could aper size report 0 ? */
1671         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1672         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1673         /* Setup GPU memory space */
1674         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1675         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1676         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1677         r700_vram_gtt_location(rdev, &rdev->mc);
1678         radeon_update_bandwidth_info(rdev);
1679
1680         return 0;
1681 }
1682
1683 static int rv770_startup(struct radeon_device *rdev)
1684 {
1685         struct radeon_ring *ring;
1686         int r;
1687
1688         /* enable pcie gen2 link */
1689         rv770_pcie_gen2_enable(rdev);
1690
1691         /* scratch needs to be initialized before MC */
1692         r = r600_vram_scratch_init(rdev);
1693         if (r)
1694                 return r;
1695
1696         rv770_mc_program(rdev);
1697
1698         if (rdev->flags & RADEON_IS_AGP) {
1699                 rv770_agp_enable(rdev);
1700         } else {
1701                 r = rv770_pcie_gart_enable(rdev);
1702                 if (r)
1703                         return r;
1704         }
1705
1706         rv770_gpu_init(rdev);
1707
1708         /* allocate wb buffer */
1709         r = radeon_wb_init(rdev);
1710         if (r)
1711                 return r;
1712
1713         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1714         if (r) {
1715                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1716                 return r;
1717         }
1718
1719         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1720         if (r) {
1721                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1722                 return r;
1723         }
1724
1725         r = uvd_v2_2_resume(rdev);
1726         if (!r) {
1727                 r = radeon_fence_driver_start_ring(rdev,
1728                                                    R600_RING_TYPE_UVD_INDEX);
1729                 if (r)
1730                         dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1731         }
1732
1733         if (r)
1734                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1735
1736         /* Enable IRQ */
1737         if (!rdev->irq.installed) {
1738                 r = radeon_irq_kms_init(rdev);
1739                 if (r)
1740                         return r;
1741         }
1742
1743         r = r600_irq_init(rdev);
1744         if (r) {
1745                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1746                 radeon_irq_kms_fini(rdev);
1747                 return r;
1748         }
1749         r600_irq_set(rdev);
1750
1751         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1752         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1753                              RADEON_CP_PACKET2);
1754         if (r)
1755                 return r;
1756
1757         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1758         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1759                              DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1760         if (r)
1761                 return r;
1762
1763         r = rv770_cp_load_microcode(rdev);
1764         if (r)
1765                 return r;
1766         r = r600_cp_resume(rdev);
1767         if (r)
1768                 return r;
1769
1770         r = r600_dma_resume(rdev);
1771         if (r)
1772                 return r;
1773
1774         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1775         if (ring->ring_size) {
1776                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
1777                                      RADEON_CP_PACKET2);
1778                 if (!r)
1779                         r = uvd_v1_0_init(rdev);
1780
1781                 if (r)
1782                         DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1783         }
1784
1785         r = radeon_ib_pool_init(rdev);
1786         if (r) {
1787                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1788                 return r;
1789         }
1790
1791         r = r600_audio_init(rdev);
1792         if (r) {
1793                 DRM_ERROR("radeon: audio init failed\n");
1794                 return r;
1795         }
1796
1797         return 0;
1798 }
1799
1800 int rv770_resume(struct radeon_device *rdev)
1801 {
1802         int r;
1803
1804         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1805          * posting will perform necessary task to bring back GPU into good
1806          * shape.
1807          */
1808         /* post card */
1809         atom_asic_init(rdev->mode_info.atom_context);
1810
1811         /* init golden registers */
1812         rv770_init_golden_registers(rdev);
1813
1814         radeon_pm_resume(rdev);
1815
1816         rdev->accel_working = true;
1817         r = rv770_startup(rdev);
1818         if (r) {
1819                 DRM_ERROR("r600 startup failed on resume\n");
1820                 rdev->accel_working = false;
1821                 return r;
1822         }
1823
1824         return r;
1825
1826 }
1827
1828 int rv770_suspend(struct radeon_device *rdev)
1829 {
1830         radeon_pm_suspend(rdev);
1831         r600_audio_fini(rdev);
1832         uvd_v1_0_fini(rdev);
1833         radeon_uvd_suspend(rdev);
1834         r700_cp_stop(rdev);
1835         r600_dma_stop(rdev);
1836         r600_irq_suspend(rdev);
1837         radeon_wb_disable(rdev);
1838         rv770_pcie_gart_disable(rdev);
1839
1840         return 0;
1841 }
1842
1843 /* Plan is to move initialization in that function and use
1844  * helper function so that radeon_device_init pretty much
1845  * do nothing more than calling asic specific function. This
1846  * should also allow to remove a bunch of callback function
1847  * like vram_info.
1848  */
1849 int rv770_init(struct radeon_device *rdev)
1850 {
1851         int r;
1852
1853         /* Read BIOS */
1854         if (!radeon_get_bios(rdev)) {
1855                 if (ASIC_IS_AVIVO(rdev))
1856                         return -EINVAL;
1857         }
1858         /* Must be an ATOMBIOS */
1859         if (!rdev->is_atom_bios) {
1860                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1861                 return -EINVAL;
1862         }
1863         r = radeon_atombios_init(rdev);
1864         if (r)
1865                 return r;
1866         /* Post card if necessary */
1867         if (!radeon_card_posted(rdev)) {
1868                 if (!rdev->bios) {
1869                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1870                         return -EINVAL;
1871                 }
1872                 DRM_INFO("GPU not posted. posting now...\n");
1873                 atom_asic_init(rdev->mode_info.atom_context);
1874         }
1875         /* init golden registers */
1876         rv770_init_golden_registers(rdev);
1877         /* Initialize scratch registers */
1878         r600_scratch_init(rdev);
1879         /* Initialize surface registers */
1880         radeon_surface_init(rdev);
1881         /* Initialize clocks */
1882         radeon_get_clock_info(rdev->ddev);
1883         /* Fence driver */
1884         r = radeon_fence_driver_init(rdev);
1885         if (r)
1886                 return r;
1887         /* initialize AGP */
1888         if (rdev->flags & RADEON_IS_AGP) {
1889                 r = radeon_agp_init(rdev);
1890                 if (r)
1891                         radeon_agp_disable(rdev);
1892         }
1893         r = rv770_mc_init(rdev);
1894         if (r)
1895                 return r;
1896         /* Memory manager */
1897         r = radeon_bo_init(rdev);
1898         if (r)
1899                 return r;
1900
1901         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1902                 r = r600_init_microcode(rdev);
1903                 if (r) {
1904                         DRM_ERROR("Failed to load firmware!\n");
1905                         return r;
1906                 }
1907         }
1908
1909         /* Initialize power management */
1910         radeon_pm_init(rdev);
1911
1912         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1913         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1914
1915         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1916         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1917
1918         r = radeon_uvd_init(rdev);
1919         if (!r) {
1920                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1921                 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
1922                                4096);
1923         }
1924
1925         rdev->ih.ring_obj = NULL;
1926         r600_ih_ring_init(rdev, 64 * 1024);
1927
1928         r = r600_pcie_gart_init(rdev);
1929         if (r)
1930                 return r;
1931
1932         rdev->accel_working = true;
1933         r = rv770_startup(rdev);
1934         if (r) {
1935                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1936                 r700_cp_fini(rdev);
1937                 r600_dma_fini(rdev);
1938                 r600_irq_fini(rdev);
1939                 radeon_wb_fini(rdev);
1940                 radeon_ib_pool_fini(rdev);
1941                 radeon_irq_kms_fini(rdev);
1942                 rv770_pcie_gart_fini(rdev);
1943                 rdev->accel_working = false;
1944         }
1945
1946         return 0;
1947 }
1948
1949 void rv770_fini(struct radeon_device *rdev)
1950 {
1951         radeon_pm_fini(rdev);
1952         r700_cp_fini(rdev);
1953         r600_dma_fini(rdev);
1954         r600_irq_fini(rdev);
1955         radeon_wb_fini(rdev);
1956         radeon_ib_pool_fini(rdev);
1957         radeon_irq_kms_fini(rdev);
1958         rv770_pcie_gart_fini(rdev);
1959         uvd_v1_0_fini(rdev);
1960         radeon_uvd_fini(rdev);
1961         r600_vram_scratch_fini(rdev);
1962         radeon_gem_fini(rdev);
1963         radeon_fence_driver_fini(rdev);
1964         radeon_agp_fini(rdev);
1965         radeon_bo_fini(rdev);
1966         radeon_atombios_fini(rdev);
1967         kfree(rdev->bios);
1968         rdev->bios = NULL;
1969 }
1970
1971 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1972 {
1973         u32 link_width_cntl, lanes, speed_cntl, tmp;
1974         u16 link_cntl2;
1975
1976         if (radeon_pcie_gen2 == 0)
1977                 return;
1978
1979         if (rdev->flags & RADEON_IS_IGP)
1980                 return;
1981
1982         if (!(rdev->flags & RADEON_IS_PCIE))
1983                 return;
1984
1985         /* x2 cards have a special sequence */
1986         if (ASIC_IS_X2(rdev))
1987                 return;
1988
1989         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
1990                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
1991                 return;
1992
1993         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1994
1995         /* advertise upconfig capability */
1996         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1997         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1998         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1999         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2000         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2001                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2002                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2003                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
2004                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2005                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2006                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2007         } else {
2008                 link_width_cntl |= LC_UPCONFIGURE_DIS;
2009                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2010         }
2011
2012         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2013         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2014             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2015
2016                 tmp = RREG32(0x541c);
2017                 WREG32(0x541c, tmp | 0x8);
2018                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2019                 link_cntl2 = RREG16(0x4088);
2020                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2021                 link_cntl2 |= 0x2;
2022                 WREG16(0x4088, link_cntl2);
2023                 WREG32(MM_CFGREGS_CNTL, 0);
2024
2025                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2026                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2027                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2028
2029                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2030                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2031                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2032
2033                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2034                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2035                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2036
2037                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2038                 speed_cntl |= LC_GEN2_EN_STRAP;
2039                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2040
2041         } else {
2042                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2043                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2044                 if (1)
2045                         link_width_cntl |= LC_UPCONFIGURE_DIS;
2046                 else
2047                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2048                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2049         }
2050 }