drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "rcar_du_crtc.h"
  25 #include "rcar_du_drv.h"
  26 #include "rcar_du_kms.h"
  27 #include "rcar_du_plane.h"
  28 #include "rcar_du_regs.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  61                                  u32 clr, u32 set)
  62 {
  63         struct rcar_du_device *rcdu = rcrtc->group->dev;
  64         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  65
  66         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  67 }
  68
  69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  70 {
  71         int ret;
  72
  73         ret = clk_prepare_enable(rcrtc->clock);
  74         if (ret < 0)
  75                 return ret;
  76
  77         ret = rcar_du_group_get(rcrtc->group);
  78         if (ret < 0)
  79                 clk_disable_unprepare(rcrtc->clock);
  80
  81         return ret;
  82 }
  83
  84 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  85 {
  86         rcar_du_group_put(rcrtc->group);
  87         clk_disable_unprepare(rcrtc->clock);
  88 }
  89
  90 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
  91 {
  92         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  93         unsigned long clk;
  94         u32 value;
  95         u32 div;
  96
  97         /* Dot clock */
  98         clk = clk_get_rate(rcrtc->clock);
  99         div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
 100         div = clamp(div, 1U, 64U) - 1;
 101
 102         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 103                             ESCR_DCLKSEL_CLKS | div);
 104         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 105
 106         /* Signal polarities */
 107         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 108               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 109               | DSMR_DIPM_DE;
 110         rcar_du_crtc_write(rcrtc, DSMR, value);
 111
 112         /* Display timings */
 113         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 114         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 115                                         mode->hdisplay - 19);
 116         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 117                                         mode->hsync_start - 1);
 118         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 119
 120         rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
 121         rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
 122                                         mode->vdisplay - 2);
 123         rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
 124                                         mode->vsync_start - 1);
 125         rcar_du_crtc_write(rcrtc, VCR,  mode->vtotal - 1);
 126
 127         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 128         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 129 }
 130
 131 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 132                                enum rcar_du_output output)
 133 {
 134         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 135         struct rcar_du_device *rcdu = rcrtc->group->dev;
 136
 137         /* Store the route from the CRTC output to the DU output. The DU will be
 138          * configured when starting the CRTC.
 139          */
 140         rcrtc->outputs |= BIT(output);
 141
 142         /* Store RGB routing to DPAD0 for R8A7790. */
 143         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) &&
 144             output == RCAR_DU_OUTPUT_DPAD0)
 145                 rcdu->dpad0_source = rcrtc->index;
 146 }
 147
 148 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 149 {
 150         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 151         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 152         unsigned int num_planes = 0;
 153         unsigned int prio = 0;
 154         unsigned int i;
 155         u32 dptsr = 0;
 156         u32 dspr = 0;
 157
 158         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 159                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 160                 unsigned int j;
 161
 162                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 163                         continue;
 164
 165                 /* Insert the plane in the sorted planes array. */
 166                 for (j = num_planes++; j > 0; --j) {
 167                         if (planes[j-1]->zpos <= plane->zpos)
 168                                 break;
 169                         planes[j] = planes[j-1];
 170                 }
 171
 172                 planes[j] = plane;
 173                 prio += plane->format->planes * 4;
 174         }
 175
 176         for (i = 0; i < num_planes; ++i) {
 177                 struct rcar_du_plane *plane = planes[i];
 178                 unsigned int index = plane->hwindex;
 179
 180                 prio -= 4;
 181                 dspr |= (index + 1) << prio;
 182                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 183
 184                 if (plane->format->planes == 2) {
 185                         index = (index + 1) % 8;
 186
 187                         prio -= 4;
 188                         dspr |= (index + 1) << prio;
 189                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 190                 }
 191         }
 192
 193         /* Select display timing and dot clock generator 2 for planes associated
 194          * with superposition controller 2.
 195          */
 196         if (rcrtc->index % 2) {
 197                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 198
 199                 /* The DPTSR register is updated when the display controller is
 200                  * stopped. We thus need to restart the DU. Once again, sorry
 201                  * for the flicker. One way to mitigate the issue would be to
 202                  * pre-associate planes with CRTCs (either with a fixed 4/4
 203                  * split, or through a module parameter). Flicker would then
 204                  * occur only if we need to break the pre-association.
 205                  */
 206                 if (value != dptsr) {
 207                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 208                         if (rcrtc->group->used_crtcs)
 209                                 rcar_du_group_restart(rcrtc->group);
 210                 }
 211         }
 212
 213         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 214                             dspr);
 215 }
 216
 217 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 218 {
 219         struct drm_crtc *crtc = &rcrtc->crtc;
 220         unsigned int i;
 221
 222         if (rcrtc->started)
 223                 return;
 224
 225         if (WARN_ON(rcrtc->plane->format == NULL))
 226                 return;
 227
 228         /* Set display off and background to black */
 229         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 230         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 231
 232         /* Configure display timings and output routing */
 233         rcar_du_crtc_set_display_timing(rcrtc);
 234         rcar_du_group_set_routing(rcrtc->group);
 235
 236         mutex_lock(&rcrtc->group->planes.lock);
 237         rcrtc->plane->enabled = true;
 238         rcar_du_crtc_update_planes(crtc);
 239         mutex_unlock(&rcrtc->group->planes.lock);
 240
 241         /* Setup planes. */
 242         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 243                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 244
 245                 if (plane->crtc != crtc || !plane->enabled)
 246                         continue;
 247
 248                 rcar_du_plane_setup(plane);
 249         }
 250
 251         /* Select master sync mode. This enables display operation in master
 252          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 253          * actively driven).
 254          */
 255         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
 256
 257         rcar_du_group_start_stop(rcrtc->group, true);
 258
 259         rcrtc->started = true;
 260 }
 261
 262 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 263 {
 264         struct drm_crtc *crtc = &rcrtc->crtc;
 265
 266         if (!rcrtc->started)
 267                 return;
 268
 269         mutex_lock(&rcrtc->group->planes.lock);
 270         rcrtc->plane->enabled = false;
 271         rcar_du_crtc_update_planes(crtc);
 272         mutex_unlock(&rcrtc->group->planes.lock);
 273
 274         /* Select switch sync mode. This stops display operation and configures
 275          * the HSYNC and VSYNC signals as inputs.
 276          */
 277         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 278
 279         rcar_du_group_start_stop(rcrtc->group, false);
 280
 281         rcrtc->started = false;
 282 }
 283
 284 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 285 {
 286         rcar_du_crtc_stop(rcrtc);
 287         rcar_du_crtc_put(rcrtc);
 288 }
 289
 290 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 291 {
 292         if (rcrtc->dpms != DRM_MODE_DPMS_ON)
 293                 return;
 294
 295         rcar_du_crtc_get(rcrtc);
 296         rcar_du_crtc_start(rcrtc);
 297 }
 298
 299 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 300 {
 301         struct drm_crtc *crtc = &rcrtc->crtc;
 302
 303         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 304         rcar_du_plane_update_base(rcrtc->plane);
 305 }
 306
 307 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 308 {
 309         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 310
 311         if (rcrtc->dpms == mode)
 312                 return;
 313
 314         if (mode == DRM_MODE_DPMS_ON) {
 315                 rcar_du_crtc_get(rcrtc);
 316                 rcar_du_crtc_start(rcrtc);
 317         } else {
 318                 rcar_du_crtc_stop(rcrtc);
 319                 rcar_du_crtc_put(rcrtc);
 320         }
 321
 322         rcrtc->dpms = mode;
 323 }
 324
 325 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 326                                     const struct drm_display_mode *mode,
 327                                     struct drm_display_mode *adjusted_mode)
 328 {
 329         /* TODO Fixup modes */
 330         return true;
 331 }
 332
 333 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
 334 {
 335         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 336
 337         /* We need to access the hardware during mode set, acquire a reference
 338          * to the CRTC.
 339          */
 340         rcar_du_crtc_get(rcrtc);
 341
 342         /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
 343          * result.
 344          */
 345         rcar_du_crtc_stop(rcrtc);
 346         rcar_du_plane_release(rcrtc->plane);
 347
 348         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 349 }
 350
 351 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
 352                                  struct drm_display_mode *mode,
 353                                  struct drm_display_mode *adjusted_mode,
 354                                  int x, int y,
 355                                  struct drm_framebuffer *old_fb)
 356 {
 357         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 358         struct rcar_du_device *rcdu = rcrtc->group->dev;
 359         const struct rcar_du_format_info *format;
 360         int ret;
 361
 362         format = rcar_du_format_info(crtc->primary->fb->pixel_format);
 363         if (format == NULL) {
 364                 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
 365                         crtc->primary->fb->pixel_format);
 366                 ret = -EINVAL;
 367                 goto error;
 368         }
 369
 370         ret = rcar_du_plane_reserve(rcrtc->plane, format);
 371         if (ret < 0)
 372                 goto error;
 373
 374         rcrtc->plane->format = format;
 375
 376         rcrtc->plane->src_x = x;
 377         rcrtc->plane->src_y = y;
 378         rcrtc->plane->width = mode->hdisplay;
 379         rcrtc->plane->height = mode->vdisplay;
 380
 381         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 382
 383         rcrtc->outputs = 0;
 384
 385         return 0;
 386
 387 error:
 388         /* There's no rollback/abort operation to clean up in case of error. We
 389          * thus need to release the reference to the CRTC acquired in prepare()
 390          * here.
 391          */
 392         rcar_du_crtc_put(rcrtc);
 393         return ret;
 394 }
 395
 396 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
 397 {
 398         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 399
 400         /* We're done, restart the CRTC and set the DPMS mode to on. The
 401          * reference to the DU acquired at prepare() time will thus be released
 402          * by the DPMS handler (possibly called by the disable() handler).
 403          */
 404         rcar_du_crtc_start(rcrtc);
 405         rcrtc->dpms = DRM_MODE_DPMS_ON;
 406 }
 407
 408 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 409                                       struct drm_framebuffer *old_fb)
 410 {
 411         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 412
 413         rcrtc->plane->src_x = x;
 414         rcrtc->plane->src_y = y;
 415
 416         rcar_du_crtc_update_base(rcrtc);
 417
 418         return 0;
 419 }
 420
 421 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 422 {
 423         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 424
 425         rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 426         rcar_du_plane_release(rcrtc->plane);
 427 }
 428
 429 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 430         .dpms = rcar_du_crtc_dpms,
 431         .mode_fixup = rcar_du_crtc_mode_fixup,
 432         .prepare = rcar_du_crtc_mode_prepare,
 433         .commit = rcar_du_crtc_mode_commit,
 434         .mode_set = rcar_du_crtc_mode_set,
 435         .mode_set_base = rcar_du_crtc_mode_set_base,
 436         .disable = rcar_du_crtc_disable,
 437 };
 438
 439 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 440                                    struct drm_file *file)
 441 {
 442         struct drm_pending_vblank_event *event;
 443         struct drm_device *dev = rcrtc->crtc.dev;
 444         unsigned long flags;
 445
 446         /* Destroy the pending vertical blanking event associated with the
 447          * pending page flip, if any, and disable vertical blanking interrupts.
 448          */
 449         spin_lock_irqsave(&dev->event_lock, flags);
 450         event = rcrtc->event;
 451         if (event && event->base.file_priv == file) {
 452                 rcrtc->event = NULL;
 453                 event->base.destroy(&event->base);
 454                 drm_vblank_put(dev, rcrtc->index);
 455         }
 456         spin_unlock_irqrestore(&dev->event_lock, flags);
 457 }
 458
 459 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 460 {
 461         struct drm_pending_vblank_event *event;
 462         struct drm_device *dev = rcrtc->crtc.dev;
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&dev->event_lock, flags);
 466         event = rcrtc->event;
 467         rcrtc->event = NULL;
 468         spin_unlock_irqrestore(&dev->event_lock, flags);
 469
 470         if (event == NULL)
 471                 return;
 472
 473         spin_lock_irqsave(&dev->event_lock, flags);
 474         drm_send_vblank_event(dev, rcrtc->index, event);
 475         spin_unlock_irqrestore(&dev->event_lock, flags);
 476
 477         drm_vblank_put(dev, rcrtc->index);
 478 }
 479
 480 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 481 {
 482         struct rcar_du_crtc *rcrtc = arg;
 483         irqreturn_t ret = IRQ_NONE;
 484         u32 status;
 485
 486         status = rcar_du_crtc_read(rcrtc, DSSR);
 487         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 488
 489         if (status & DSSR_VBK) {
 490                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 491                 rcar_du_crtc_finish_page_flip(rcrtc);
 492                 ret = IRQ_HANDLED;
 493         }
 494
 495         return ret;
 496 }
 497
 498 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 499                                   struct drm_framebuffer *fb,
 500                                   struct drm_pending_vblank_event *event,
 501                                   uint32_t page_flip_flags)
 502 {
 503         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 504         struct drm_device *dev = rcrtc->crtc.dev;
 505         unsigned long flags;
 506
 507         spin_lock_irqsave(&dev->event_lock, flags);
 508         if (rcrtc->event != NULL) {
 509                 spin_unlock_irqrestore(&dev->event_lock, flags);
 510                 return -EBUSY;
 511         }
 512         spin_unlock_irqrestore(&dev->event_lock, flags);
 513
 514         crtc->primary->fb = fb;
 515         rcar_du_crtc_update_base(rcrtc);
 516
 517         if (event) {
 518                 event->pipe = rcrtc->index;
 519                 drm_vblank_get(dev, rcrtc->index);
 520                 spin_lock_irqsave(&dev->event_lock, flags);
 521                 rcrtc->event = event;
 522                 spin_unlock_irqrestore(&dev->event_lock, flags);
 523         }
 524
 525         return 0;
 526 }
 527
 528 static const struct drm_crtc_funcs crtc_funcs = {
 529         .destroy = drm_crtc_cleanup,
 530         .set_config = drm_crtc_helper_set_config,
 531         .page_flip = rcar_du_crtc_page_flip,
 532 };
 533
 534 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 535 {
 536         static const unsigned int mmio_offsets[] = {
 537                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 538         };
 539
 540         struct rcar_du_device *rcdu = rgrp->dev;
 541         struct platform_device *pdev = to_platform_device(rcdu->dev);
 542         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 543         struct drm_crtc *crtc = &rcrtc->crtc;
 544         unsigned int irqflags;
 545         char clk_name[5];
 546         char *name;
 547         int irq;
 548         int ret;
 549
 550         /* Get the CRTC clock. */
 551         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 552                 sprintf(clk_name, "du.%u", index);
 553                 name = clk_name;
 554         } else {
 555                 name = NULL;
 556         }
 557
 558         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 559         if (IS_ERR(rcrtc->clock)) {
 560                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 561                 return PTR_ERR(rcrtc->clock);
 562         }
 563
 564         rcrtc->group = rgrp;
 565         rcrtc->mmio_offset = mmio_offsets[index];
 566         rcrtc->index = index;
 567         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 568         rcrtc->plane = &rgrp->planes.planes[index % 2];
 569
 570         rcrtc->plane->crtc = crtc;
 571
 572         ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
 573         if (ret < 0)
 574                 return ret;
 575
 576         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 577
 578         /* Register the interrupt handler. */
 579         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 580                 irq = platform_get_irq(pdev, index);
 581                 irqflags = 0;
 582         } else {
 583                 irq = platform_get_irq(pdev, 0);
 584                 irqflags = IRQF_SHARED;
 585         }
 586
 587         if (irq < 0) {
 588                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 589                 return irq;
 590         }
 591
 592         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 593                                dev_name(rcdu->dev), rcrtc);
 594         if (ret < 0) {
 595                 dev_err(rcdu->dev,
 596                         "failed to register IRQ for CRTC %u\n", index);
 597                 return ret;
 598         }
 599
 600         return 0;
 601 }
 602
 603 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 604 {
 605         if (enable) {
 606                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 607                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 608         } else {
 609                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 610         }
 611 }