drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 /*
   2  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/mutex.h>
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23
  24 #include "rcar_du_crtc.h"
  25 #include "rcar_du_drv.h"
  26 #include "rcar_du_kms.h"
  27 #include "rcar_du_plane.h"
  28 #include "rcar_du_regs.h"
  29
  30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  31 {
  32         struct rcar_du_device *rcdu = rcrtc->group->dev;
  33
  34         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  35 }
  36
  37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  38 {
  39         struct rcar_du_device *rcdu = rcrtc->group->dev;
  40
  41         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  42 }
  43
  44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  45 {
  46         struct rcar_du_device *rcdu = rcrtc->group->dev;
  47
  48         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  49                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  50 }
  51
  52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  53 {
  54         struct rcar_du_device *rcdu = rcrtc->group->dev;
  55
  56         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  57                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  58 }
  59
  60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  61                                  u32 clr, u32 set)
  62 {
  63         struct rcar_du_device *rcdu = rcrtc->group->dev;
  64         u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  65
  66         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  67 }
  68
  69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  70 {
  71         int ret;
  72
  73         ret = clk_prepare_enable(rcrtc->clock);
  74         if (ret < 0)
  75                 return ret;
  76
  77         ret = clk_prepare_enable(rcrtc->extclock);
  78         if (ret < 0)
  79                 goto error_clock;
  80
  81         ret = rcar_du_group_get(rcrtc->group);
  82         if (ret < 0)
  83                 goto error_group;
  84
  85         return 0;
  86
  87 error_group:
  88         clk_disable_unprepare(rcrtc->extclock);
  89 error_clock:
  90         clk_disable_unprepare(rcrtc->clock);
  91         return ret;
  92 }
  93
  94 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  95 {
  96         rcar_du_group_put(rcrtc->group);
  97
  98         clk_disable_unprepare(rcrtc->extclock);
  99         clk_disable_unprepare(rcrtc->clock);
 100 }
 101
 102 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 103 {
 104         const struct drm_display_mode *mode = &rcrtc->crtc.mode;
 105         unsigned long mode_clock = mode->clock * 1000;
 106         unsigned long clk;
 107         u32 value;
 108         u32 escr;
 109         u32 div;
 110
 111         /* Compute the clock divisor and select the internal or external dot
 112          * clock based on the requested frequency.
 113          */
 114         clk = clk_get_rate(rcrtc->clock);
 115         div = DIV_ROUND_CLOSEST(clk, mode_clock);
 116         div = clamp(div, 1U, 64U) - 1;
 117         escr = div | ESCR_DCLKSEL_CLKS;
 118
 119         if (rcrtc->extclock) {
 120                 unsigned long extclk;
 121                 unsigned long extrate;
 122                 unsigned long rate;
 123                 u32 extdiv;
 124
 125                 extclk = clk_get_rate(rcrtc->extclock);
 126                 extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
 127                 extdiv = clamp(extdiv, 1U, 64U) - 1;
 128
 129                 rate = clk / (div + 1);
 130                 extrate = extclk / (extdiv + 1);
 131
 132                 if (abs((long)extrate - (long)mode_clock) <
 133                     abs((long)rate - (long)mode_clock)) {
 134                         dev_dbg(rcrtc->group->dev->dev,
 135                                 "crtc%u: using external clock\n", rcrtc->index);
 136                         escr = extdiv | ESCR_DCLKSEL_DCLKIN;
 137                 }
 138         }
 139
 140         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
 141                             escr);
 142         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 143
 144         /* Signal polarities */
 145         value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
 146               | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
 147               | DSMR_DIPM_DE | DSMR_CSPM;
 148         rcar_du_crtc_write(rcrtc, DSMR, value);
 149
 150         /* Display timings */
 151         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 152         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 153                                         mode->hdisplay - 19);
 154         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 155                                         mode->hsync_start - 1);
 156         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 157
 158         rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
 159         rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
 160                                         mode->vdisplay - 2);
 161         rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
 162                                         mode->vsync_start - 1);
 163         rcar_du_crtc_write(rcrtc, VCR,  mode->vtotal - 1);
 164
 165         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);
 166         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 167 }
 168
 169 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
 170                                enum rcar_du_output output)
 171 {
 172         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 173         struct rcar_du_device *rcdu = rcrtc->group->dev;
 174
 175         /* Store the route from the CRTC output to the DU output. The DU will be
 176          * configured when starting the CRTC.
 177          */
 178         rcrtc->outputs |= BIT(output);
 179
 180         /* Store RGB routing to DPAD0, the hardware will be configured when
 181          * starting the CRTC.
 182          */
 183         if (output == RCAR_DU_OUTPUT_DPAD0)
 184                 rcdu->dpad0_source = rcrtc->index;
 185 }
 186
 187 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
 188 {
 189         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 190         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 191         unsigned int num_planes = 0;
 192         unsigned int prio = 0;
 193         unsigned int i;
 194         u32 dptsr = 0;
 195         u32 dspr = 0;
 196
 197         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 198                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 199                 unsigned int j;
 200
 201                 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
 202                         continue;
 203
 204                 /* Insert the plane in the sorted planes array. */
 205                 for (j = num_planes++; j > 0; --j) {
 206                         if (planes[j-1]->zpos <= plane->zpos)
 207                                 break;
 208                         planes[j] = planes[j-1];
 209                 }
 210
 211                 planes[j] = plane;
 212                 prio += plane->format->planes * 4;
 213         }
 214
 215         for (i = 0; i < num_planes; ++i) {
 216                 struct rcar_du_plane *plane = planes[i];
 217                 unsigned int index = plane->hwindex;
 218
 219                 prio -= 4;
 220                 dspr |= (index + 1) << prio;
 221                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 222
 223                 if (plane->format->planes == 2) {
 224                         index = (index + 1) % 8;
 225
 226                         prio -= 4;
 227                         dspr |= (index + 1) << prio;
 228                         dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 229                 }
 230         }
 231
 232         /* Select display timing and dot clock generator 2 for planes associated
 233          * with superposition controller 2.
 234          */
 235         if (rcrtc->index % 2) {
 236                 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
 237
 238                 /* The DPTSR register is updated when the display controller is
 239                  * stopped. We thus need to restart the DU. Once again, sorry
 240                  * for the flicker. One way to mitigate the issue would be to
 241                  * pre-associate planes with CRTCs (either with a fixed 4/4
 242                  * split, or through a module parameter). Flicker would then
 243                  * occur only if we need to break the pre-association.
 244                  */
 245                 if (value != dptsr) {
 246                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
 247                         if (rcrtc->group->used_crtcs)
 248                                 rcar_du_group_restart(rcrtc->group);
 249                 }
 250         }
 251
 252         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 253                             dspr);
 254 }
 255
 256 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 257 {
 258         struct drm_crtc *crtc = &rcrtc->crtc;
 259         unsigned int i;
 260
 261         if (rcrtc->started)
 262                 return;
 263
 264         if (WARN_ON(rcrtc->plane->format == NULL))
 265                 return;
 266
 267         /* Set display off and background to black */
 268         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 269         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 270
 271         /* Configure display timings and output routing */
 272         rcar_du_crtc_set_display_timing(rcrtc);
 273         rcar_du_group_set_routing(rcrtc->group);
 274
 275         mutex_lock(&rcrtc->group->planes.lock);
 276         rcrtc->plane->enabled = true;
 277         rcar_du_crtc_update_planes(crtc);
 278         mutex_unlock(&rcrtc->group->planes.lock);
 279
 280         /* Setup planes. */
 281         for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
 282                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 283
 284                 if (plane->crtc != crtc || !plane->enabled)
 285                         continue;
 286
 287                 rcar_du_plane_setup(plane);
 288         }
 289
 290         /* Select master sync mode. This enables display operation in master
 291          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 292          * actively driven).
 293          */
 294         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
 295
 296         rcar_du_group_start_stop(rcrtc->group, true);
 297
 298         rcrtc->started = true;
 299 }
 300
 301 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 302 {
 303         struct drm_crtc *crtc = &rcrtc->crtc;
 304
 305         if (!rcrtc->started)
 306                 return;
 307
 308         mutex_lock(&rcrtc->group->planes.lock);
 309         rcrtc->plane->enabled = false;
 310         rcar_du_crtc_update_planes(crtc);
 311         mutex_unlock(&rcrtc->group->planes.lock);
 312
 313         /* Select switch sync mode. This stops display operation and configures
 314          * the HSYNC and VSYNC signals as inputs.
 315          */
 316         rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
 317
 318         rcar_du_group_start_stop(rcrtc->group, false);
 319
 320         rcrtc->started = false;
 321 }
 322
 323 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 324 {
 325         rcar_du_crtc_stop(rcrtc);
 326         rcar_du_crtc_put(rcrtc);
 327 }
 328
 329 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 330 {
 331         if (rcrtc->dpms != DRM_MODE_DPMS_ON)
 332                 return;
 333
 334         rcar_du_crtc_get(rcrtc);
 335         rcar_du_crtc_start(rcrtc);
 336 }
 337
 338 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
 339 {
 340         struct drm_crtc *crtc = &rcrtc->crtc;
 341
 342         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 343         rcar_du_plane_update_base(rcrtc->plane);
 344 }
 345
 346 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
 347 {
 348         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 349
 350         if (rcrtc->dpms == mode)
 351                 return;
 352
 353         if (mode == DRM_MODE_DPMS_ON) {
 354                 rcar_du_crtc_get(rcrtc);
 355                 rcar_du_crtc_start(rcrtc);
 356         } else {
 357                 rcar_du_crtc_stop(rcrtc);
 358                 rcar_du_crtc_put(rcrtc);
 359         }
 360
 361         rcrtc->dpms = mode;
 362 }
 363
 364 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
 365                                     const struct drm_display_mode *mode,
 366                                     struct drm_display_mode *adjusted_mode)
 367 {
 368         /* TODO Fixup modes */
 369         return true;
 370 }
 371
 372 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
 373 {
 374         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 375
 376         /* We need to access the hardware during mode set, acquire a reference
 377          * to the CRTC.
 378          */
 379         rcar_du_crtc_get(rcrtc);
 380
 381         /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
 382          * result.
 383          */
 384         rcar_du_crtc_stop(rcrtc);
 385         rcar_du_plane_release(rcrtc->plane);
 386
 387         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 388 }
 389
 390 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
 391                                  struct drm_display_mode *mode,
 392                                  struct drm_display_mode *adjusted_mode,
 393                                  int x, int y,
 394                                  struct drm_framebuffer *old_fb)
 395 {
 396         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 397         struct rcar_du_device *rcdu = rcrtc->group->dev;
 398         const struct rcar_du_format_info *format;
 399         int ret;
 400
 401         format = rcar_du_format_info(crtc->primary->fb->pixel_format);
 402         if (format == NULL) {
 403                 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
 404                         crtc->primary->fb->pixel_format);
 405                 ret = -EINVAL;
 406                 goto error;
 407         }
 408
 409         ret = rcar_du_plane_reserve(rcrtc->plane, format);
 410         if (ret < 0)
 411                 goto error;
 412
 413         rcrtc->plane->format = format;
 414
 415         rcrtc->plane->src_x = x;
 416         rcrtc->plane->src_y = y;
 417         rcrtc->plane->width = mode->hdisplay;
 418         rcrtc->plane->height = mode->vdisplay;
 419
 420         rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
 421
 422         rcrtc->outputs = 0;
 423
 424         return 0;
 425
 426 error:
 427         /* There's no rollback/abort operation to clean up in case of error. We
 428          * thus need to release the reference to the CRTC acquired in prepare()
 429          * here.
 430          */
 431         rcar_du_crtc_put(rcrtc);
 432         return ret;
 433 }
 434
 435 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
 436 {
 437         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 438
 439         /* We're done, restart the CRTC and set the DPMS mode to on. The
 440          * reference to the DU acquired at prepare() time will thus be released
 441          * by the DPMS handler (possibly called by the disable() handler).
 442          */
 443         rcar_du_crtc_start(rcrtc);
 444         rcrtc->dpms = DRM_MODE_DPMS_ON;
 445 }
 446
 447 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 448                                       struct drm_framebuffer *old_fb)
 449 {
 450         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 451
 452         rcrtc->plane->src_x = x;
 453         rcrtc->plane->src_y = y;
 454
 455         rcar_du_crtc_update_base(rcrtc);
 456
 457         return 0;
 458 }
 459
 460 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 461 {
 462         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 463
 464         rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 465         rcar_du_plane_release(rcrtc->plane);
 466 }
 467
 468 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 469         .dpms = rcar_du_crtc_dpms,
 470         .mode_fixup = rcar_du_crtc_mode_fixup,
 471         .prepare = rcar_du_crtc_mode_prepare,
 472         .commit = rcar_du_crtc_mode_commit,
 473         .mode_set = rcar_du_crtc_mode_set,
 474         .mode_set_base = rcar_du_crtc_mode_set_base,
 475         .disable = rcar_du_crtc_disable,
 476 };
 477
 478 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
 479                                    struct drm_file *file)
 480 {
 481         struct drm_pending_vblank_event *event;
 482         struct drm_device *dev = rcrtc->crtc.dev;
 483         unsigned long flags;
 484
 485         /* Destroy the pending vertical blanking event associated with the
 486          * pending page flip, if any, and disable vertical blanking interrupts.
 487          */
 488         spin_lock_irqsave(&dev->event_lock, flags);
 489         event = rcrtc->event;
 490         if (event && event->base.file_priv == file) {
 491                 rcrtc->event = NULL;
 492                 event->base.destroy(&event->base);
 493                 drm_vblank_put(dev, rcrtc->index);
 494         }
 495         spin_unlock_irqrestore(&dev->event_lock, flags);
 496 }
 497
 498 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 499 {
 500         struct drm_pending_vblank_event *event;
 501         struct drm_device *dev = rcrtc->crtc.dev;
 502         unsigned long flags;
 503
 504         spin_lock_irqsave(&dev->event_lock, flags);
 505         event = rcrtc->event;
 506         rcrtc->event = NULL;
 507         spin_unlock_irqrestore(&dev->event_lock, flags);
 508
 509         if (event == NULL)
 510                 return;
 511
 512         spin_lock_irqsave(&dev->event_lock, flags);
 513         drm_send_vblank_event(dev, rcrtc->index, event);
 514         spin_unlock_irqrestore(&dev->event_lock, flags);
 515
 516         drm_vblank_put(dev, rcrtc->index);
 517 }
 518
 519 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 520 {
 521         struct rcar_du_crtc *rcrtc = arg;
 522         irqreturn_t ret = IRQ_NONE;
 523         u32 status;
 524
 525         status = rcar_du_crtc_read(rcrtc, DSSR);
 526         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
 527
 528         if (status & DSSR_VBK) {
 529                 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
 530                 rcar_du_crtc_finish_page_flip(rcrtc);
 531                 ret = IRQ_HANDLED;
 532         }
 533
 534         return ret;
 535 }
 536
 537 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
 538                                   struct drm_framebuffer *fb,
 539                                   struct drm_pending_vblank_event *event,
 540                                   uint32_t page_flip_flags)
 541 {
 542         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 543         struct drm_device *dev = rcrtc->crtc.dev;
 544         unsigned long flags;
 545
 546         spin_lock_irqsave(&dev->event_lock, flags);
 547         if (rcrtc->event != NULL) {
 548                 spin_unlock_irqrestore(&dev->event_lock, flags);
 549                 return -EBUSY;
 550         }
 551         spin_unlock_irqrestore(&dev->event_lock, flags);
 552
 553         crtc->primary->fb = fb;
 554         rcar_du_crtc_update_base(rcrtc);
 555
 556         if (event) {
 557                 event->pipe = rcrtc->index;
 558                 drm_vblank_get(dev, rcrtc->index);
 559                 spin_lock_irqsave(&dev->event_lock, flags);
 560                 rcrtc->event = event;
 561                 spin_unlock_irqrestore(&dev->event_lock, flags);
 562         }
 563
 564         return 0;
 565 }
 566
 567 static const struct drm_crtc_funcs crtc_funcs = {
 568         .destroy = drm_crtc_cleanup,
 569         .set_config = drm_crtc_helper_set_config,
 570         .page_flip = rcar_du_crtc_page_flip,
 571 };
 572
 573 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 574 {
 575         static const unsigned int mmio_offsets[] = {
 576                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
 577         };
 578
 579         struct rcar_du_device *rcdu = rgrp->dev;
 580         struct platform_device *pdev = to_platform_device(rcdu->dev);
 581         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
 582         struct drm_crtc *crtc = &rcrtc->crtc;
 583         unsigned int irqflags;
 584         struct clk *clk;
 585         char clk_name[9];
 586         char *name;
 587         int irq;
 588         int ret;
 589
 590         /* Get the CRTC clock and the optional external clock. */
 591         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 592                 sprintf(clk_name, "du.%u", index);
 593                 name = clk_name;
 594         } else {
 595                 name = NULL;
 596         }
 597
 598         rcrtc->clock = devm_clk_get(rcdu->dev, name);
 599         if (IS_ERR(rcrtc->clock)) {
 600                 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
 601                 return PTR_ERR(rcrtc->clock);
 602         }
 603
 604         sprintf(clk_name, "dclkin.%u", index);
 605         clk = devm_clk_get(rcdu->dev, clk_name);
 606         if (!IS_ERR(clk)) {
 607                 rcrtc->extclock = clk;
 608         } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
 609                 dev_info(rcdu->dev, "can't get external clock %u\n", index);
 610                 return -EPROBE_DEFER;
 611         }
 612
 613         rcrtc->group = rgrp;
 614         rcrtc->mmio_offset = mmio_offsets[index];
 615         rcrtc->index = index;
 616         rcrtc->dpms = DRM_MODE_DPMS_OFF;
 617         rcrtc->plane = &rgrp->planes.planes[index % 2];
 618
 619         rcrtc->plane->crtc = crtc;
 620
 621         ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
 622         if (ret < 0)
 623                 return ret;
 624
 625         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 626
 627         /* Register the interrupt handler. */
 628         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
 629                 irq = platform_get_irq(pdev, index);
 630                 irqflags = 0;
 631         } else {
 632                 irq = platform_get_irq(pdev, 0);
 633                 irqflags = IRQF_SHARED;
 634         }
 635
 636         if (irq < 0) {
 637                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
 638                 return irq;
 639         }
 640
 641         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
 642                                dev_name(rcdu->dev), rcrtc);
 643         if (ret < 0) {
 644                 dev_err(rcdu->dev,
 645                         "failed to register IRQ for CRTC %u\n", index);
 646                 return ret;
 647         }
 648
 649         return 0;
 650 }
 651
 652 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
 653 {
 654         if (enable) {
 655                 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 656                 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 657         } else {
 658                 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 659         }
 660 }