drivers/gpu/drm/tegra/gr3d.c

   1 /*
   2  * Copyright (C) 2013 Avionic Design GmbH
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/host1x.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15 #include <linux/tegra-powergate.h>
  16
  17 #include "drm.h"
  18 #include "gem.h"
  19 #include "gr3d.h"
  20
  21 struct gr3d {
  22         struct tegra_drm_client client;
  23         struct host1x_channel *channel;
  24         struct clk *clk_secondary;
  25         struct clk *clk;
  26         struct reset_control *rst_secondary;
  27         struct reset_control *rst;
  28
  29         DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
  30 };
  31
  32 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
  33 {
  34         return container_of(client, struct gr3d, client);
  35 }
  36
  37 static int gr3d_init(struct host1x_client *client)
  38 {
  39         struct tegra_drm_client *drm = host1x_to_drm_client(client);
  40         struct drm_device *dev = dev_get_drvdata(client->parent);
  41         unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
  42         struct gr3d *gr3d = to_gr3d(drm);
  43
  44         gr3d->channel = host1x_channel_request(client->dev);
  45         if (!gr3d->channel)
  46                 return -ENOMEM;
  47
  48         client->syncpts[0] = host1x_syncpt_request(client->dev, flags);
  49         if (!client->syncpts[0]) {
  50                 host1x_channel_free(gr3d->channel);
  51                 return -ENOMEM;
  52         }
  53
  54         return tegra_drm_register_client(dev->dev_private, drm);
  55 }
  56
  57 static int gr3d_exit(struct host1x_client *client)
  58 {
  59         struct tegra_drm_client *drm = host1x_to_drm_client(client);
  60         struct drm_device *dev = dev_get_drvdata(client->parent);
  61         struct gr3d *gr3d = to_gr3d(drm);
  62         int err;
  63
  64         err = tegra_drm_unregister_client(dev->dev_private, drm);
  65         if (err < 0)
  66                 return err;
  67
  68         host1x_syncpt_free(client->syncpts[0]);
  69         host1x_channel_free(gr3d->channel);
  70
  71         return 0;
  72 }
  73
  74 static const struct host1x_client_ops gr3d_client_ops = {
  75         .init = gr3d_init,
  76         .exit = gr3d_exit,
  77 };
  78
  79 static int gr3d_open_channel(struct tegra_drm_client *client,
  80                              struct tegra_drm_context *context)
  81 {
  82         struct gr3d *gr3d = to_gr3d(client);
  83
  84         context->channel = host1x_channel_get(gr3d->channel);
  85         if (!context->channel)
  86                 return -ENOMEM;
  87
  88         return 0;
  89 }
  90
  91 static void gr3d_close_channel(struct tegra_drm_context *context)
  92 {
  93         host1x_channel_put(context->channel);
  94 }
  95
  96 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
  97 {
  98         struct gr3d *gr3d = dev_get_drvdata(dev);
  99
 100         switch (class) {
 101         case HOST1X_CLASS_HOST1X:
 102                 if (offset == 0x2b)
 103                         return 1;
 104
 105                 break;
 106
 107         case HOST1X_CLASS_GR3D:
 108                 if (offset >= GR3D_NUM_REGS)
 109                         break;
 110
 111                 if (test_bit(offset, gr3d->addr_regs))
 112                         return 1;
 113
 114                 break;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static const struct tegra_drm_client_ops gr3d_ops = {
 121         .open_channel = gr3d_open_channel,
 122         .close_channel = gr3d_close_channel,
 123         .is_addr_reg = gr3d_is_addr_reg,
 124         .submit = tegra_drm_submit,
 125 };
 126
 127 static const struct of_device_id tegra_gr3d_match[] = {
 128         { .compatible = "nvidia,tegra114-gr3d" },
 129         { .compatible = "nvidia,tegra30-gr3d" },
 130         { .compatible = "nvidia,tegra20-gr3d" },
 131         { }
 132 };
 133
 134 static const u32 gr3d_addr_regs[] = {
 135         GR3D_IDX_ATTRIBUTE( 0),
 136         GR3D_IDX_ATTRIBUTE( 1),
 137         GR3D_IDX_ATTRIBUTE( 2),
 138         GR3D_IDX_ATTRIBUTE( 3),
 139         GR3D_IDX_ATTRIBUTE( 4),
 140         GR3D_IDX_ATTRIBUTE( 5),
 141         GR3D_IDX_ATTRIBUTE( 6),
 142         GR3D_IDX_ATTRIBUTE( 7),
 143         GR3D_IDX_ATTRIBUTE( 8),
 144         GR3D_IDX_ATTRIBUTE( 9),
 145         GR3D_IDX_ATTRIBUTE(10),
 146         GR3D_IDX_ATTRIBUTE(11),
 147         GR3D_IDX_ATTRIBUTE(12),
 148         GR3D_IDX_ATTRIBUTE(13),
 149         GR3D_IDX_ATTRIBUTE(14),
 150         GR3D_IDX_ATTRIBUTE(15),
 151         GR3D_IDX_INDEX_BASE,
 152         GR3D_QR_ZTAG_ADDR,
 153         GR3D_QR_CTAG_ADDR,
 154         GR3D_QR_CZ_ADDR,
 155         GR3D_TEX_TEX_ADDR( 0),
 156         GR3D_TEX_TEX_ADDR( 1),
 157         GR3D_TEX_TEX_ADDR( 2),
 158         GR3D_TEX_TEX_ADDR( 3),
 159         GR3D_TEX_TEX_ADDR( 4),
 160         GR3D_TEX_TEX_ADDR( 5),
 161         GR3D_TEX_TEX_ADDR( 6),
 162         GR3D_TEX_TEX_ADDR( 7),
 163         GR3D_TEX_TEX_ADDR( 8),
 164         GR3D_TEX_TEX_ADDR( 9),
 165         GR3D_TEX_TEX_ADDR(10),
 166         GR3D_TEX_TEX_ADDR(11),
 167         GR3D_TEX_TEX_ADDR(12),
 168         GR3D_TEX_TEX_ADDR(13),
 169         GR3D_TEX_TEX_ADDR(14),
 170         GR3D_TEX_TEX_ADDR(15),
 171         GR3D_DW_MEMORY_OUTPUT_ADDRESS,
 172         GR3D_GLOBAL_SURFADDR( 0),
 173         GR3D_GLOBAL_SURFADDR( 1),
 174         GR3D_GLOBAL_SURFADDR( 2),
 175         GR3D_GLOBAL_SURFADDR( 3),
 176         GR3D_GLOBAL_SURFADDR( 4),
 177         GR3D_GLOBAL_SURFADDR( 5),
 178         GR3D_GLOBAL_SURFADDR( 6),
 179         GR3D_GLOBAL_SURFADDR( 7),
 180         GR3D_GLOBAL_SURFADDR( 8),
 181         GR3D_GLOBAL_SURFADDR( 9),
 182         GR3D_GLOBAL_SURFADDR(10),
 183         GR3D_GLOBAL_SURFADDR(11),
 184         GR3D_GLOBAL_SURFADDR(12),
 185         GR3D_GLOBAL_SURFADDR(13),
 186         GR3D_GLOBAL_SURFADDR(14),
 187         GR3D_GLOBAL_SURFADDR(15),
 188         GR3D_GLOBAL_SPILLSURFADDR,
 189         GR3D_GLOBAL_SURFOVERADDR( 0),
 190         GR3D_GLOBAL_SURFOVERADDR( 1),
 191         GR3D_GLOBAL_SURFOVERADDR( 2),
 192         GR3D_GLOBAL_SURFOVERADDR( 3),
 193         GR3D_GLOBAL_SURFOVERADDR( 4),
 194         GR3D_GLOBAL_SURFOVERADDR( 5),
 195         GR3D_GLOBAL_SURFOVERADDR( 6),
 196         GR3D_GLOBAL_SURFOVERADDR( 7),
 197         GR3D_GLOBAL_SURFOVERADDR( 8),
 198         GR3D_GLOBAL_SURFOVERADDR( 9),
 199         GR3D_GLOBAL_SURFOVERADDR(10),
 200         GR3D_GLOBAL_SURFOVERADDR(11),
 201         GR3D_GLOBAL_SURFOVERADDR(12),
 202         GR3D_GLOBAL_SURFOVERADDR(13),
 203         GR3D_GLOBAL_SURFOVERADDR(14),
 204         GR3D_GLOBAL_SURFOVERADDR(15),
 205         GR3D_GLOBAL_SAMP01SURFADDR( 0),
 206         GR3D_GLOBAL_SAMP01SURFADDR( 1),
 207         GR3D_GLOBAL_SAMP01SURFADDR( 2),
 208         GR3D_GLOBAL_SAMP01SURFADDR( 3),
 209         GR3D_GLOBAL_SAMP01SURFADDR( 4),
 210         GR3D_GLOBAL_SAMP01SURFADDR( 5),
 211         GR3D_GLOBAL_SAMP01SURFADDR( 6),
 212         GR3D_GLOBAL_SAMP01SURFADDR( 7),
 213         GR3D_GLOBAL_SAMP01SURFADDR( 8),
 214         GR3D_GLOBAL_SAMP01SURFADDR( 9),
 215         GR3D_GLOBAL_SAMP01SURFADDR(10),
 216         GR3D_GLOBAL_SAMP01SURFADDR(11),
 217         GR3D_GLOBAL_SAMP01SURFADDR(12),
 218         GR3D_GLOBAL_SAMP01SURFADDR(13),
 219         GR3D_GLOBAL_SAMP01SURFADDR(14),
 220         GR3D_GLOBAL_SAMP01SURFADDR(15),
 221         GR3D_GLOBAL_SAMP23SURFADDR( 0),
 222         GR3D_GLOBAL_SAMP23SURFADDR( 1),
 223         GR3D_GLOBAL_SAMP23SURFADDR( 2),
 224         GR3D_GLOBAL_SAMP23SURFADDR( 3),
 225         GR3D_GLOBAL_SAMP23SURFADDR( 4),
 226         GR3D_GLOBAL_SAMP23SURFADDR( 5),
 227         GR3D_GLOBAL_SAMP23SURFADDR( 6),
 228         GR3D_GLOBAL_SAMP23SURFADDR( 7),
 229         GR3D_GLOBAL_SAMP23SURFADDR( 8),
 230         GR3D_GLOBAL_SAMP23SURFADDR( 9),
 231         GR3D_GLOBAL_SAMP23SURFADDR(10),
 232         GR3D_GLOBAL_SAMP23SURFADDR(11),
 233         GR3D_GLOBAL_SAMP23SURFADDR(12),
 234         GR3D_GLOBAL_SAMP23SURFADDR(13),
 235         GR3D_GLOBAL_SAMP23SURFADDR(14),
 236         GR3D_GLOBAL_SAMP23SURFADDR(15),
 237 };
 238
 239 static int gr3d_probe(struct platform_device *pdev)
 240 {
 241         struct device_node *np = pdev->dev.of_node;
 242         struct host1x_syncpt **syncpts;
 243         struct gr3d *gr3d;
 244         unsigned int i;
 245         int err;
 246
 247         gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
 248         if (!gr3d)
 249                 return -ENOMEM;
 250
 251         syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
 252         if (!syncpts)
 253                 return -ENOMEM;
 254
 255         gr3d->clk = devm_clk_get(&pdev->dev, NULL);
 256         if (IS_ERR(gr3d->clk)) {
 257                 dev_err(&pdev->dev, "cannot get clock\n");
 258                 return PTR_ERR(gr3d->clk);
 259         }
 260
 261         gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
 262         if (IS_ERR(gr3d->rst)) {
 263                 dev_err(&pdev->dev, "cannot get reset\n");
 264                 return PTR_ERR(gr3d->rst);
 265         }
 266
 267         if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
 268                 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
 269                 if (IS_ERR(gr3d->clk)) {
 270                         dev_err(&pdev->dev, "cannot get secondary clock\n");
 271                         return PTR_ERR(gr3d->clk);
 272                 }
 273
 274                 gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
 275                                                                 "3d2");
 276                 if (IS_ERR(gr3d->rst_secondary)) {
 277                         dev_err(&pdev->dev, "cannot get secondary reset\n");
 278                         return PTR_ERR(gr3d->rst_secondary);
 279                 }
 280         }
 281
 282         err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
 283                                                 gr3d->rst);
 284         if (err < 0) {
 285                 dev_err(&pdev->dev, "failed to power up 3D unit\n");
 286                 return err;
 287         }
 288
 289         if (gr3d->clk_secondary) {
 290                 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
 291                                                         gr3d->clk_secondary,
 292                                                         gr3d->rst_secondary);
 293                 if (err < 0) {
 294                         dev_err(&pdev->dev,
 295                                 "failed to power up secondary 3D unit\n");
 296                         return err;
 297                 }
 298         }
 299
 300         INIT_LIST_HEAD(&gr3d->client.base.list);
 301         gr3d->client.base.ops = &gr3d_client_ops;
 302         gr3d->client.base.dev = &pdev->dev;
 303         gr3d->client.base.class = HOST1X_CLASS_GR3D;
 304         gr3d->client.base.syncpts = syncpts;
 305         gr3d->client.base.num_syncpts = 1;
 306
 307         INIT_LIST_HEAD(&gr3d->client.list);
 308         gr3d->client.ops = &gr3d_ops;
 309
 310         err = host1x_client_register(&gr3d->client.base);
 311         if (err < 0) {
 312                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
 313                         err);
 314                 return err;
 315         }
 316
 317         /* initialize address register map */
 318         for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
 319                 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
 320
 321         platform_set_drvdata(pdev, gr3d);
 322
 323         return 0;
 324 }
 325
 326 static int gr3d_remove(struct platform_device *pdev)
 327 {
 328         struct gr3d *gr3d = platform_get_drvdata(pdev);
 329         int err;
 330
 331         err = host1x_client_unregister(&gr3d->client.base);
 332         if (err < 0) {
 333                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
 334                         err);
 335                 return err;
 336         }
 337
 338         if (gr3d->clk_secondary) {
 339                 tegra_powergate_power_off(TEGRA_POWERGATE_3D1);
 340                 clk_disable_unprepare(gr3d->clk_secondary);
 341         }
 342
 343         tegra_powergate_power_off(TEGRA_POWERGATE_3D);
 344         clk_disable_unprepare(gr3d->clk);
 345
 346         return 0;
 347 }
 348
 349 struct platform_driver tegra_gr3d_driver = {
 350         .driver = {
 351                 .name = "tegra-gr3d",
 352                 .of_match_table = tegra_gr3d_match,
 353         },
 354         .probe = gr3d_probe,
 355         .remove = gr3d_remove,
 356 };