drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "drm_fb_cma_helper.h"
  39 #include "linux/component.h"
  40 #include "linux/of_device.h"
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc {
  45         struct drm_crtc base;
  46         const struct vc4_crtc_data *data;
  47         void __iomem *regs;
  48
  49         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  50         ktime_t t_vblank;
  51
  52         /* Which HVS channel we're using for our CRTC. */
  53         int channel;
  54
  55         u8 lut_r[256];
  56         u8 lut_g[256];
  57         u8 lut_b[256];
  58         /* Size in pixels of the COB memory allocated to this CRTC. */
  59         u32 cob_size;
  60
  61         struct drm_pending_vblank_event *event;
  62 };
  63
  64 struct vc4_crtc_state {
  65         struct drm_crtc_state base;
  66         /* Dlist area for this CRTC configuration. */
  67         struct drm_mm_node mm;
  68 };
  69
  70 static inline struct vc4_crtc *
  71 to_vc4_crtc(struct drm_crtc *crtc)
  72 {
  73         return (struct vc4_crtc *)crtc;
  74 }
  75
  76 static inline struct vc4_crtc_state *
  77 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  78 {
  79         return (struct vc4_crtc_state *)crtc_state;
  80 }
  81
  82 struct vc4_crtc_data {
  83         /* Which channel of the HVS this pixelvalve sources from. */
  84         int hvs_channel;
  85
  86         enum vc4_encoder_type encoder0_type;
  87         enum vc4_encoder_type encoder1_type;
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                             unsigned int flags, int *vpos, int *hpos,
 156                             ktime_t *stime, ktime_t *etime,
 157                             const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 161         u32 val;
 162         int fifo_lines;
 163         int vblank_lines;
 164         int ret = 0;
 165
 166         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 167
 168         /* Get optional system timestamp before query. */
 169         if (stime)
 170                 *stime = ktime_get();
 171
 172         /*
 173          * Read vertical scanline which is currently composed for our
 174          * pixelvalve by the HVS, and also the scaler status.
 175          */
 176         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 177
 178         /* Get optional system timestamp after query. */
 179         if (etime)
 180                 *etime = ktime_get();
 181
 182         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 183
 184         /* Vertical position of hvs composed scanline. */
 185         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 186         *hpos = 0;
 187
 188         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 189                 *vpos /= 2;
 190
 191                 /* Use hpos to correct for field offset in interlaced mode. */
 192                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 193                         *hpos += mode->crtc_htotal / 2;
 194         }
 195
 196         /* This is the offset we need for translating hvs -> pv scanout pos. */
 197         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 198
 199         if (fifo_lines > 0)
 200                 ret |= DRM_SCANOUTPOS_VALID;
 201
 202         /* HVS more than fifo_lines into frame for compositing? */
 203         if (*vpos > fifo_lines) {
 204                 /*
 205                  * We are in active scanout and can get some meaningful results
 206                  * from HVS. The actual PV scanout can not trail behind more
 207                  * than fifo_lines as that is the fifo's capacity. Assume that
 208                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 209                  * refilling the fifo and PV consuming from the fifo, ie.
 210                  * whenever the PV consumes and frees up a scanline in the
 211                  * fifo, the HVS will immediately refill it, therefore
 212                  * incrementing vpos. Therefore we choose HVS read position -
 213                  * fifo size in scanlines as a estimate of the real scanout
 214                  * position of the PV.
 215                  */
 216                 *vpos -= fifo_lines + 1;
 217
 218                 ret |= DRM_SCANOUTPOS_ACCURATE;
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         ret |= DRM_SCANOUTPOS_IN_VBLANK;
 232         vblank_lines = mode->vtotal - mode->vdisplay;
 233
 234         if (flags & DRM_CALLED_FROM_VBLIRQ) {
 235                 /*
 236                  * Assume the irq handler got called close to first
 237                  * line of vblank, so PV has about a full vblank
 238                  * scanlines to go, and as a base timestamp use the
 239                  * one taken at entry into vblank irq handler, so it
 240                  * is not affected by random delays due to lock
 241                  * contention on event_lock or vblank_time lock in
 242                  * the core.
 243                  */
 244                 *vpos = -vblank_lines;
 245
 246                 if (stime)
 247                         *stime = vc4_crtc->t_vblank;
 248                 if (etime)
 249                         *etime = vc4_crtc->t_vblank;
 250
 251                 /*
 252                  * If the HVS fifo is not yet full then we know for certain
 253                  * we are at the very beginning of vblank, as the hvs just
 254                  * started refilling, and the stime and etime timestamps
 255                  * truly correspond to start of vblank.
 256                  */
 257                 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
 258                         ret |= DRM_SCANOUTPOS_ACCURATE;
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 273                                   int *max_error, struct timeval *vblank_time,
 274                                   unsigned flags)
 275 {
 276         struct vc4_dev *vc4 = to_vc4_dev(dev);
 277         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 278         struct drm_crtc *crtc = &vc4_crtc->base;
 279         struct drm_crtc_state *state = crtc->state;
 280
 281         /* Helper routine in DRM core does all the work: */
 282         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
 283                                                      vblank_time, flags,
 284                                                      &state->adjusted_mode);
 285 }
 286
 287 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 288 {
 289         drm_crtc_cleanup(crtc);
 290 }
 291
 292 static void
 293 vc4_crtc_lut_load(struct drm_crtc *crtc)
 294 {
 295         struct drm_device *dev = crtc->dev;
 296         struct vc4_dev *vc4 = to_vc4_dev(dev);
 297         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 298         u32 i;
 299
 300         /* The LUT memory is laid out with each HVS channel in order,
 301          * each of which takes 256 writes for R, 256 for G, then 256
 302          * for B.
 303          */
 304         HVS_WRITE(SCALER_GAMADDR,
 305                   SCALER_GAMADDR_AUTOINC |
 306                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 307
 308         for (i = 0; i < crtc->gamma_size; i++)
 309                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 310         for (i = 0; i < crtc->gamma_size; i++)
 311                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 312         for (i = 0; i < crtc->gamma_size; i++)
 313                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 314 }
 315
 316 static int
 317 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 318                    uint32_t size)
 319 {
 320         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 321         u32 i;
 322
 323         for (i = 0; i < size; i++) {
 324                 vc4_crtc->lut_r[i] = r[i] >> 8;
 325                 vc4_crtc->lut_g[i] = g[i] >> 8;
 326                 vc4_crtc->lut_b[i] = b[i] >> 8;
 327         }
 328
 329         vc4_crtc_lut_load(crtc);
 330
 331         return 0;
 332 }
 333
 334 static u32 vc4_get_fifo_full_level(u32 format)
 335 {
 336         static const u32 fifo_len_bytes = 64;
 337         static const u32 hvs_latency_pix = 6;
 338
 339         switch (format) {
 340         case PV_CONTROL_FORMAT_DSIV_16:
 341         case PV_CONTROL_FORMAT_DSIC_16:
 342                 return fifo_len_bytes - 2 * hvs_latency_pix;
 343         case PV_CONTROL_FORMAT_DSIV_18:
 344                 return fifo_len_bytes - 14;
 345         case PV_CONTROL_FORMAT_24:
 346         case PV_CONTROL_FORMAT_DSIV_24:
 347         default:
 348                 return fifo_len_bytes - 3 * hvs_latency_pix;
 349         }
 350 }
 351
 352 /*
 353  * Returns the clock select bit for the connector attached to the
 354  * CRTC.
 355  */
 356 static int vc4_get_clock_select(struct drm_crtc *crtc)
 357 {
 358         struct drm_connector *connector;
 359
 360         drm_for_each_connector(connector, crtc->dev) {
 361                 if (connector->state->crtc == crtc) {
 362                         struct drm_encoder *encoder = connector->encoder;
 363                         struct vc4_encoder *vc4_encoder =
 364                                 to_vc4_encoder(encoder);
 365
 366                         return vc4_encoder->clock_select;
 367                 }
 368         }
 369
 370         return -1;
 371 }
 372
 373 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 374 {
 375         struct drm_device *dev = crtc->dev;
 376         struct vc4_dev *vc4 = to_vc4_dev(dev);
 377         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 378         struct drm_crtc_state *state = crtc->state;
 379         struct drm_display_mode *mode = &state->adjusted_mode;
 380         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 381         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 382         u32 format = PV_CONTROL_FORMAT_24;
 383         bool debug_dump_regs = false;
 384         int clock_select = vc4_get_clock_select(crtc);
 385
 386         if (debug_dump_regs) {
 387                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 388                 vc4_crtc_dump_regs(vc4_crtc);
 389         }
 390
 391         /* Reset the PV fifo. */
 392         CRTC_WRITE(PV_CONTROL, 0);
 393         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 394         CRTC_WRITE(PV_CONTROL, 0);
 395
 396         CRTC_WRITE(PV_HORZA,
 397                    VC4_SET_FIELD((mode->htotal -
 398                                   mode->hsync_end) * pixel_rep,
 399                                  PV_HORZA_HBP) |
 400                    VC4_SET_FIELD((mode->hsync_end -
 401                                   mode->hsync_start) * pixel_rep,
 402                                  PV_HORZA_HSYNC));
 403         CRTC_WRITE(PV_HORZB,
 404                    VC4_SET_FIELD((mode->hsync_start -
 405                                   mode->hdisplay) * pixel_rep,
 406                                  PV_HORZB_HFP) |
 407                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 408
 409         CRTC_WRITE(PV_VERTA,
 410                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 411                                  PV_VERTA_VBP) |
 412                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 413                                  PV_VERTA_VSYNC));
 414         CRTC_WRITE(PV_VERTB,
 415                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 416                                  PV_VERTB_VFP) |
 417                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 418
 419         if (interlace) {
 420                 CRTC_WRITE(PV_VERTA_EVEN,
 421                            VC4_SET_FIELD(mode->crtc_vtotal -
 422                                          mode->crtc_vsync_end - 1,
 423                                          PV_VERTA_VBP) |
 424                            VC4_SET_FIELD(mode->crtc_vsync_end -
 425                                          mode->crtc_vsync_start,
 426                                          PV_VERTA_VSYNC));
 427                 CRTC_WRITE(PV_VERTB_EVEN,
 428                            VC4_SET_FIELD(mode->crtc_vsync_start -
 429                                          mode->crtc_vdisplay,
 430                                          PV_VERTB_VFP) |
 431                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 432
 433                 /* We set up first field even mode for HDMI.  VEC's
 434                  * NTSC mode would want first field odd instead, once
 435                  * we support it (to do so, set ODD_FIRST and put the
 436                  * delay in VSYNCD_EVEN instead).
 437                  */
 438                 CRTC_WRITE(PV_V_CONTROL,
 439                            PV_VCONTROL_CONTINUOUS |
 440                            PV_VCONTROL_INTERLACE |
 441                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 442                                          PV_VCONTROL_ODD_DELAY));
 443                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 444         } else {
 445                 CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
 446         }
 447
 448         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 449
 450
 451         CRTC_WRITE(PV_CONTROL,
 452                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 453                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 454                                  PV_CONTROL_FIFO_LEVEL) |
 455                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 456                    PV_CONTROL_CLR_AT_START |
 457                    PV_CONTROL_TRIGGER_UNDERFLOW |
 458                    PV_CONTROL_WAIT_HSTART |
 459                    VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
 460                    PV_CONTROL_FIFO_CLR |
 461                    PV_CONTROL_EN);
 462
 463         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 464                   SCALER_DISPBKGND_AUTOHS |
 465                   SCALER_DISPBKGND_GAMMA |
 466                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 467
 468         /* Reload the LUT, since the SRAMs would have been disabled if
 469          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 470          */
 471         vc4_crtc_lut_load(crtc);
 472
 473         if (debug_dump_regs) {
 474                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 475                 vc4_crtc_dump_regs(vc4_crtc);
 476         }
 477 }
 478
 479 static void require_hvs_enabled(struct drm_device *dev)
 480 {
 481         struct vc4_dev *vc4 = to_vc4_dev(dev);
 482
 483         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 484                      SCALER_DISPCTRL_ENABLE);
 485 }
 486
 487 static void vc4_crtc_disable(struct drm_crtc *crtc)
 488 {
 489         struct drm_device *dev = crtc->dev;
 490         struct vc4_dev *vc4 = to_vc4_dev(dev);
 491         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 492         u32 chan = vc4_crtc->channel;
 493         int ret;
 494         require_hvs_enabled(dev);
 495
 496         /* Disable vblank irq handling before crtc is disabled. */
 497         drm_crtc_vblank_off(crtc);
 498
 499         CRTC_WRITE(PV_V_CONTROL,
 500                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 501         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 502         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 503
 504         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 505             SCALER_DISPCTRLX_ENABLE) {
 506                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 507                           SCALER_DISPCTRLX_RESET);
 508
 509                 /* While the docs say that reset is self-clearing, it
 510                  * seems it doesn't actually.
 511                  */
 512                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 513         }
 514
 515         /* Once we leave, the scaler should be disabled and its fifo empty. */
 516
 517         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 518
 519         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 520                                    SCALER_DISPSTATX_MODE) !=
 521                      SCALER_DISPSTATX_MODE_DISABLED);
 522
 523         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 524                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 525                      SCALER_DISPSTATX_EMPTY);
 526 }
 527
 528 static void vc4_crtc_enable(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct vc4_dev *vc4 = to_vc4_dev(dev);
 532         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 533         struct drm_crtc_state *state = crtc->state;
 534         struct drm_display_mode *mode = &state->adjusted_mode;
 535
 536         require_hvs_enabled(dev);
 537
 538         /* Turn on the scaler, which will wait for vstart to start
 539          * compositing.
 540          */
 541         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 542                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 543                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 544                   SCALER_DISPCTRLX_ENABLE);
 545
 546         /* Turn on the pixel valve, which will emit the vstart signal. */
 547         CRTC_WRITE(PV_V_CONTROL,
 548                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 549
 550         /* Enable vblank irq handling after crtc is started. */
 551         drm_crtc_vblank_on(crtc);
 552 }
 553
 554 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 555                                 const struct drm_display_mode *mode,
 556                                 struct drm_display_mode *adjusted_mode)
 557 {
 558         /* Do not allow doublescan modes from user space */
 559         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 560                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 561                               crtc->base.id);
 562                 return false;
 563         }
 564
 565         return true;
 566 }
 567
 568 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 569                                  struct drm_crtc_state *state)
 570 {
 571         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 572         struct drm_device *dev = crtc->dev;
 573         struct vc4_dev *vc4 = to_vc4_dev(dev);
 574         struct drm_plane *plane;
 575         unsigned long flags;
 576         const struct drm_plane_state *plane_state;
 577         u32 dlist_count = 0;
 578         int ret;
 579
 580         /* The pixelvalve can only feed one encoder (and encoders are
 581          * 1:1 with connectors.)
 582          */
 583         if (hweight32(state->connector_mask) > 1)
 584                 return -EINVAL;
 585
 586         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 587                 dlist_count += vc4_plane_dlist_size(plane_state);
 588
 589         dlist_count++; /* Account for SCALER_CTL0_END. */
 590
 591         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 592         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 593                                  dlist_count, 1, 0);
 594         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 595         if (ret)
 596                 return ret;
 597
 598         return 0;
 599 }
 600
 601 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 602                                   struct drm_crtc_state *old_state)
 603 {
 604         struct drm_device *dev = crtc->dev;
 605         struct vc4_dev *vc4 = to_vc4_dev(dev);
 606         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 607         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 608         struct drm_plane *plane;
 609         bool debug_dump_regs = false;
 610         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 611         u32 __iomem *dlist_next = dlist_start;
 612
 613         if (debug_dump_regs) {
 614                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 615                 vc4_hvs_dump_state(dev);
 616         }
 617
 618         /* Copy all the active planes' dlist contents to the hardware dlist. */
 619         drm_atomic_crtc_for_each_plane(plane, crtc) {
 620                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 621         }
 622
 623         writel(SCALER_CTL0_END, dlist_next);
 624         dlist_next++;
 625
 626         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 627
 628         if (crtc->state->event) {
 629                 unsigned long flags;
 630
 631                 crtc->state->event->pipe = drm_crtc_index(crtc);
 632
 633                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 634
 635                 spin_lock_irqsave(&dev->event_lock, flags);
 636                 vc4_crtc->event = crtc->state->event;
 637                 crtc->state->event = NULL;
 638
 639                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 640                           vc4_state->mm.start);
 641
 642                 spin_unlock_irqrestore(&dev->event_lock, flags);
 643         } else {
 644                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 645                           vc4_state->mm.start);
 646         }
 647
 648         if (debug_dump_regs) {
 649                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 650                 vc4_hvs_dump_state(dev);
 651         }
 652 }
 653
 654 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 655 {
 656         struct vc4_dev *vc4 = to_vc4_dev(dev);
 657         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 658
 659         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 660
 661         return 0;
 662 }
 663
 664 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 665 {
 666         struct vc4_dev *vc4 = to_vc4_dev(dev);
 667         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 668
 669         CRTC_WRITE(PV_INTEN, 0);
 670 }
 671
 672 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 673 {
 674         struct drm_crtc *crtc = &vc4_crtc->base;
 675         struct drm_device *dev = crtc->dev;
 676         struct vc4_dev *vc4 = to_vc4_dev(dev);
 677         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 678         u32 chan = vc4_crtc->channel;
 679         unsigned long flags;
 680
 681         spin_lock_irqsave(&dev->event_lock, flags);
 682         if (vc4_crtc->event &&
 683             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 684                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 685                 vc4_crtc->event = NULL;
 686                 drm_crtc_vblank_put(crtc);
 687         }
 688         spin_unlock_irqrestore(&dev->event_lock, flags);
 689 }
 690
 691 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 692 {
 693         struct vc4_crtc *vc4_crtc = data;
 694         u32 stat = CRTC_READ(PV_INTSTAT);
 695         irqreturn_t ret = IRQ_NONE;
 696
 697         if (stat & PV_INT_VFP_START) {
 698                 vc4_crtc->t_vblank = ktime_get();
 699                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 700                 drm_crtc_handle_vblank(&vc4_crtc->base);
 701                 vc4_crtc_handle_page_flip(vc4_crtc);
 702                 ret = IRQ_HANDLED;
 703         }
 704
 705         return ret;
 706 }
 707
 708 struct vc4_async_flip_state {
 709         struct drm_crtc *crtc;
 710         struct drm_framebuffer *fb;
 711         struct drm_pending_vblank_event *event;
 712
 713         struct vc4_seqno_cb cb;
 714 };
 715
 716 /* Called when the V3D execution for the BO being flipped to is done, so that
 717  * we can actually update the plane's address to point to it.
 718  */
 719 static void
 720 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 721 {
 722         struct vc4_async_flip_state *flip_state =
 723                 container_of(cb, struct vc4_async_flip_state, cb);
 724         struct drm_crtc *crtc = flip_state->crtc;
 725         struct drm_device *dev = crtc->dev;
 726         struct vc4_dev *vc4 = to_vc4_dev(dev);
 727         struct drm_plane *plane = crtc->primary;
 728
 729         vc4_plane_async_set_fb(plane, flip_state->fb);
 730         if (flip_state->event) {
 731                 unsigned long flags;
 732
 733                 spin_lock_irqsave(&dev->event_lock, flags);
 734                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 735                 spin_unlock_irqrestore(&dev->event_lock, flags);
 736         }
 737
 738         drm_crtc_vblank_put(crtc);
 739         drm_framebuffer_unreference(flip_state->fb);
 740         kfree(flip_state);
 741
 742         up(&vc4->async_modeset);
 743 }
 744
 745 /* Implements async (non-vblank-synced) page flips.
 746  *
 747  * The page flip ioctl needs to return immediately, so we grab the
 748  * modeset semaphore on the pipe, and queue the address update for
 749  * when V3D is done with the BO being flipped to.
 750  */
 751 static int vc4_async_page_flip(struct drm_crtc *crtc,
 752                                struct drm_framebuffer *fb,
 753                                struct drm_pending_vblank_event *event,
 754                                uint32_t flags)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct vc4_dev *vc4 = to_vc4_dev(dev);
 758         struct drm_plane *plane = crtc->primary;
 759         int ret = 0;
 760         struct vc4_async_flip_state *flip_state;
 761         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 762         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 763
 764         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 765         if (!flip_state)
 766                 return -ENOMEM;
 767
 768         drm_framebuffer_reference(fb);
 769         flip_state->fb = fb;
 770         flip_state->crtc = crtc;
 771         flip_state->event = event;
 772
 773         /* Make sure all other async modesetes have landed. */
 774         ret = down_interruptible(&vc4->async_modeset);
 775         if (ret) {
 776                 drm_framebuffer_unreference(fb);
 777                 kfree(flip_state);
 778                 return ret;
 779         }
 780
 781         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 782
 783         /* Immediately update the plane's legacy fb pointer, so that later
 784          * modeset prep sees the state that will be present when the semaphore
 785          * is released.
 786          */
 787         drm_atomic_set_fb_for_plane(plane->state, fb);
 788         plane->fb = fb;
 789
 790         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 791                            vc4_async_page_flip_complete);
 792
 793         /* Driver takes ownership of state on successful async commit. */
 794         return 0;
 795 }
 796
 797 static int vc4_page_flip(struct drm_crtc *crtc,
 798                          struct drm_framebuffer *fb,
 799                          struct drm_pending_vblank_event *event,
 800                          uint32_t flags)
 801 {
 802         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 803                 return vc4_async_page_flip(crtc, fb, event, flags);
 804         else
 805                 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
 806 }
 807
 808 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 809 {
 810         struct vc4_crtc_state *vc4_state;
 811
 812         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 813         if (!vc4_state)
 814                 return NULL;
 815
 816         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 817         return &vc4_state->base;
 818 }
 819
 820 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 821                                    struct drm_crtc_state *state)
 822 {
 823         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 824         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 825
 826         if (vc4_state->mm.allocated) {
 827                 unsigned long flags;
 828
 829                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 830                 drm_mm_remove_node(&vc4_state->mm);
 831                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 832
 833         }
 834
 835         __drm_atomic_helper_crtc_destroy_state(state);
 836 }
 837
 838 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 839         .set_config = drm_atomic_helper_set_config,
 840         .destroy = vc4_crtc_destroy,
 841         .page_flip = vc4_page_flip,
 842         .set_property = NULL,
 843         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 844         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 845         .reset = drm_atomic_helper_crtc_reset,
 846         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 847         .atomic_destroy_state = vc4_crtc_destroy_state,
 848         .gamma_set = vc4_crtc_gamma_set,
 849 };
 850
 851 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 852         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 853         .disable = vc4_crtc_disable,
 854         .enable = vc4_crtc_enable,
 855         .mode_fixup = vc4_crtc_mode_fixup,
 856         .atomic_check = vc4_crtc_atomic_check,
 857         .atomic_flush = vc4_crtc_atomic_flush,
 858 };
 859
 860 static const struct vc4_crtc_data pv0_data = {
 861         .hvs_channel = 0,
 862         .encoder0_type = VC4_ENCODER_TYPE_DSI0,
 863         .encoder1_type = VC4_ENCODER_TYPE_DPI,
 864 };
 865
 866 static const struct vc4_crtc_data pv1_data = {
 867         .hvs_channel = 2,
 868         .encoder0_type = VC4_ENCODER_TYPE_DSI1,
 869         .encoder1_type = VC4_ENCODER_TYPE_SMI,
 870 };
 871
 872 static const struct vc4_crtc_data pv2_data = {
 873         .hvs_channel = 1,
 874         .encoder0_type = VC4_ENCODER_TYPE_VEC,
 875         .encoder1_type = VC4_ENCODER_TYPE_HDMI,
 876 };
 877
 878 static const struct of_device_id vc4_crtc_dt_match[] = {
 879         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 880         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 881         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 882         {}
 883 };
 884
 885 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 886                                         struct drm_crtc *crtc)
 887 {
 888         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 889         struct drm_encoder *encoder;
 890
 891         drm_for_each_encoder(encoder, drm) {
 892                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 893
 894                 if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
 895                         vc4_encoder->clock_select = 0;
 896                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 897                 } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
 898                         vc4_encoder->clock_select = 1;
 899                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 900                 }
 901         }
 902 }
 903
 904 static void
 905 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 906 {
 907         struct drm_device *drm = vc4_crtc->base.dev;
 908         struct vc4_dev *vc4 = to_vc4_dev(drm);
 909         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 910         /* Top/base are supposed to be 4-pixel aligned, but the
 911          * Raspberry Pi firmware fills the low bits (which are
 912          * presumably ignored).
 913          */
 914         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 915         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 916
 917         vc4_crtc->cob_size = top - base + 4;
 918 }
 919
 920 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 921 {
 922         struct platform_device *pdev = to_platform_device(dev);
 923         struct drm_device *drm = dev_get_drvdata(master);
 924         struct vc4_dev *vc4 = to_vc4_dev(drm);
 925         struct vc4_crtc *vc4_crtc;
 926         struct drm_crtc *crtc;
 927         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 928         const struct of_device_id *match;
 929         int ret, i;
 930
 931         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 932         if (!vc4_crtc)
 933                 return -ENOMEM;
 934         crtc = &vc4_crtc->base;
 935
 936         match = of_match_device(vc4_crtc_dt_match, dev);
 937         if (!match)
 938                 return -ENODEV;
 939         vc4_crtc->data = match->data;
 940
 941         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 942         if (IS_ERR(vc4_crtc->regs))
 943                 return PTR_ERR(vc4_crtc->regs);
 944
 945         /* For now, we create just the primary and the legacy cursor
 946          * planes.  We should be able to stack more planes on easily,
 947          * but to do that we would need to compute the bandwidth
 948          * requirement of the plane configuration, and reject ones
 949          * that will take too much.
 950          */
 951         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 952         if (IS_ERR(primary_plane)) {
 953                 dev_err(dev, "failed to construct primary plane\n");
 954                 ret = PTR_ERR(primary_plane);
 955                 goto err;
 956         }
 957
 958         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 959                                   &vc4_crtc_funcs, NULL);
 960         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 961         primary_plane->crtc = crtc;
 962         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 963         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 964         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 965
 966         /* Set up some arbitrary number of planes.  We're not limited
 967          * by a set number of physical registers, just the space in
 968          * the HVS (16k) and how small an plane can be (28 bytes).
 969          * However, each plane we set up takes up some memory, and
 970          * increases the cost of looping over planes, which atomic
 971          * modesetting does quite a bit.  As a result, we pick a
 972          * modest number of planes to expose, that should hopefully
 973          * still cover any sane usecase.
 974          */
 975         for (i = 0; i < 8; i++) {
 976                 struct drm_plane *plane =
 977                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 978
 979                 if (IS_ERR(plane))
 980                         continue;
 981
 982                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 983         }
 984
 985         /* Set up the legacy cursor after overlay initialization,
 986          * since we overlay planes on the CRTC in the order they were
 987          * initialized.
 988          */
 989         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
 990         if (!IS_ERR(cursor_plane)) {
 991                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 992                 cursor_plane->crtc = crtc;
 993                 crtc->cursor = cursor_plane;
 994         }
 995
 996         vc4_crtc_get_cob_allocation(vc4_crtc);
 997
 998         CRTC_WRITE(PV_INTEN, 0);
 999         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1000         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1001                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1002         if (ret)
1003                 goto err_destroy_planes;
1004
1005         vc4_set_crtc_possible_masks(drm, crtc);
1006
1007         for (i = 0; i < crtc->gamma_size; i++) {
1008                 vc4_crtc->lut_r[i] = i;
1009                 vc4_crtc->lut_g[i] = i;
1010                 vc4_crtc->lut_b[i] = i;
1011         }
1012
1013         platform_set_drvdata(pdev, vc4_crtc);
1014
1015         return 0;
1016
1017 err_destroy_planes:
1018         list_for_each_entry_safe(destroy_plane, temp,
1019                                  &drm->mode_config.plane_list, head) {
1020                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1021                     destroy_plane->funcs->destroy(destroy_plane);
1022         }
1023 err:
1024         return ret;
1025 }
1026
1027 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1028                             void *data)
1029 {
1030         struct platform_device *pdev = to_platform_device(dev);
1031         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1032
1033         vc4_crtc_destroy(&vc4_crtc->base);
1034
1035         CRTC_WRITE(PV_INTEN, 0);
1036
1037         platform_set_drvdata(pdev, NULL);
1038 }
1039
1040 static const struct component_ops vc4_crtc_ops = {
1041         .bind   = vc4_crtc_bind,
1042         .unbind = vc4_crtc_unbind,
1043 };
1044
1045 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1046 {
1047         return component_add(&pdev->dev, &vc4_crtc_ops);
1048 }
1049
1050 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1051 {
1052         component_del(&pdev->dev, &vc4_crtc_ops);
1053         return 0;
1054 }
1055
1056 struct platform_driver vc4_crtc_driver = {
1057         .probe = vc4_crtc_dev_probe,
1058         .remove = vc4_crtc_dev_remove,
1059         .driver = {
1060                 .name = "vc4_crtc",
1061                 .of_match_table = vc4_crtc_dt_match,
1062         },
1063 };