drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  Most of the unit
  24  * operates off of the HSM clock from CPRMAN.  It also internally uses
  25  * the PLLH_PIX clock for the PHY.
  26  */
  27
  28 #include "drm_atomic_helper.h"
  29 #include "drm_crtc_helper.h"
  30 #include "drm_edid.h"
  31 #include "linux/clk.h"
  32 #include "linux/component.h"
  33 #include "linux/i2c.h"
  34 #include "linux/of_gpio.h"
  35 #include "linux/of_platform.h"
  36 #include "vc4_drv.h"
  37 #include "vc4_regs.h"
  38
  39 /* General HDMI hardware state. */
  40 struct vc4_hdmi {
  41         struct platform_device *pdev;
  42
  43         struct drm_encoder *encoder;
  44         struct drm_connector *connector;
  45
  46         struct i2c_adapter *ddc;
  47         void __iomem *hdmicore_regs;
  48         void __iomem *hd_regs;
  49         int hpd_gpio;
  50         bool hpd_active_low;
  51
  52         struct clk *pixel_clock;
  53         struct clk *hsm_clock;
  54 };
  55
  56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
  59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
  60
  61 /* VC4 HDMI encoder KMS struct */
  62 struct vc4_hdmi_encoder {
  63         struct vc4_encoder base;
  64         bool hdmi_monitor;
  65 };
  66
  67 static inline struct vc4_hdmi_encoder *
  68 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
  69 {
  70         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
  71 }
  72
  73 /* VC4 HDMI connector KMS struct */
  74 struct vc4_hdmi_connector {
  75         struct drm_connector base;
  76
  77         /* Since the connector is attached to just the one encoder,
  78          * this is the reference to it so we can do the best_encoder()
  79          * hook.
  80          */
  81         struct drm_encoder *encoder;
  82 };
  83
  84 static inline struct vc4_hdmi_connector *
  85 to_vc4_hdmi_connector(struct drm_connector *connector)
  86 {
  87         return container_of(connector, struct vc4_hdmi_connector, base);
  88 }
  89
  90 #define HDMI_REG(reg) { reg, #reg }
  91 static const struct {
  92         u32 reg;
  93         const char *name;
  94 } hdmi_regs[] = {
  95         HDMI_REG(VC4_HDMI_CORE_REV),
  96         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
  97         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
  98         HDMI_REG(VC4_HDMI_HOTPLUG),
  99         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 100         HDMI_REG(VC4_HDMI_HORZA),
 101         HDMI_REG(VC4_HDMI_HORZB),
 102         HDMI_REG(VC4_HDMI_FIFO_CTL),
 103         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 104         HDMI_REG(VC4_HDMI_VERTA0),
 105         HDMI_REG(VC4_HDMI_VERTA1),
 106         HDMI_REG(VC4_HDMI_VERTB0),
 107         HDMI_REG(VC4_HDMI_VERTB1),
 108         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 109 };
 110
 111 static const struct {
 112         u32 reg;
 113         const char *name;
 114 } hd_regs[] = {
 115         HDMI_REG(VC4_HD_M_CTL),
 116         HDMI_REG(VC4_HD_MAI_CTL),
 117         HDMI_REG(VC4_HD_VID_CTL),
 118         HDMI_REG(VC4_HD_CSC_CTL),
 119         HDMI_REG(VC4_HD_FRAME_COUNT),
 120 };
 121
 122 #ifdef CONFIG_DEBUG_FS
 123 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 124 {
 125         struct drm_info_node *node = (struct drm_info_node *)m->private;
 126         struct drm_device *dev = node->minor->dev;
 127         struct vc4_dev *vc4 = to_vc4_dev(dev);
 128         int i;
 129
 130         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 131                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 132                            hdmi_regs[i].name, hdmi_regs[i].reg,
 133                            HDMI_READ(hdmi_regs[i].reg));
 134         }
 135
 136         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 137                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 138                            hd_regs[i].name, hd_regs[i].reg,
 139                            HD_READ(hd_regs[i].reg));
 140         }
 141
 142         return 0;
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 147 {
 148         struct vc4_dev *vc4 = to_vc4_dev(dev);
 149         int i;
 150
 151         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 152                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 153                          hdmi_regs[i].reg, hdmi_regs[i].name,
 154                          HDMI_READ(hdmi_regs[i].reg));
 155         }
 156         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 157                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 158                          hd_regs[i].reg, hd_regs[i].name,
 159                          HD_READ(hd_regs[i].reg));
 160         }
 161 }
 162
 163 static enum drm_connector_status
 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 165 {
 166         struct drm_device *dev = connector->dev;
 167         struct vc4_dev *vc4 = to_vc4_dev(dev);
 168
 169         if (vc4->hdmi->hpd_gpio) {
 170                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 171                     vc4->hdmi->hpd_active_low)
 172                         return connector_status_connected;
 173                 else
 174                         return connector_status_disconnected;
 175         }
 176
 177         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 178                 return connector_status_connected;
 179         else
 180                 return connector_status_disconnected;
 181 }
 182
 183 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 184 {
 185         drm_connector_unregister(connector);
 186         drm_connector_cleanup(connector);
 187 }
 188
 189 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 190 {
 191         struct vc4_hdmi_connector *vc4_connector =
 192                 to_vc4_hdmi_connector(connector);
 193         struct drm_encoder *encoder = vc4_connector->encoder;
 194         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 195         struct drm_device *dev = connector->dev;
 196         struct vc4_dev *vc4 = to_vc4_dev(dev);
 197         int ret = 0;
 198         struct edid *edid;
 199
 200         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 201         if (!edid)
 202                 return -ENODEV;
 203
 204         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 205         drm_mode_connector_update_edid_property(connector, edid);
 206         ret = drm_add_edid_modes(connector, edid);
 207
 208         return ret;
 209 }
 210
 211 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 212         .dpms = drm_atomic_helper_connector_dpms,
 213         .detect = vc4_hdmi_connector_detect,
 214         .fill_modes = drm_helper_probe_single_connector_modes,
 215         .destroy = vc4_hdmi_connector_destroy,
 216         .reset = drm_atomic_helper_connector_reset,
 217         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 218         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 219 };
 220
 221 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 222         .get_modes = vc4_hdmi_connector_get_modes,
 223 };
 224
 225 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 226                                                      struct drm_encoder *encoder)
 227 {
 228         struct drm_connector *connector = NULL;
 229         struct vc4_hdmi_connector *hdmi_connector;
 230         int ret = 0;
 231
 232         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 233                                       GFP_KERNEL);
 234         if (!hdmi_connector) {
 235                 ret = -ENOMEM;
 236                 goto fail;
 237         }
 238         connector = &hdmi_connector->base;
 239
 240         hdmi_connector->encoder = encoder;
 241
 242         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 243                            DRM_MODE_CONNECTOR_HDMIA);
 244         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 245
 246         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 247                              DRM_CONNECTOR_POLL_DISCONNECT);
 248
 249         connector->interlace_allowed = 0;
 250         connector->doublescan_allowed = 0;
 251
 252         drm_mode_connector_attach_encoder(connector, encoder);
 253
 254         return connector;
 255
 256  fail:
 257         if (connector)
 258                 vc4_hdmi_connector_destroy(connector);
 259
 260         return ERR_PTR(ret);
 261 }
 262
 263 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 264 {
 265         drm_encoder_cleanup(encoder);
 266 }
 267
 268 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 269         .destroy = vc4_hdmi_encoder_destroy,
 270 };
 271
 272 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 273                                       struct drm_display_mode *unadjusted_mode,
 274                                       struct drm_display_mode *mode)
 275 {
 276         struct drm_device *dev = encoder->dev;
 277         struct vc4_dev *vc4 = to_vc4_dev(dev);
 278         bool debug_dump_regs = false;
 279         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 280         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 281         u32 vactive = (mode->vdisplay >>
 282                        ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
 283         u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 284                                    VC4_HDMI_VERTA_VSP) |
 285                      VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 286                                    VC4_HDMI_VERTA_VFP) |
 287                      VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
 288         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 289                      VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
 290                                    VC4_HDMI_VERTB_VBP));
 291
 292         if (debug_dump_regs) {
 293                 DRM_INFO("HDMI regs before:\n");
 294                 vc4_hdmi_dump_regs(dev);
 295         }
 296
 297         HD_WRITE(VC4_HD_VID_CTL, 0);
 298
 299         clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
 300
 301         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 302                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 303                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 304                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 305
 306         HDMI_WRITE(VC4_HDMI_HORZA,
 307                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 308                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 309                    VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
 310
 311         HDMI_WRITE(VC4_HDMI_HORZB,
 312                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 313                                  VC4_HDMI_HORZB_HBP) |
 314                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 315                                  VC4_HDMI_HORZB_HSP) |
 316                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 317                                  VC4_HDMI_HORZB_HFP));
 318
 319         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 320         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 321
 322         HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
 323         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 324
 325         HD_WRITE(VC4_HD_VID_CTL,
 326                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 327                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 328
 329         /* The RGB order applies even when CSC is disabled. */
 330         HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 331                                                VC4_HD_CSC_CTL_ORDER));
 332
 333         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 334
 335         if (debug_dump_regs) {
 336                 DRM_INFO("HDMI regs after:\n");
 337                 vc4_hdmi_dump_regs(dev);
 338         }
 339 }
 340
 341 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 342 {
 343         struct drm_device *dev = encoder->dev;
 344         struct vc4_dev *vc4 = to_vc4_dev(dev);
 345
 346         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 347         HD_WRITE(VC4_HD_VID_CTL,
 348                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 349 }
 350
 351 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 352 {
 353         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 354         struct drm_device *dev = encoder->dev;
 355         struct vc4_dev *vc4 = to_vc4_dev(dev);
 356         int ret;
 357
 358         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 359
 360         HD_WRITE(VC4_HD_VID_CTL,
 361                  HD_READ(VC4_HD_VID_CTL) |
 362                  VC4_HD_VID_CTL_ENABLE |
 363                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 364                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 365
 366         if (vc4_encoder->hdmi_monitor) {
 367                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 368                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 369                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 370
 371                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 372                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1);
 373                 WARN_ONCE(ret, "Timeout waiting for "
 374                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 375         } else {
 376                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 377                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 378                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 379                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 380                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 381                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 382
 383                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 384                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1);
 385                 WARN_ONCE(ret, "Timeout waiting for "
 386                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 387         }
 388
 389         if (vc4_encoder->hdmi_monitor) {
 390                 u32 drift;
 391
 392                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 393                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 394                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 395                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 396                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 397
 398                 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
 399                  * up the infoframe.
 400                  */
 401
 402                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 403                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 404
 405                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 406                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 407                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 408                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 409                 udelay(1000);
 410                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 411                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 412                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 413                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 414
 415                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 416                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 417                 WARN_ONCE(ret, "Timeout waiting for "
 418                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 419         }
 420 }
 421
 422 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 423         .mode_set = vc4_hdmi_encoder_mode_set,
 424         .disable = vc4_hdmi_encoder_disable,
 425         .enable = vc4_hdmi_encoder_enable,
 426 };
 427
 428 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
 429 {
 430         struct platform_device *pdev = to_platform_device(dev);
 431         struct drm_device *drm = dev_get_drvdata(master);
 432         struct vc4_dev *vc4 = drm->dev_private;
 433         struct vc4_hdmi *hdmi;
 434         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
 435         struct device_node *ddc_node;
 436         u32 value;
 437         int ret;
 438
 439         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 440         if (!hdmi)
 441                 return -ENOMEM;
 442
 443         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
 444                                         GFP_KERNEL);
 445         if (!vc4_hdmi_encoder)
 446                 return -ENOMEM;
 447         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
 448         hdmi->encoder = &vc4_hdmi_encoder->base.base;
 449
 450         hdmi->pdev = pdev;
 451         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
 452         if (IS_ERR(hdmi->hdmicore_regs))
 453                 return PTR_ERR(hdmi->hdmicore_regs);
 454
 455         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
 456         if (IS_ERR(hdmi->hd_regs))
 457                 return PTR_ERR(hdmi->hd_regs);
 458
 459         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
 460         if (IS_ERR(hdmi->pixel_clock)) {
 461                 DRM_ERROR("Failed to get pixel clock\n");
 462                 return PTR_ERR(hdmi->pixel_clock);
 463         }
 464         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
 465         if (IS_ERR(hdmi->hsm_clock)) {
 466                 DRM_ERROR("Failed to get HDMI state machine clock\n");
 467                 return PTR_ERR(hdmi->hsm_clock);
 468         }
 469
 470         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
 471         if (!ddc_node) {
 472                 DRM_ERROR("Failed to find ddc node in device tree\n");
 473                 return -ENODEV;
 474         }
 475
 476         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
 477         of_node_put(ddc_node);
 478         if (!hdmi->ddc) {
 479                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
 480                 return -EPROBE_DEFER;
 481         }
 482
 483         /* Enable the clocks at startup.  We can't quite recover from
 484          * turning off the pixel clock during disable/enables yet, so
 485          * it's always running.
 486          */
 487         ret = clk_prepare_enable(hdmi->pixel_clock);
 488         if (ret) {
 489                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 490                 goto err_put_i2c;
 491         }
 492
 493         /* This is the rate that is set by the firmware.  The number
 494          * needs to be a bit higher than the pixel clock rate
 495          * (generally 148.5Mhz).
 496          */
 497         ret = clk_set_rate(hdmi->hsm_clock, 163682864);
 498         if (ret) {
 499                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 500                 goto err_unprepare_pix;
 501         }
 502
 503         ret = clk_prepare_enable(hdmi->hsm_clock);
 504         if (ret) {
 505                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
 506                           ret);
 507                 goto err_unprepare_pix;
 508         }
 509
 510         /* Only use the GPIO HPD pin if present in the DT, otherwise
 511          * we'll use the HDMI core's register.
 512          */
 513         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
 514                 enum of_gpio_flags hpd_gpio_flags;
 515
 516                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
 517                                                          "hpd-gpios", 0,
 518                                                          &hpd_gpio_flags);
 519                 if (hdmi->hpd_gpio < 0) {
 520                         ret = hdmi->hpd_gpio;
 521                         goto err_unprepare_hsm;
 522                 }
 523
 524                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
 525         }
 526
 527         vc4->hdmi = hdmi;
 528
 529         /* HDMI core must be enabled. */
 530         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
 531                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
 532                 udelay(1);
 533                 HD_WRITE(VC4_HD_M_CTL, 0);
 534
 535                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
 536
 537                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 538                            VC4_HDMI_SW_RESET_HDMI |
 539                            VC4_HDMI_SW_RESET_FORMAT_DETECT);
 540
 541                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 542
 543                 /* PHY should be in reset, like
 544                  * vc4_hdmi_encoder_disable() does.
 545                  */
 546                 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 547         }
 548
 549         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
 550                          DRM_MODE_ENCODER_TMDS, NULL);
 551         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
 552
 553         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
 554         if (IS_ERR(hdmi->connector)) {
 555                 ret = PTR_ERR(hdmi->connector);
 556                 goto err_destroy_encoder;
 557         }
 558
 559         return 0;
 560
 561 err_destroy_encoder:
 562         vc4_hdmi_encoder_destroy(hdmi->encoder);
 563 err_unprepare_hsm:
 564         clk_disable_unprepare(hdmi->hsm_clock);
 565 err_unprepare_pix:
 566         clk_disable_unprepare(hdmi->pixel_clock);
 567 err_put_i2c:
 568         put_device(&hdmi->ddc->dev);
 569
 570         return ret;
 571 }
 572
 573 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
 574                             void *data)
 575 {
 576         struct drm_device *drm = dev_get_drvdata(master);
 577         struct vc4_dev *vc4 = drm->dev_private;
 578         struct vc4_hdmi *hdmi = vc4->hdmi;
 579
 580         vc4_hdmi_connector_destroy(hdmi->connector);
 581         vc4_hdmi_encoder_destroy(hdmi->encoder);
 582
 583         clk_disable_unprepare(hdmi->pixel_clock);
 584         clk_disable_unprepare(hdmi->hsm_clock);
 585         put_device(&hdmi->ddc->dev);
 586
 587         vc4->hdmi = NULL;
 588 }
 589
 590 static const struct component_ops vc4_hdmi_ops = {
 591         .bind   = vc4_hdmi_bind,
 592         .unbind = vc4_hdmi_unbind,
 593 };
 594
 595 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
 596 {
 597         return component_add(&pdev->dev, &vc4_hdmi_ops);
 598 }
 599
 600 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
 601 {
 602         component_del(&pdev->dev, &vc4_hdmi_ops);
 603         return 0;
 604 }
 605
 606 static const struct of_device_id vc4_hdmi_dt_match[] = {
 607         { .compatible = "brcm,bcm2835-hdmi" },
 608         {}
 609 };
 610
 611 struct platform_driver vc4_hdmi_driver = {
 612         .probe = vc4_hdmi_dev_probe,
 613         .remove = vc4_hdmi_dev_remove,
 614         .driver = {
 615                 .name = "vc4_hdmi",
 616                 .of_match_table = vc4_hdmi_dt_match,
 617         },
 618 };