drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/export.h>
  25 #include <linux/errno.h>
  26 #include <linux/err.h>
  27 #include <linux/i2c.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/delay.h>
  32 #include <linux/module.h>
  33 #include "i2c-designware-core.h"
  34
  35 /*
  36  * Registers offset
  37  */
  38 #define DW_IC_CON               0x0
  39 #define DW_IC_TAR               0x4
  40 #define DW_IC_DATA_CMD          0x10
  41 #define DW_IC_SS_SCL_HCNT       0x14
  42 #define DW_IC_SS_SCL_LCNT       0x18
  43 #define DW_IC_FS_SCL_HCNT       0x1c
  44 #define DW_IC_FS_SCL_LCNT       0x20
  45 #define DW_IC_HS_SCL_HCNT       0x24
  46 #define DW_IC_HS_SCL_LCNT       0x28
  47 #define DW_IC_INTR_STAT         0x2c
  48 #define DW_IC_INTR_MASK         0x30
  49 #define DW_IC_RAW_INTR_STAT     0x34
  50 #define DW_IC_RX_TL             0x38
  51 #define DW_IC_TX_TL             0x3c
  52 #define DW_IC_CLR_INTR          0x40
  53 #define DW_IC_CLR_RX_UNDER      0x44
  54 #define DW_IC_CLR_RX_OVER       0x48
  55 #define DW_IC_CLR_TX_OVER       0x4c
  56 #define DW_IC_CLR_RD_REQ        0x50
  57 #define DW_IC_CLR_TX_ABRT       0x54
  58 #define DW_IC_CLR_RX_DONE       0x58
  59 #define DW_IC_CLR_ACTIVITY      0x5c
  60 #define DW_IC_CLR_STOP_DET      0x60
  61 #define DW_IC_CLR_START_DET     0x64
  62 #define DW_IC_CLR_GEN_CALL      0x68
  63 #define DW_IC_ENABLE            0x6c
  64 #define DW_IC_STATUS            0x70
  65 #define DW_IC_TXFLR             0x74
  66 #define DW_IC_RXFLR             0x78
  67 #define DW_IC_SDA_HOLD          0x7c
  68 #define DW_IC_TX_ABRT_SOURCE    0x80
  69 #define DW_IC_ENABLE_STATUS     0x9c
  70 #define DW_IC_COMP_PARAM_1      0xf4
  71 #define DW_IC_COMP_VERSION      0xf8
  72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  73 #define DW_IC_COMP_TYPE         0xfc
  74 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  75
  76 #define DW_IC_INTR_RX_UNDER     0x001
  77 #define DW_IC_INTR_RX_OVER      0x002
  78 #define DW_IC_INTR_RX_FULL      0x004
  79 #define DW_IC_INTR_TX_OVER      0x008
  80 #define DW_IC_INTR_TX_EMPTY     0x010
  81 #define DW_IC_INTR_RD_REQ       0x020
  82 #define DW_IC_INTR_TX_ABRT      0x040
  83 #define DW_IC_INTR_RX_DONE      0x080
  84 #define DW_IC_INTR_ACTIVITY     0x100
  85 #define DW_IC_INTR_STOP_DET     0x200
  86 #define DW_IC_INTR_START_DET    0x400
  87 #define DW_IC_INTR_GEN_CALL     0x800
  88
  89 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  90                                          DW_IC_INTR_TX_EMPTY | \
  91                                          DW_IC_INTR_TX_ABRT | \
  92                                          DW_IC_INTR_STOP_DET)
  93
  94 #define DW_IC_STATUS_ACTIVITY           0x1
  95 #define DW_IC_STATUS_TFE                BIT(2)
  96 #define DW_IC_STATUS_MST_ACTIVITY       BIT(5)
  97
  98 #define DW_IC_SDA_HOLD_RX_SHIFT         16
  99 #define DW_IC_SDA_HOLD_RX_MASK          GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
 100
 101 #define DW_IC_ERR_TX_ABRT       0x1
 102
 103 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 104
 105 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
 106 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      GENMASK(3, 2)
 107
 108 /*
 109  * status codes
 110  */
 111 #define STATUS_IDLE                     0x0
 112 #define STATUS_WRITE_IN_PROGRESS        0x1
 113 #define STATUS_READ_IN_PROGRESS         0x2
 114
 115 #define TIMEOUT                 20 /* ms */
 116
 117 /*
 118  * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 119  *
 120  * only expected abort codes are listed here
 121  * refer to the datasheet for the full list
 122  */
 123 #define ABRT_7B_ADDR_NOACK      0
 124 #define ABRT_10ADDR1_NOACK      1
 125 #define ABRT_10ADDR2_NOACK      2
 126 #define ABRT_TXDATA_NOACK       3
 127 #define ABRT_GCALL_NOACK        4
 128 #define ABRT_GCALL_READ         5
 129 #define ABRT_SBYTE_ACKDET       7
 130 #define ABRT_SBYTE_NORSTRT      9
 131 #define ABRT_10B_RD_NORSTRT     10
 132 #define ABRT_MASTER_DIS         11
 133 #define ARB_LOST                12
 134
 135 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 136 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 137 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 138 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 139 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 140 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 141 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 142 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 143 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 144 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 145 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 146
 147 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 148                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 149                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 150                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 151                                          DW_IC_TX_ABRT_GCALL_NOACK)
 152
 153 static char *abort_sources[] = {
 154         [ABRT_7B_ADDR_NOACK] =
 155                 "slave address not acknowledged (7bit mode)",
 156         [ABRT_10ADDR1_NOACK] =
 157                 "first address byte not acknowledged (10bit mode)",
 158         [ABRT_10ADDR2_NOACK] =
 159                 "second address byte not acknowledged (10bit mode)",
 160         [ABRT_TXDATA_NOACK] =
 161                 "data not acknowledged",
 162         [ABRT_GCALL_NOACK] =
 163                 "no acknowledgement for a general call",
 164         [ABRT_GCALL_READ] =
 165                 "read after general call",
 166         [ABRT_SBYTE_ACKDET] =
 167                 "start byte acknowledged",
 168         [ABRT_SBYTE_NORSTRT] =
 169                 "trying to send start byte when restart is disabled",
 170         [ABRT_10B_RD_NORSTRT] =
 171                 "trying to read when restart is disabled (10bit mode)",
 172         [ABRT_MASTER_DIS] =
 173                 "trying to use disabled adapter",
 174         [ARB_LOST] =
 175                 "lost arbitration",
 176 };
 177
 178 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 179 {
 180         u32 value;
 181
 182         if (dev->accessor_flags & ACCESS_16BIT)
 183                 value = readw_relaxed(dev->base + offset) |
 184                         (readw_relaxed(dev->base + offset + 2) << 16);
 185         else
 186                 value = readl_relaxed(dev->base + offset);
 187
 188         if (dev->accessor_flags & ACCESS_SWAP)
 189                 return swab32(value);
 190         else
 191                 return value;
 192 }
 193
 194 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 195 {
 196         if (dev->accessor_flags & ACCESS_SWAP)
 197                 b = swab32(b);
 198
 199         if (dev->accessor_flags & ACCESS_16BIT) {
 200                 writew_relaxed((u16)b, dev->base + offset);
 201                 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
 202         } else {
 203                 writel_relaxed(b, dev->base + offset);
 204         }
 205 }
 206
 207 static u32
 208 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 209 {
 210         /*
 211          * DesignWare I2C core doesn't seem to have solid strategy to meet
 212          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 213          * will result in violation of the tHD;STA spec.
 214          */
 215         if (cond)
 216                 /*
 217                  * Conditional expression:
 218                  *
 219                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 220                  *
 221                  * This is based on the DW manuals, and represents an ideal
 222                  * configuration.  The resulting I2C bus speed will be
 223                  * faster than any of the others.
 224                  *
 225                  * If your hardware is free from tHD;STA issue, try this one.
 226                  */
 227                 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
 228         else
 229                 /*
 230                  * Conditional expression:
 231                  *
 232                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 233                  *
 234                  * This is just experimental rule; the tHD;STA period turned
 235                  * out to be proportinal to (_HCNT + 3).  With this setting,
 236                  * we could meet both tHIGH and tHD;STA timing specs.
 237                  *
 238                  * If unsure, you'd better to take this alternative.
 239                  *
 240                  * The reason why we need to take into account "tf" here,
 241                  * is the same as described in i2c_dw_scl_lcnt().
 242                  */
 243                 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
 244                         - 3 + offset;
 245 }
 246
 247 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 248 {
 249         /*
 250          * Conditional expression:
 251          *
 252          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 253          *
 254          * DW I2C core starts counting the SCL CNTs for the LOW period
 255          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 256          * In order to meet the tLOW timing spec, we need to take into
 257          * account the fall time of SCL signal (tf).  Default tf value
 258          * should be 0.3 us, for safety.
 259          */
 260         return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
 261 }
 262
 263 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
 264 {
 265         dw_writel(dev, enable, DW_IC_ENABLE);
 266 }
 267
 268 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
 269 {
 270         int timeout = 100;
 271
 272         do {
 273                 __i2c_dw_enable(dev, enable);
 274                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
 275                         return;
 276
 277                 /*
 278                  * Wait 10 times the signaling period of the highest I2C
 279                  * transfer supported by the driver (for 400KHz this is
 280                  * 25us) as described in the DesignWare I2C databook.
 281                  */
 282                 usleep_range(25, 250);
 283         } while (timeout--);
 284
 285         dev_warn(dev->dev, "timeout in %sabling adapter\n",
 286                  enable ? "en" : "dis");
 287 }
 288
 289 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
 290 {
 291         /*
 292          * Clock is not necessary if we got LCNT/HCNT values directly from
 293          * the platform code.
 294          */
 295         if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
 296                 return 0;
 297         return dev->get_clk_rate_khz(dev);
 298 }
 299
 300 static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
 301 {
 302         int ret;
 303
 304         if (!dev->acquire_lock)
 305                 return 0;
 306
 307         ret = dev->acquire_lock(dev);
 308         if (!ret)
 309                 return 0;
 310
 311         dev_err(dev->dev, "couldn't acquire bus ownership\n");
 312
 313         return ret;
 314 }
 315
 316 static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
 317 {
 318         if (dev->release_lock)
 319                 dev->release_lock(dev);
 320 }
 321
 322 /**
 323  * i2c_dw_init() - initialize the designware i2c master hardware
 324  * @dev: device private data
 325  *
 326  * This functions configures and enables the I2C master.
 327  * This function is called during I2C init function, and in case of timeout at
 328  * run time.
 329  */
 330 int i2c_dw_init(struct dw_i2c_dev *dev)
 331 {
 332         u32 hcnt, lcnt;
 333         u32 reg, comp_param1;
 334         u32 sda_falling_time, scl_falling_time;
 335         int ret;
 336
 337         ret = i2c_dw_acquire_lock(dev);
 338         if (ret)
 339                 return ret;
 340
 341         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 342         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 343                 /* Configure register endianess access */
 344                 dev->accessor_flags |= ACCESS_SWAP;
 345         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 346                 /* Configure register access mode 16bit */
 347                 dev->accessor_flags |= ACCESS_16BIT;
 348         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 349                 dev_err(dev->dev, "Unknown Synopsys component type: "
 350                         "0x%08x\n", reg);
 351                 i2c_dw_release_lock(dev);
 352                 return -ENODEV;
 353         }
 354
 355         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
 356
 357         /* Disable the adapter */
 358         __i2c_dw_enable_and_wait(dev, false);
 359
 360         /* set standard and fast speed deviders for high/low periods */
 361
 362         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
 363         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
 364
 365         /* Set SCL timing parameters for standard-mode */
 366         if (dev->ss_hcnt && dev->ss_lcnt) {
 367                 hcnt = dev->ss_hcnt;
 368                 lcnt = dev->ss_lcnt;
 369         } else {
 370                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 371                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
 372                                         sda_falling_time,
 373                                         0,      /* 0: DW default, 1: Ideal */
 374                                         0);     /* No offset */
 375                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 376                                         4700,   /* tLOW = 4.7 us */
 377                                         scl_falling_time,
 378                                         0);     /* No offset */
 379         }
 380         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 381         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 382         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 383
 384         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 385         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 386                 hcnt = dev->fp_hcnt;
 387                 lcnt = dev->fp_lcnt;
 388         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 389                 hcnt = dev->fs_hcnt;
 390                 lcnt = dev->fs_lcnt;
 391         } else {
 392                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 393                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 394                                         sda_falling_time,
 395                                         0,      /* 0: DW default, 1: Ideal */
 396                                         0);     /* No offset */
 397                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 398                                         1300,   /* tLOW = 1.3 us */
 399                                         scl_falling_time,
 400                                         0);     /* No offset */
 401         }
 402         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 403         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 404         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 405
 406         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 407                 DW_IC_CON_SPEED_HIGH) {
 408                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 409                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 410                         dev_err(dev->dev, "High Speed not supported!\n");
 411                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 412                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 413                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 414                         hcnt = dev->hs_hcnt;
 415                         lcnt = dev->hs_lcnt;
 416                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 417                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 418                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 419                                 hcnt, lcnt);
 420                 }
 421         }
 422
 423         /* Configure SDA Hold Time if required */
 424         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 425         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 426                 if (!dev->sda_hold_time) {
 427                         /* Keep previous hold time setting if no one set it */
 428                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 429                 }
 430                 /*
 431                  * Workaround for avoiding TX arbitration lost in case I2C
 432                  * slave pulls SDA down "too quickly" after falling egde of
 433                  * SCL by enabling non-zero SDA RX hold. Specification says it
 434                  * extends incoming SDA low to high transition while SCL is
 435                  * high but it apprears to help also above issue.
 436                  */
 437                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 438                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 439                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 440         } else {
 441                 dev_warn(dev->dev,
 442                         "Hardware too old to adjust SDA hold time.\n");
 443         }
 444
 445         /* Configure Tx/Rx FIFO threshold levels */
 446         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
 447         dw_writel(dev, 0, DW_IC_RX_TL);
 448
 449         /* configure the i2c master */
 450         dw_writel(dev, dev->master_cfg , DW_IC_CON);
 451
 452         i2c_dw_release_lock(dev);
 453
 454         return 0;
 455 }
 456 EXPORT_SYMBOL_GPL(i2c_dw_init);
 457
 458 /*
 459  * Waiting for bus not busy
 460  */
 461 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 462 {
 463         int timeout = TIMEOUT;
 464
 465         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 466                 if (timeout <= 0) {
 467                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 468                         return -ETIMEDOUT;
 469                 }
 470                 timeout--;
 471                 usleep_range(1000, 1100);
 472         }
 473
 474         return 0;
 475 }
 476
 477 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 478 {
 479         struct i2c_msg *msgs = dev->msgs;
 480         u32 ic_tar = 0;
 481         bool enabled;
 482
 483         enabled = dw_readl(dev, DW_IC_ENABLE_STATUS) & 1;
 484
 485         if (enabled) {
 486                 u32 ic_status;
 487
 488                 /*
 489                  * Only disable adapter if ic_tar and ic_con can't be
 490                  * dynamically updated
 491                  */
 492                 ic_status = dw_readl(dev, DW_IC_STATUS);
 493                 if (!dev->dynamic_tar_update_enabled ||
 494                     (ic_status & DW_IC_STATUS_MST_ACTIVITY) ||
 495                     !(ic_status & DW_IC_STATUS_TFE)) {
 496                         __i2c_dw_enable_and_wait(dev, false);
 497                         enabled = false;
 498                 }
 499         }
 500
 501         /* if the slave address is ten bit address, enable 10BITADDR */
 502         if (dev->dynamic_tar_update_enabled) {
 503                 /*
 504                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 505                  * mode has to be enabled via bit 12 of IC_TAR register,
 506                  * otherwise bit 4 of IC_CON is used.
 507                  */
 508                 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
 509                         ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 510         } else {
 511                 u32 ic_con = dw_readl(dev, DW_IC_CON);
 512
 513                 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
 514                         ic_con |= DW_IC_CON_10BITADDR_MASTER;
 515                 else
 516                         ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 517                 dw_writel(dev, ic_con, DW_IC_CON);
 518         }
 519
 520         /*
 521          * Set the slave (target) address and enable 10-bit addressing mode
 522          * if applicable.
 523          */
 524         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 525
 526         /* enforce disabled interrupts (due to HW issues) */
 527         i2c_dw_disable_int(dev);
 528
 529         if (!enabled)
 530                 __i2c_dw_enable(dev, true);
 531
 532         /* Clear and enable interrupts */
 533         dw_readl(dev, DW_IC_CLR_INTR);
 534         dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
 535 }
 536
 537 /*
 538  * Initiate (and continue) low level master read/write transaction.
 539  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 540  * messages into the tx buffer.  Even if the size of i2c_msg data is
 541  * longer than the size of the tx buffer, it handles everything.
 542  */
 543 static void
 544 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 545 {
 546         struct i2c_msg *msgs = dev->msgs;
 547         u32 intr_mask;
 548         int tx_limit, rx_limit;
 549         u32 addr = msgs[dev->msg_write_idx].addr;
 550         u32 buf_len = dev->tx_buf_len;
 551         u8 *buf = dev->tx_buf;
 552         bool need_restart = false;
 553
 554         intr_mask = DW_IC_INTR_DEFAULT_MASK;
 555
 556         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 557                 /*
 558                  * if target address has changed, we need to
 559                  * reprogram the target address in the i2c
 560                  * adapter when we are done with this transfer
 561                  */
 562                 if (msgs[dev->msg_write_idx].addr != addr) {
 563                         dev_err(dev->dev,
 564                                 "%s: invalid target address\n", __func__);
 565                         dev->msg_err = -EINVAL;
 566                         break;
 567                 }
 568
 569                 if (msgs[dev->msg_write_idx].len == 0) {
 570                         dev_err(dev->dev,
 571                                 "%s: invalid message length\n", __func__);
 572                         dev->msg_err = -EINVAL;
 573                         break;
 574                 }
 575
 576                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 577                         /* new i2c_msg */
 578                         buf = msgs[dev->msg_write_idx].buf;
 579                         buf_len = msgs[dev->msg_write_idx].len;
 580
 581                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 582                          * IC_RESTART_EN are set, we must manually
 583                          * set restart bit between messages.
 584                          */
 585                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 586                                         (dev->msg_write_idx > 0))
 587                                 need_restart = true;
 588                 }
 589
 590                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 591                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 592
 593                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 594                         u32 cmd = 0;
 595
 596                         /*
 597                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 598                          * manually set the stop bit. However, it cannot be
 599                          * detected from the registers so we set it always
 600                          * when writing/reading the last byte.
 601                          */
 602                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 603                             buf_len == 1)
 604                                 cmd |= BIT(9);
 605
 606                         if (need_restart) {
 607                                 cmd |= BIT(10);
 608                                 need_restart = false;
 609                         }
 610
 611                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 612
 613                                 /* avoid rx buffer overrun */
 614                                 if (rx_limit - dev->rx_outstanding <= 0)
 615                                         break;
 616
 617                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 618                                 rx_limit--;
 619                                 dev->rx_outstanding++;
 620                         } else
 621                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 622                         tx_limit--; buf_len--;
 623                 }
 624
 625                 dev->tx_buf = buf;
 626                 dev->tx_buf_len = buf_len;
 627
 628                 if (buf_len > 0) {
 629                         /* more bytes to be written */
 630                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 631                         break;
 632                 } else
 633                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 634         }
 635
 636         /*
 637          * If i2c_msg index search is completed, we don't need TX_EMPTY
 638          * interrupt any more.
 639          */
 640         if (dev->msg_write_idx == dev->msgs_num)
 641                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 642
 643         if (dev->msg_err)
 644                 intr_mask = 0;
 645
 646         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 647 }
 648
 649 static void
 650 i2c_dw_read(struct dw_i2c_dev *dev)
 651 {
 652         struct i2c_msg *msgs = dev->msgs;
 653         int rx_valid;
 654
 655         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 656                 u32 len;
 657                 u8 *buf;
 658
 659                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 660                         continue;
 661
 662                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 663                         len = msgs[dev->msg_read_idx].len;
 664                         buf = msgs[dev->msg_read_idx].buf;
 665                 } else {
 666                         len = dev->rx_buf_len;
 667                         buf = dev->rx_buf;
 668                 }
 669
 670                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 671
 672                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 673                         *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
 674                         dev->rx_outstanding--;
 675                 }
 676
 677                 if (len > 0) {
 678                         dev->status |= STATUS_READ_IN_PROGRESS;
 679                         dev->rx_buf_len = len;
 680                         dev->rx_buf = buf;
 681                         return;
 682                 } else
 683                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 684         }
 685 }
 686
 687 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 688 {
 689         unsigned long abort_source = dev->abort_source;
 690         int i;
 691
 692         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 693                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 694                         dev_dbg(dev->dev,
 695                                 "%s: %s\n", __func__, abort_sources[i]);
 696                 return -EREMOTEIO;
 697         }
 698
 699         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 700                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 701
 702         if (abort_source & DW_IC_TX_ARB_LOST)
 703                 return -EAGAIN;
 704         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 705                 return -EINVAL; /* wrong msgs[] data */
 706         else
 707                 return -EIO;
 708 }
 709
 710 /*
 711  * Prepare controller for a transaction and start transfer by calling
 712  * i2c_dw_xfer_init()
 713  */
 714 static int
 715 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 716 {
 717         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 718         int ret;
 719
 720         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 721
 722         pm_runtime_get_sync(dev->dev);
 723
 724         reinit_completion(&dev->cmd_complete);
 725         dev->msgs = msgs;
 726         dev->msgs_num = num;
 727         dev->cmd_err = 0;
 728         dev->msg_write_idx = 0;
 729         dev->msg_read_idx = 0;
 730         dev->msg_err = 0;
 731         dev->status = STATUS_IDLE;
 732         dev->abort_source = 0;
 733         dev->rx_outstanding = 0;
 734
 735         ret = i2c_dw_acquire_lock(dev);
 736         if (ret)
 737                 goto done_nolock;
 738
 739         ret = i2c_dw_wait_bus_not_busy(dev);
 740         if (ret < 0)
 741                 goto done;
 742
 743         /* start the transfers */
 744         i2c_dw_xfer_init(dev);
 745
 746         /* wait for tx to complete */
 747         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 748                 dev_err(dev->dev, "controller timed out\n");
 749                 /* i2c_dw_init implicitly disables the adapter */
 750                 i2c_dw_init(dev);
 751                 ret = -ETIMEDOUT;
 752                 goto done;
 753         }
 754
 755         if (dev->msg_err) {
 756                 ret = dev->msg_err;
 757                 goto done;
 758         }
 759
 760         /* no error */
 761         if (likely(!dev->cmd_err)) {
 762                 ret = num;
 763                 goto done;
 764         }
 765
 766         /* We have an error */
 767         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 768                 ret = i2c_dw_handle_tx_abort(dev);
 769                 goto done;
 770         }
 771         ret = -EIO;
 772
 773 done:
 774         i2c_dw_release_lock(dev);
 775
 776 done_nolock:
 777         pm_runtime_mark_last_busy(dev->dev);
 778         pm_runtime_put_autosuspend(dev->dev);
 779
 780         return ret;
 781 }
 782
 783 static u32 i2c_dw_func(struct i2c_adapter *adap)
 784 {
 785         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 786         return dev->functionality;
 787 }
 788
 789 static struct i2c_algorithm i2c_dw_algo = {
 790         .master_xfer    = i2c_dw_xfer,
 791         .functionality  = i2c_dw_func,
 792 };
 793
 794 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 795 {
 796         u32 stat;
 797
 798         /*
 799          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 800          * Ths unmasked raw version of interrupt status bits are available
 801          * in the IC_RAW_INTR_STAT register.
 802          *
 803          * That is,
 804          *   stat = dw_readl(IC_INTR_STAT);
 805          * equals to,
 806          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 807          *
 808          * The raw version might be useful for debugging purposes.
 809          */
 810         stat = dw_readl(dev, DW_IC_INTR_STAT);
 811
 812         /*
 813          * Do not use the IC_CLR_INTR register to clear interrupts, or
 814          * you'll miss some interrupts, triggered during the period from
 815          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 816          *
 817          * Instead, use the separately-prepared IC_CLR_* registers.
 818          */
 819         if (stat & DW_IC_INTR_RX_UNDER)
 820                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 821         if (stat & DW_IC_INTR_RX_OVER)
 822                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 823         if (stat & DW_IC_INTR_TX_OVER)
 824                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 825         if (stat & DW_IC_INTR_RD_REQ)
 826                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 827         if (stat & DW_IC_INTR_TX_ABRT) {
 828                 /*
 829                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 830                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 831                  */
 832                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 833                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 834         }
 835         if (stat & DW_IC_INTR_RX_DONE)
 836                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 837         if (stat & DW_IC_INTR_ACTIVITY)
 838                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 839         if (stat & DW_IC_INTR_STOP_DET)
 840                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 841         if (stat & DW_IC_INTR_START_DET)
 842                 dw_readl(dev, DW_IC_CLR_START_DET);
 843         if (stat & DW_IC_INTR_GEN_CALL)
 844                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 845
 846         return stat;
 847 }
 848
 849 /*
 850  * Interrupt service routine. This gets called whenever an I2C interrupt
 851  * occurs.
 852  */
 853 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 854 {
 855         struct dw_i2c_dev *dev = dev_id;
 856         u32 stat, enabled;
 857
 858         enabled = dw_readl(dev, DW_IC_ENABLE);
 859         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 860         dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
 861         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 862                 return IRQ_NONE;
 863
 864         stat = i2c_dw_read_clear_intrbits(dev);
 865
 866         if (stat & DW_IC_INTR_TX_ABRT) {
 867                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 868                 dev->status = STATUS_IDLE;
 869
 870                 /*
 871                  * Anytime TX_ABRT is set, the contents of the tx/rx
 872                  * buffers are flushed.  Make sure to skip them.
 873                  */
 874                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 875                 goto tx_aborted;
 876         }
 877
 878         if (stat & DW_IC_INTR_RX_FULL)
 879                 i2c_dw_read(dev);
 880
 881         if (stat & DW_IC_INTR_TX_EMPTY)
 882                 i2c_dw_xfer_msg(dev);
 883
 884         /*
 885          * No need to modify or disable the interrupt mask here.
 886          * i2c_dw_xfer_msg() will take care of it according to
 887          * the current transmit status.
 888          */
 889
 890 tx_aborted:
 891         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET))
 892                         || dev->msg_err) {
 893                 /*
 894                  * We must disable interruts before returning and signaling
 895                  * the end of the current transfer. Otherwise the hardware
 896                  * might continue generating interrupts for non-existent
 897                  * transfers.
 898                  */
 899                 i2c_dw_disable_int(dev);
 900                 dw_readl(dev, DW_IC_CLR_INTR);
 901
 902                 complete(&dev->cmd_complete);
 903         } else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
 904                 /* workaround to trigger pending interrupt */
 905                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 906                 i2c_dw_disable_int(dev);
 907                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 908         }
 909
 910         return IRQ_HANDLED;
 911 }
 912
 913 void i2c_dw_disable(struct dw_i2c_dev *dev)
 914 {
 915         /* Disable controller */
 916         __i2c_dw_enable_and_wait(dev, false);
 917
 918         /* Disable all interupts */
 919         dw_writel(dev, 0, DW_IC_INTR_MASK);
 920         dw_readl(dev, DW_IC_CLR_INTR);
 921 }
 922 EXPORT_SYMBOL_GPL(i2c_dw_disable);
 923
 924 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 925 {
 926         dw_writel(dev, 0, DW_IC_INTR_MASK);
 927 }
 928 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
 929
 930 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 931 {
 932         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 933 }
 934 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 935
 936 int i2c_dw_probe(struct dw_i2c_dev *dev)
 937 {
 938         struct i2c_adapter *adap = &dev->adapter;
 939         int r;
 940         u32 reg;
 941
 942         init_completion(&dev->cmd_complete);
 943
 944         r = i2c_dw_init(dev);
 945         if (r)
 946                 return r;
 947
 948         r = i2c_dw_acquire_lock(dev);
 949         if (r)
 950                 return r;
 951
 952         /*
 953          * Test if dynamic TAR update is enabled in this controller by writing
 954          * to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this
 955          * field is read-only so it should not succeed
 956          */
 957         reg = dw_readl(dev, DW_IC_CON);
 958         dw_writel(dev, reg ^ DW_IC_CON_10BITADDR_MASTER, DW_IC_CON);
 959
 960         if ((dw_readl(dev, DW_IC_CON) & DW_IC_CON_10BITADDR_MASTER) ==
 961             (reg & DW_IC_CON_10BITADDR_MASTER)) {
 962                 dev->dynamic_tar_update_enabled = true;
 963                 dev_dbg(dev->dev, "Dynamic TAR update enabled");
 964         }
 965
 966         i2c_dw_release_lock(dev);
 967
 968         snprintf(adap->name, sizeof(adap->name),
 969                  "Synopsys DesignWare I2C adapter");
 970         adap->retries = 3;
 971         adap->algo = &i2c_dw_algo;
 972         adap->dev.parent = dev->dev;
 973         i2c_set_adapdata(adap, dev);
 974
 975         i2c_dw_disable_int(dev);
 976         r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
 977                              IRQF_SHARED | IRQF_COND_SUSPEND,
 978                              dev_name(dev->dev), dev);
 979         if (r) {
 980                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 981                         dev->irq, r);
 982                 return r;
 983         }
 984
 985         /*
 986          * Increment PM usage count during adapter registration in order to
 987          * avoid possible spurious runtime suspend when adapter device is
 988          * registered to the device core and immediate resume in case bus has
 989          * registered I2C slaves that do I2C transfers in their probe.
 990          */
 991         pm_runtime_get_noresume(dev->dev);
 992         r = i2c_add_numbered_adapter(adap);
 993         if (r)
 994                 dev_err(dev->dev, "failure adding adapter: %d\n", r);
 995         pm_runtime_put_noidle(dev->dev);
 996
 997         return r;
 998 }
 999 EXPORT_SYMBOL_GPL(i2c_dw_probe);
1000
1001 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
1002 MODULE_LICENSE("GPL");