2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
26 #define DW_IC_CON_MASTER 0x1
27 #define DW_IC_CON_SPEED_STD 0x2
28 #define DW_IC_CON_SPEED_FAST 0x4
29 #define DW_IC_CON_SPEED_MASK 0x6
30 #define DW_IC_CON_10BITADDR_MASTER 0x10
31 #define DW_IC_CON_RESTART_EN 0x20
32 #define DW_IC_CON_SLAVE_DISABLE 0x40
36 * struct dw_i2c_dev - private i2c-designware data
37 * @dev: driver model device node
38 * @base: IO registers pointer
39 * @cmd_complete: tx completion indicator
40 * @clk: input reference clock
41 * @cmd_err: run time hadware error code
42 * @msgs: points to an array of messages currently being transfered
43 * @msgs_num: the number of elements in msgs
44 * @msg_write_idx: the element index of the current tx message in the msgs
46 * @tx_buf_len: the length of the current tx buffer
47 * @tx_buf: the current tx buffer
48 * @msg_read_idx: the element index of the current rx message in the msgs
50 * @rx_buf_len: the length of the current rx buffer
51 * @rx_buf: the current rx buffer
52 * @msg_err: error status of the current transfer
53 * @status: i2c master status, one of STATUS_*
54 * @abort_source: copy of the TX_ABRT_SOURCE register
55 * @irq: interrupt number for the i2c master
56 * @adapter: i2c subsystem adapter node
57 * @tx_fifo_depth: depth of the hardware tx fifo
58 * @rx_fifo_depth: depth of the hardware rx fifo
59 * @rx_outstanding: current master-rx elements in tx fifo
60 * @clk_freq: bus clock frequency
61 * @ss_hcnt: standard speed HCNT value
62 * @ss_lcnt: standard speed LCNT value
63 * @fs_hcnt: fast speed HCNT value
64 * @fs_lcnt: fast speed LCNT value
65 * @fp_hcnt: fast plus HCNT value
66 * @fp_lcnt: fast plus LCNT value
67 * @hs_hcnt: high speed HCNT value
68 * @hs_lcnt: high speed LCNT value
69 * @acquire_lock: function to acquire a hardware lock on the bus
70 * @release_lock: function to release a hardware lock on the bus
71 * @pm_runtime_disabled: true if pm runtime is disabled
73 * HCNT and LCNT parameters can be used if the platform knows more accurate
74 * values than the one computed based only on the input clock frequency.
75 * Leave them to be %0 if not used.
80 struct completion cmd_complete;
82 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
83 struct dw_pci_controller *controller;
98 struct i2c_adapter adapter;
101 unsigned int tx_fifo_depth;
102 unsigned int rx_fifo_depth;
106 u32 sda_falling_time;
107 u32 scl_falling_time;
116 int (*acquire_lock)(struct dw_i2c_dev *dev);
117 void (*release_lock)(struct dw_i2c_dev *dev);
118 bool pm_runtime_disabled;
121 #define ACCESS_SWAP 0x00000001
122 #define ACCESS_16BIT 0x00000002
123 #define ACCESS_INTR_MASK 0x00000004
125 extern int i2c_dw_init(struct dw_i2c_dev *dev);
126 extern void i2c_dw_disable(struct dw_i2c_dev *dev);
127 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
128 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
129 extern int i2c_dw_probe(struct dw_i2c_dev *dev);
131 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
132 extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
134 static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }