drivers/i2c/busses/i2c-exynos5.c

   1 /**
   2  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <linux/i2c.h>
  15 #include <linux/time.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/slab.h>
  23 #include <linux/io.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29  * HSI2C controller from Samsung supports 2 modes of operation
  30  * 1. Auto mode: Where in master automatically controls the whole transaction
  31  * 2. Manual mode: Software controls the transaction by issuing commands
  32  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
  33  *
  34  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
  35  *
  36  * Special bits are available for both modes of operation to set commands
  37  * and for checking transfer status
  38  */
  39
  40 /* Register Map */
  41 #define HSI2C_CTL               0x00
  42 #define HSI2C_FIFO_CTL          0x04
  43 #define HSI2C_TRAILIG_CTL       0x08
  44 #define HSI2C_CLK_CTL           0x0C
  45 #define HSI2C_CLK_SLOT          0x10
  46 #define HSI2C_INT_ENABLE        0x20
  47 #define HSI2C_INT_STATUS        0x24
  48 #define HSI2C_ERR_STATUS        0x2C
  49 #define HSI2C_FIFO_STATUS       0x30
  50 #define HSI2C_TX_DATA           0x34
  51 #define HSI2C_RX_DATA           0x38
  52 #define HSI2C_CONF              0x40
  53 #define HSI2C_AUTO_CONF         0x44
  54 #define HSI2C_TIMEOUT           0x48
  55 #define HSI2C_MANUAL_CMD        0x4C
  56 #define HSI2C_TRANS_STATUS      0x50
  57 #define HSI2C_TIMING_HS1        0x54
  58 #define HSI2C_TIMING_HS2        0x58
  59 #define HSI2C_TIMING_HS3        0x5C
  60 #define HSI2C_TIMING_FS1        0x60
  61 #define HSI2C_TIMING_FS2        0x64
  62 #define HSI2C_TIMING_FS3        0x68
  63 #define HSI2C_TIMING_SLA        0x6C
  64 #define HSI2C_ADDR              0x70
  65
  66 /* I2C_CTL Register bits */
  67 #define HSI2C_FUNC_MODE_I2C                     (1u << 0)
  68 #define HSI2C_MASTER                            (1u << 3)
  69 #define HSI2C_RXCHON                            (1u << 6)
  70 #define HSI2C_TXCHON                            (1u << 7)
  71 #define HSI2C_SW_RST                            (1u << 31)
  72
  73 /* I2C_FIFO_CTL Register bits */
  74 #define HSI2C_RXFIFO_EN                         (1u << 0)
  75 #define HSI2C_TXFIFO_EN                         (1u << 1)
  76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)           ((x) << 4)
  77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)           ((x) << 16)
  78
  79 /* I2C_TRAILING_CTL Register bits */
  80 #define HSI2C_TRAILING_COUNT                    (0xf)
  81
  82 /* I2C_INT_EN Register bits */
  83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN             (1u << 0)
  84 #define HSI2C_INT_RX_ALMOSTFULL_EN              (1u << 1)
  85 #define HSI2C_INT_TRAILING_EN                   (1u << 6)
  86 #define HSI2C_INT_I2C_EN                        (1u << 9)
  87
  88 /* I2C_INT_STAT Register bits */
  89 #define HSI2C_INT_TX_ALMOSTEMPTY                (1u << 0)
  90 #define HSI2C_INT_RX_ALMOSTFULL                 (1u << 1)
  91 #define HSI2C_INT_TX_UNDERRUN                   (1u << 2)
  92 #define HSI2C_INT_TX_OVERRUN                    (1u << 3)
  93 #define HSI2C_INT_RX_UNDERRUN                   (1u << 4)
  94 #define HSI2C_INT_RX_OVERRUN                    (1u << 5)
  95 #define HSI2C_INT_TRAILING                      (1u << 6)
  96 #define HSI2C_INT_I2C                           (1u << 9)
  97
  98 /* I2C_FIFO_STAT Register bits */
  99 #define HSI2C_RX_FIFO_EMPTY                     (1u << 24)
 100 #define HSI2C_RX_FIFO_FULL                      (1u << 23)
 101 #define HSI2C_RX_FIFO_LVL(x)                    ((x >> 16) & 0x7f)
 102 #define HSI2C_TX_FIFO_EMPTY                     (1u << 8)
 103 #define HSI2C_TX_FIFO_FULL                      (1u << 7)
 104 #define HSI2C_TX_FIFO_LVL(x)                    ((x >> 0) & 0x7f)
 105
 106 /* I2C_CONF Register bits */
 107 #define HSI2C_AUTO_MODE                         (1u << 31)
 108 #define HSI2C_10BIT_ADDR_MODE                   (1u << 30)
 109 #define HSI2C_HS_MODE                           (1u << 29)
 110
 111 /* I2C_AUTO_CONF Register bits */
 112 #define HSI2C_READ_WRITE                        (1u << 16)
 113 #define HSI2C_STOP_AFTER_TRANS                  (1u << 17)
 114 #define HSI2C_MASTER_RUN                        (1u << 31)
 115
 116 /* I2C_TIMEOUT Register bits */
 117 #define HSI2C_TIMEOUT_EN                        (1u << 31)
 118 #define HSI2C_TIMEOUT_MASK                      0xff
 119
 120 /* I2C_TRANS_STATUS register bits */
 121 #define HSI2C_MASTER_BUSY                       (1u << 17)
 122 #define HSI2C_SLAVE_BUSY                        (1u << 16)
 123 #define HSI2C_TIMEOUT_AUTO                      (1u << 4)
 124 #define HSI2C_NO_DEV                            (1u << 3)
 125 #define HSI2C_NO_DEV_ACK                        (1u << 2)
 126 #define HSI2C_TRANS_ABORT                       (1u << 1)
 127 #define HSI2C_TRANS_DONE                        (1u << 0)
 128
 129 /* I2C_ADDR register bits */
 130 #define HSI2C_SLV_ADDR_SLV(x)                   ((x & 0x3ff) << 0)
 131 #define HSI2C_SLV_ADDR_MAS(x)                   ((x & 0x3ff) << 10)
 132 #define HSI2C_MASTER_ID(x)                      ((x & 0xff) << 24)
 133 #define MASTER_ID(x)                            ((x & 0x7) + 0x08)
 134
 135 /*
 136  * Controller operating frequency, timing values for operation
 137  * are calculated against this frequency
 138  */
 139 #define HSI2C_HS_TX_CLOCK       1000000
 140 #define HSI2C_FS_TX_CLOCK       100000
 141 #define HSI2C_HIGH_SPD          1
 142 #define HSI2C_FAST_SPD          0
 143
 144 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
 145
 146 struct exynos5_i2c {
 147         struct i2c_adapter      adap;
 148         unsigned int            suspended:1;
 149
 150         struct i2c_msg          *msg;
 151         struct completion       msg_complete;
 152         unsigned int            msg_ptr;
 153
 154         unsigned int            irq;
 155
 156         void __iomem            *regs;
 157         struct clk              *clk;
 158         struct device           *dev;
 159         int                     state;
 160
 161         spinlock_t              lock;           /* IRQ synchronization */
 162
 163         /*
 164          * Since the TRANS_DONE bit is cleared on read, and we may read it
 165          * either during an IRQ or after a transaction, keep track of its
 166          * state here.
 167          */
 168         int                     trans_done;
 169
 170         /* Controller operating frequency */
 171         unsigned int            fs_clock;
 172         unsigned int            hs_clock;
 173
 174         /*
 175          * HSI2C Controller can operate in
 176          * 1. High speed upto 3.4Mbps
 177          * 2. Fast speed upto 1Mbps
 178          */
 179         int                     speed_mode;
 180
 181         /* Version of HS-I2C Hardware */
 182         struct exynos_hsi2c_variant     *variant;
 183 };
 184
 185 /**
 186  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
 187  * @fifo_depth: the fifo depth supported by the HSI2C module
 188  *
 189  * Specifies platform specific configuration of HSI2C module.
 190  * Note: A structure for driver specific platform data is used for future
 191  * expansion of its usage.
 192  */
 193 struct exynos_hsi2c_variant {
 194         unsigned int    fifo_depth;
 195 };
 196
 197 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 198         .fifo_depth     = 64,
 199 };
 200
 201 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 202         .fifo_depth     = 16,
 203 };
 204
 205 static const struct of_device_id exynos5_i2c_match[] = {
 206         {
 207                 .compatible = "samsung,exynos5-hsi2c",
 208                 .data = &exynos5250_hsi2c_data
 209         }, {
 210                 .compatible = "samsung,exynos5250-hsi2c",
 211                 .data = &exynos5250_hsi2c_data
 212         }, {
 213                 .compatible = "samsung,exynos5260-hsi2c",
 214                 .data = &exynos5260_hsi2c_data
 215         }, {},
 216 };
 217 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 218
 219 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
 220                                         (struct platform_device *pdev)
 221 {
 222         const struct of_device_id *match;
 223
 224         match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
 225         return (struct exynos_hsi2c_variant *)match->data;
 226 }
 227
 228 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
 229 {
 230         writel(readl(i2c->regs + HSI2C_INT_STATUS),
 231                                 i2c->regs + HSI2C_INT_STATUS);
 232 }
 233
 234 /*
 235  * exynos5_i2c_set_timing: updates the registers with appropriate
 236  * timing values calculated
 237  *
 238  * Returns 0 on success, -EINVAL if the cycle length cannot
 239  * be calculated.
 240  */
 241 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
 242 {
 243         u32 i2c_timing_s1;
 244         u32 i2c_timing_s2;
 245         u32 i2c_timing_s3;
 246         u32 i2c_timing_sla;
 247         unsigned int t_start_su, t_start_hd;
 248         unsigned int t_stop_su;
 249         unsigned int t_data_su, t_data_hd;
 250         unsigned int t_scl_l, t_scl_h;
 251         unsigned int t_sr_release;
 252         unsigned int t_ftl_cycle;
 253         unsigned int clkin = clk_get_rate(i2c->clk);
 254         unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
 255         unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
 256                                 i2c->hs_clock : i2c->fs_clock;
 257
 258         /*
 259          * FPCLK / FI2C =
 260          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 261          * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 262          * utemp1 = (TSCLK_L + TSCLK_H + 2)
 263          */
 264         t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
 265         utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
 266
 267         /* CLK_DIV max is 256 */
 268         for (div = 0; div < 256; div++) {
 269                 utemp1 = utemp0 / (div + 1);
 270
 271                 /*
 272                  * SCL_L and SCL_H each has max value of 255
 273                  * Hence, For the clk_cycle to the have right value
 274                  * utemp1 has to be less then 512 and more than 4.
 275                  */
 276                 if ((utemp1 < 512) && (utemp1 > 4)) {
 277                         clk_cycle = utemp1 - 2;
 278                         break;
 279                 } else if (div == 255) {
 280                         dev_warn(i2c->dev, "Failed to calculate divisor");
 281                         return -EINVAL;
 282                 }
 283         }
 284
 285         t_scl_l = clk_cycle / 2;
 286         t_scl_h = clk_cycle / 2;
 287         t_start_su = t_scl_l;
 288         t_start_hd = t_scl_l;
 289         t_stop_su = t_scl_l;
 290         t_data_su = t_scl_l / 2;
 291         t_data_hd = t_scl_l / 2;
 292         t_sr_release = clk_cycle;
 293
 294         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 295         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 296         i2c_timing_s3 = div << 16 | t_sr_release << 0;
 297         i2c_timing_sla = t_data_hd << 0;
 298
 299         dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
 300                 t_start_su, t_start_hd, t_stop_su);
 301         dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
 302                 t_data_su, t_scl_l, t_scl_h);
 303         dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
 304                 div, t_sr_release);
 305         dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 306
 307         if (mode == HSI2C_HIGH_SPD) {
 308                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
 309                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
 310                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
 311         } else {
 312                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
 313                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
 314                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
 315         }
 316         writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
 317
 318         return 0;
 319 }
 320
 321 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 322 {
 323         /*
 324          * Configure the Fast speed timing values
 325          * Even the High Speed mode initially starts with Fast mode
 326          */
 327         if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
 328                 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
 329                 return -EINVAL;
 330         }
 331
 332         /* configure the High speed timing values */
 333         if (i2c->speed_mode == HSI2C_HIGH_SPD) {
 334                 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
 335                         dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
 336                         return -EINVAL;
 337                 }
 338         }
 339
 340         return 0;
 341 }
 342
 343 /*
 344  * exynos5_i2c_init: configures the controller for I2C functionality
 345  * Programs I2C controller for Master mode operation
 346  */
 347 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
 348 {
 349         u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
 350         u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
 351
 352         /* Clear to disable Timeout */
 353         i2c_timeout &= ~HSI2C_TIMEOUT_EN;
 354         writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
 355
 356         writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 357                                         i2c->regs + HSI2C_CTL);
 358         writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 359
 360         if (i2c->speed_mode == HSI2C_HIGH_SPD) {
 361                 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
 362                                         i2c->regs + HSI2C_ADDR);
 363                 i2c_conf |= HSI2C_HS_MODE;
 364         }
 365
 366         writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
 367 }
 368
 369 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 370 {
 371         u32 i2c_ctl;
 372
 373         /* Set and clear the bit for reset */
 374         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 375         i2c_ctl |= HSI2C_SW_RST;
 376         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 377
 378         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 379         i2c_ctl &= ~HSI2C_SW_RST;
 380         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 381
 382         /* We don't expect calculations to fail during the run */
 383         exynos5_hsi2c_clock_setup(i2c);
 384         /* Initialize the configure registers */
 385         exynos5_i2c_init(i2c);
 386 }
 387
 388 /*
 389  * exynos5_i2c_irq: top level IRQ servicing routine
 390  *
 391  * INT_STATUS registers gives the interrupt details. Further,
 392  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
 393  * state of the bus.
 394  */
 395 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 396 {
 397         struct exynos5_i2c *i2c = dev_id;
 398         u32 fifo_level, int_status, fifo_status, trans_status;
 399         unsigned char byte;
 400         int len = 0;
 401
 402         i2c->state = -EINVAL;
 403
 404         spin_lock(&i2c->lock);
 405
 406         int_status = readl(i2c->regs + HSI2C_INT_STATUS);
 407         writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 408         fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 409
 410         /* handle interrupt related to the transfer status */
 411         if (int_status & HSI2C_INT_I2C) {
 412                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 413                 if (trans_status & HSI2C_NO_DEV_ACK) {
 414                         dev_dbg(i2c->dev, "No ACK from device\n");
 415                         i2c->state = -ENXIO;
 416                         goto stop;
 417                 } else if (trans_status & HSI2C_NO_DEV) {
 418                         dev_dbg(i2c->dev, "No device\n");
 419                         i2c->state = -ENXIO;
 420                         goto stop;
 421                 } else if (trans_status & HSI2C_TRANS_ABORT) {
 422                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 423                         i2c->state = -EAGAIN;
 424                         goto stop;
 425                 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
 426                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 427                         i2c->state = -EAGAIN;
 428                         goto stop;
 429                 } else if (trans_status & HSI2C_TRANS_DONE) {
 430                         i2c->trans_done = 1;
 431                         i2c->state = 0;
 432                 }
 433         }
 434
 435         if ((i2c->msg->flags & I2C_M_RD) && (int_status &
 436                         (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
 437                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 438                 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
 439                 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
 440
 441                 while (len > 0) {
 442                         byte = (unsigned char)
 443                                 readl(i2c->regs + HSI2C_RX_DATA);
 444                         i2c->msg->buf[i2c->msg_ptr++] = byte;
 445                         len--;
 446                 }
 447                 i2c->state = 0;
 448         } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
 449                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 450                 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
 451
 452                 len = i2c->variant->fifo_depth - fifo_level;
 453                 if (len > (i2c->msg->len - i2c->msg_ptr))
 454                         len = i2c->msg->len - i2c->msg_ptr;
 455
 456                 while (len > 0) {
 457                         byte = i2c->msg->buf[i2c->msg_ptr++];
 458                         writel(byte, i2c->regs + HSI2C_TX_DATA);
 459                         len--;
 460                 }
 461                 i2c->state = 0;
 462         }
 463
 464  stop:
 465         if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
 466             (i2c->state < 0)) {
 467                 writel(0, i2c->regs + HSI2C_INT_ENABLE);
 468                 exynos5_i2c_clr_pend_irq(i2c);
 469                 complete(&i2c->msg_complete);
 470         }
 471
 472         spin_unlock(&i2c->lock);
 473
 474         return IRQ_HANDLED;
 475 }
 476
 477 /*
 478  * exynos5_i2c_wait_bus_idle
 479  *
 480  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
 481  * cleared.
 482  *
 483  * Returns -EBUSY if the bus cannot be bought to idle
 484  */
 485 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
 486 {
 487         unsigned long stop_time;
 488         u32 trans_status;
 489
 490         /* wait for 100 milli seconds for the bus to be idle */
 491         stop_time = jiffies + msecs_to_jiffies(100) + 1;
 492         do {
 493                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 494                 if (!(trans_status & HSI2C_MASTER_BUSY))
 495                         return 0;
 496
 497                 usleep_range(50, 200);
 498         } while (time_before(jiffies, stop_time));
 499
 500         return -EBUSY;
 501 }
 502
 503 /*
 504  * exynos5_i2c_message_start: Configures the bus and starts the xfer
 505  * i2c: struct exynos5_i2c pointer for the current bus
 506  * stop: Enables stop after transfer if set. Set for last transfer of
 507  *       in the list of messages.
 508  *
 509  * Configures the bus for read/write function
 510  * Sets chip address to talk to, message length to be sent.
 511  * Enables appropriate interrupts and sends start xfer command.
 512  */
 513 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 514 {
 515         u32 i2c_ctl;
 516         u32 int_en = HSI2C_INT_I2C_EN;
 517         u32 i2c_auto_conf = 0;
 518         u32 fifo_ctl;
 519         unsigned long flags;
 520         unsigned short trig_lvl;
 521
 522         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 523         i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
 524         fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
 525
 526         if (i2c->msg->flags & I2C_M_RD) {
 527                 i2c_ctl |= HSI2C_RXCHON;
 528
 529                 i2c_auto_conf = HSI2C_READ_WRITE;
 530
 531                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 532                         (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
 533                 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
 534
 535                 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
 536                         HSI2C_INT_TRAILING_EN);
 537         } else {
 538                 i2c_ctl |= HSI2C_TXCHON;
 539
 540                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 541                         (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
 542                 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
 543
 544                 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
 545         }
 546
 547         writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
 548
 549         writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
 550         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 551
 552
 553         /*
 554          * Enable interrupts before starting the transfer so that we don't
 555          * miss any INT_I2C interrupts.
 556          */
 557         spin_lock_irqsave(&i2c->lock, flags);
 558         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 559
 560         if (stop == 1)
 561                 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
 562         i2c_auto_conf |= i2c->msg->len;
 563         i2c_auto_conf |= HSI2C_MASTER_RUN;
 564         writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
 565         spin_unlock_irqrestore(&i2c->lock, flags);
 566 }
 567
 568 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
 569                               struct i2c_msg *msgs, int stop)
 570 {
 571         unsigned long timeout;
 572         int ret;
 573
 574         i2c->msg = msgs;
 575         i2c->msg_ptr = 0;
 576         i2c->trans_done = 0;
 577
 578         reinit_completion(&i2c->msg_complete);
 579
 580         exynos5_i2c_message_start(i2c, stop);
 581
 582         timeout = wait_for_completion_timeout(&i2c->msg_complete,
 583                                               EXYNOS5_I2C_TIMEOUT);
 584         if (timeout == 0)
 585                 ret = -ETIMEDOUT;
 586         else
 587                 ret = i2c->state;
 588
 589         /*
 590          * If this is the last message to be transfered (stop == 1)
 591          * Then check if the bus can be brought back to idle.
 592          */
 593         if (ret == 0 && stop)
 594                 ret = exynos5_i2c_wait_bus_idle(i2c);
 595
 596         if (ret < 0) {
 597                 exynos5_i2c_reset(i2c);
 598                 if (ret == -ETIMEDOUT)
 599                         dev_warn(i2c->dev, "%s timeout\n",
 600                                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
 601         }
 602
 603         /* Return the state as in interrupt routine */
 604         return ret;
 605 }
 606
 607 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
 608                         struct i2c_msg *msgs, int num)
 609 {
 610         struct exynos5_i2c *i2c = adap->algo_data;
 611         int i = 0, ret = 0, stop = 0;
 612
 613         if (i2c->suspended) {
 614                 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
 615                 return -EIO;
 616         }
 617
 618         clk_prepare_enable(i2c->clk);
 619
 620         for (i = 0; i < num; i++, msgs++) {
 621                 stop = (i == num - 1);
 622
 623                 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
 624
 625                 if (ret < 0)
 626                         goto out;
 627         }
 628
 629         if (i == num) {
 630                 ret = num;
 631         } else {
 632                 /* Only one message, cannot access the device */
 633                 if (i == 1)
 634                         ret = -EREMOTEIO;
 635                 else
 636                         ret = i;
 637
 638                 dev_warn(i2c->dev, "xfer message failed\n");
 639         }
 640
 641  out:
 642         clk_disable_unprepare(i2c->clk);
 643         return ret;
 644 }
 645
 646 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
 647 {
 648         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 649 }
 650
 651 static const struct i2c_algorithm exynos5_i2c_algorithm = {
 652         .master_xfer            = exynos5_i2c_xfer,
 653         .functionality          = exynos5_i2c_func,
 654 };
 655
 656 static int exynos5_i2c_probe(struct platform_device *pdev)
 657 {
 658         struct device_node *np = pdev->dev.of_node;
 659         struct exynos5_i2c *i2c;
 660         struct resource *mem;
 661         unsigned int op_clock;
 662         int ret;
 663
 664         i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
 665         if (!i2c)
 666                 return -ENOMEM;
 667
 668         if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
 669                 i2c->speed_mode = HSI2C_FAST_SPD;
 670                 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
 671         } else {
 672                 if (op_clock >= HSI2C_HS_TX_CLOCK) {
 673                         i2c->speed_mode = HSI2C_HIGH_SPD;
 674                         i2c->fs_clock = HSI2C_FS_TX_CLOCK;
 675                         i2c->hs_clock = op_clock;
 676                 } else {
 677                         i2c->speed_mode = HSI2C_FAST_SPD;
 678                         i2c->fs_clock = op_clock;
 679                 }
 680         }
 681
 682         strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
 683         i2c->adap.owner   = THIS_MODULE;
 684         i2c->adap.algo    = &exynos5_i2c_algorithm;
 685         i2c->adap.retries = 3;
 686
 687         i2c->dev = &pdev->dev;
 688         i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
 689         if (IS_ERR(i2c->clk)) {
 690                 dev_err(&pdev->dev, "cannot get clock\n");
 691                 return -ENOENT;
 692         }
 693
 694         clk_prepare_enable(i2c->clk);
 695
 696         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 697         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 698         if (IS_ERR(i2c->regs)) {
 699                 ret = PTR_ERR(i2c->regs);
 700                 goto err_clk;
 701         }
 702
 703         i2c->adap.dev.of_node = np;
 704         i2c->adap.algo_data = i2c;
 705         i2c->adap.dev.parent = &pdev->dev;
 706
 707         /* Clear pending interrupts from u-boot or misc causes */
 708         exynos5_i2c_clr_pend_irq(i2c);
 709
 710         spin_lock_init(&i2c->lock);
 711         init_completion(&i2c->msg_complete);
 712
 713         i2c->irq = ret = platform_get_irq(pdev, 0);
 714         if (ret <= 0) {
 715                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 716                 ret = -EINVAL;
 717                 goto err_clk;
 718         }
 719
 720         ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
 721                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 722                                 dev_name(&pdev->dev), i2c);
 723
 724         if (ret != 0) {
 725                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
 726                 goto err_clk;
 727         }
 728
 729         ret = exynos5_hsi2c_clock_setup(i2c);
 730         if (ret)
 731                 goto err_clk;
 732
 733         i2c->variant = exynos5_i2c_get_variant(pdev);
 734
 735         exynos5_i2c_reset(i2c);
 736
 737         ret = i2c_add_adapter(&i2c->adap);
 738         if (ret < 0) {
 739                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 740                 goto err_clk;
 741         }
 742
 743         platform_set_drvdata(pdev, i2c);
 744
 745  err_clk:
 746         clk_disable_unprepare(i2c->clk);
 747         return ret;
 748 }
 749
 750 static int exynos5_i2c_remove(struct platform_device *pdev)
 751 {
 752         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 753
 754         i2c_del_adapter(&i2c->adap);
 755
 756         return 0;
 757 }
 758
 759 #ifdef CONFIG_PM_SLEEP
 760 static int exynos5_i2c_suspend_noirq(struct device *dev)
 761 {
 762         struct platform_device *pdev = to_platform_device(dev);
 763         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 764
 765         i2c->suspended = 1;
 766
 767         return 0;
 768 }
 769
 770 static int exynos5_i2c_resume_noirq(struct device *dev)
 771 {
 772         struct platform_device *pdev = to_platform_device(dev);
 773         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 774         int ret = 0;
 775
 776         clk_prepare_enable(i2c->clk);
 777
 778         ret = exynos5_hsi2c_clock_setup(i2c);
 779         if (ret) {
 780                 clk_disable_unprepare(i2c->clk);
 781                 return ret;
 782         }
 783
 784         exynos5_i2c_init(i2c);
 785         clk_disable_unprepare(i2c->clk);
 786         i2c->suspended = 0;
 787
 788         return 0;
 789 }
 790 #endif
 791
 792 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
 793 #ifdef CONFIG_PM_SLEEP
 794         .suspend_noirq = exynos5_i2c_suspend_noirq,
 795         .resume_noirq = exynos5_i2c_resume_noirq,
 796         .freeze_noirq = exynos5_i2c_suspend_noirq,
 797         .thaw_noirq = exynos5_i2c_resume_noirq,
 798         .poweroff_noirq = exynos5_i2c_suspend_noirq,
 799         .restore_noirq = exynos5_i2c_resume_noirq,
 800 #endif
 801 };
 802
 803 static struct platform_driver exynos5_i2c_driver = {
 804         .probe          = exynos5_i2c_probe,
 805         .remove         = exynos5_i2c_remove,
 806         .driver         = {
 807                 .owner  = THIS_MODULE,
 808                 .name   = "exynos5-hsi2c",
 809                 .pm     = &exynos5_i2c_dev_pm_ops,
 810                 .of_match_table = exynos5_i2c_match,
 811         },
 812 };
 813
 814 module_platform_driver(exynos5_i2c_driver);
 815
 816 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
 817 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
 818 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
 819 MODULE_LICENSE("GPL v2");