drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  *
  63  * Features supported by this driver:
  64  * Software PEC                         no
  65  * Hardware PEC                         yes
  66  * Block buffer                         yes
  67  * Block process call transaction       no
  68  * I2C block read transaction           yes (doesn't use the block buffer)
  69  * Slave mode                           no
  70  * Interrupt processing                 yes
  71  *
  72  * See the file Documentation/i2c/busses/i2c-i801 for details.
  73  */
  74
  75 #include <linux/interrupt.h>
  76 #include <linux/module.h>
  77 #include <linux/pci.h>
  78 #include <linux/kernel.h>
  79 #include <linux/stddef.h>
  80 #include <linux/delay.h>
  81 #include <linux/ioport.h>
  82 #include <linux/init.h>
  83 #include <linux/i2c.h>
  84 #include <linux/acpi.h>
  85 #include <linux/io.h>
  86 #include <linux/dmi.h>
  87 #include <linux/slab.h>
  88 #include <linux/wait.h>
  89 #include <linux/err.h>
  90
  91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  92                 defined CONFIG_DMI
  93 #include <linux/gpio.h>
  94 #include <linux/i2c-mux-gpio.h>
  95 #include <linux/platform_device.h>
  96 #endif
  97
  98 /* I801 SMBus address offsets */
  99 #define SMBHSTSTS(p)    (0 + (p)->smba)
 100 #define SMBHSTCNT(p)    (2 + (p)->smba)
 101 #define SMBHSTCMD(p)    (3 + (p)->smba)
 102 #define SMBHSTADD(p)    (4 + (p)->smba)
 103 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 104 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 105 #define SMBBLKDAT(p)    (7 + (p)->smba)
 106 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 107 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 108 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 109
 110 /* PCI Address Constants */
 111 #define SMBBAR          4
 112 #define SMBPCICTL       0x004
 113 #define SMBPCISTS       0x006
 114 #define SMBHSTCFG       0x040
 115
 116 /* Host status bits for SMBPCISTS */
 117 #define SMBPCISTS_INTS          0x08
 118
 119 /* Control bits for SMBPCICTL */
 120 #define SMBPCICTL_INTDIS        0x0400
 121
 122 /* Host configuration bits for SMBHSTCFG */
 123 #define SMBHSTCFG_HST_EN        1
 124 #define SMBHSTCFG_SMB_SMI_EN    2
 125 #define SMBHSTCFG_I2C_EN        4
 126
 127 /* Auxiliary control register bits, ICH4+ only */
 128 #define SMBAUXCTL_CRC           1
 129 #define SMBAUXCTL_E32B          2
 130
 131 /* Other settings */
 132 #define MAX_RETRIES             400
 133
 134 /* I801 command constants */
 135 #define I801_QUICK              0x00
 136 #define I801_BYTE               0x04
 137 #define I801_BYTE_DATA          0x08
 138 #define I801_WORD_DATA          0x0C
 139 #define I801_PROC_CALL          0x10    /* unimplemented */
 140 #define I801_BLOCK_DATA         0x14
 141 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 142
 143 /* I801 Host Control register bits */
 144 #define SMBHSTCNT_INTREN        0x01
 145 #define SMBHSTCNT_KILL          0x02
 146 #define SMBHSTCNT_LAST_BYTE     0x20
 147 #define SMBHSTCNT_START         0x40
 148 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 149
 150 /* I801 Hosts Status register bits */
 151 #define SMBHSTSTS_BYTE_DONE     0x80
 152 #define SMBHSTSTS_INUSE_STS     0x40
 153 #define SMBHSTSTS_SMBALERT_STS  0x20
 154 #define SMBHSTSTS_FAILED        0x10
 155 #define SMBHSTSTS_BUS_ERR       0x08
 156 #define SMBHSTSTS_DEV_ERR       0x04
 157 #define SMBHSTSTS_INTR          0x02
 158 #define SMBHSTSTS_HOST_BUSY     0x01
 159
 160 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 161                                  SMBHSTSTS_DEV_ERR)
 162
 163 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 164                                  STATUS_ERROR_FLAGS)
 165
 166 /* Older devices have their ID defined in <linux/pci_ids.h> */
 167 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 168 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 169 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 171 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 173 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 174 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 175 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 176 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 177 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 178 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 179 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 180 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 181 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 185 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 186 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 187 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 188 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 189
 190 struct i801_mux_config {
 191         char *gpio_chip;
 192         unsigned values[3];
 193         int n_values;
 194         unsigned classes[3];
 195         unsigned gpios[2];              /* Relative to gpio_chip->base */
 196         int n_gpios;
 197 };
 198
 199 struct i801_priv {
 200         struct i2c_adapter adapter;
 201         unsigned long smba;
 202         unsigned char original_hstcfg;
 203         struct pci_dev *pci_dev;
 204         unsigned int features;
 205
 206         /* isr processing */
 207         wait_queue_head_t waitq;
 208         u8 status;
 209
 210         /* Command state used by isr for byte-by-byte block transactions */
 211         u8 cmd;
 212         bool is_read;
 213         int count;
 214         int len;
 215         u8 *data;
 216
 217 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 218                 defined CONFIG_DMI
 219         const struct i801_mux_config *mux_drvdata;
 220         struct platform_device *mux_pdev;
 221 #endif
 222 };
 223
 224 static struct pci_driver i801_driver;
 225
 226 #define FEATURE_SMBUS_PEC       (1 << 0)
 227 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 228 #define FEATURE_BLOCK_PROC      (1 << 2)
 229 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 230 #define FEATURE_IRQ             (1 << 4)
 231 /* Not really a feature, but it's convenient to handle it as such */
 232 #define FEATURE_IDF             (1 << 15)
 233
 234 static const char *i801_feature_names[] = {
 235         "SMBus PEC",
 236         "Block buffer",
 237         "Block process call",
 238         "I2C block read",
 239         "Interrupt",
 240 };
 241
 242 static unsigned int disable_features;
 243 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 244 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 245         "\t\t  0x01  disable SMBus PEC\n"
 246         "\t\t  0x02  disable the block buffer\n"
 247         "\t\t  0x08  disable the I2C block read functionality\n"
 248         "\t\t  0x10  don't use interrupts ");
 249
 250 /* Make sure the SMBus host is ready to start transmitting.
 251    Return 0 if it is, -EBUSY if it is not. */
 252 static int i801_check_pre(struct i801_priv *priv)
 253 {
 254         int status;
 255
 256         status = inb_p(SMBHSTSTS(priv));
 257         if (status & SMBHSTSTS_HOST_BUSY) {
 258                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 259                 return -EBUSY;
 260         }
 261
 262         status &= STATUS_FLAGS;
 263         if (status) {
 264                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 265                         status);
 266                 outb_p(status, SMBHSTSTS(priv));
 267                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 268                 if (status) {
 269                         dev_err(&priv->pci_dev->dev,
 270                                 "Failed clearing status flags (%02x)\n",
 271                                 status);
 272                         return -EBUSY;
 273                 }
 274         }
 275
 276         return 0;
 277 }
 278
 279 /*
 280  * Convert the status register to an error code, and clear it.
 281  * Note that status only contains the bits we want to clear, not the
 282  * actual register value.
 283  */
 284 static int i801_check_post(struct i801_priv *priv, int status)
 285 {
 286         int result = 0;
 287
 288         /*
 289          * If the SMBus is still busy, we give up
 290          * Note: This timeout condition only happens when using polling
 291          * transactions.  For interrupt operation, NAK/timeout is indicated by
 292          * DEV_ERR.
 293          */
 294         if (unlikely(status < 0)) {
 295                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 296                 /* try to stop the current command */
 297                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 298                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 299                        SMBHSTCNT(priv));
 300                 usleep_range(1000, 2000);
 301                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 302                        SMBHSTCNT(priv));
 303
 304                 /* Check if it worked */
 305                 status = inb_p(SMBHSTSTS(priv));
 306                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 307                     !(status & SMBHSTSTS_FAILED))
 308                         dev_err(&priv->pci_dev->dev,
 309                                 "Failed terminating the transaction\n");
 310                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 311                 return -ETIMEDOUT;
 312         }
 313
 314         if (status & SMBHSTSTS_FAILED) {
 315                 result = -EIO;
 316                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 317         }
 318         if (status & SMBHSTSTS_DEV_ERR) {
 319                 result = -ENXIO;
 320                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 321         }
 322         if (status & SMBHSTSTS_BUS_ERR) {
 323                 result = -EAGAIN;
 324                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 325         }
 326
 327         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 328         outb_p(status, SMBHSTSTS(priv));
 329
 330         return result;
 331 }
 332
 333 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 334 static int i801_wait_intr(struct i801_priv *priv)
 335 {
 336         int timeout = 0;
 337         int status;
 338
 339         /* We will always wait for a fraction of a second! */
 340         do {
 341                 usleep_range(250, 500);
 342                 status = inb_p(SMBHSTSTS(priv));
 343         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 344                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 345                  (timeout++ < MAX_RETRIES));
 346
 347         if (timeout > MAX_RETRIES) {
 348                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 349                 return -ETIMEDOUT;
 350         }
 351         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 352 }
 353
 354 /* Wait for either BYTE_DONE or an error flag being set */
 355 static int i801_wait_byte_done(struct i801_priv *priv)
 356 {
 357         int timeout = 0;
 358         int status;
 359
 360         /* We will always wait for a fraction of a second! */
 361         do {
 362                 usleep_range(250, 500);
 363                 status = inb_p(SMBHSTSTS(priv));
 364         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 365                  (timeout++ < MAX_RETRIES));
 366
 367         if (timeout > MAX_RETRIES) {
 368                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 369                 return -ETIMEDOUT;
 370         }
 371         return status & STATUS_ERROR_FLAGS;
 372 }
 373
 374 static int i801_transaction(struct i801_priv *priv, int xact)
 375 {
 376         int status;
 377         int result;
 378         const struct i2c_adapter *adap = &priv->adapter;
 379
 380         result = i801_check_pre(priv);
 381         if (result < 0)
 382                 return result;
 383
 384         if (priv->features & FEATURE_IRQ) {
 385                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 386                        SMBHSTCNT(priv));
 387                 result = wait_event_timeout(priv->waitq,
 388                                             (status = priv->status),
 389                                             adap->timeout);
 390                 if (!result) {
 391                         status = -ETIMEDOUT;
 392                         dev_warn(&priv->pci_dev->dev,
 393                                  "Timeout waiting for interrupt!\n");
 394                 }
 395                 priv->status = 0;
 396                 return i801_check_post(priv, status);
 397         }
 398
 399         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 400          * SMBSCMD are passed in xact */
 401         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 402
 403         status = i801_wait_intr(priv);
 404         return i801_check_post(priv, status);
 405 }
 406
 407 static int i801_block_transaction_by_block(struct i801_priv *priv,
 408                                            union i2c_smbus_data *data,
 409                                            char read_write, int hwpec)
 410 {
 411         int i, len;
 412         int status;
 413
 414         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 415
 416         /* Use 32-byte buffer to process this transaction */
 417         if (read_write == I2C_SMBUS_WRITE) {
 418                 len = data->block[0];
 419                 outb_p(len, SMBHSTDAT0(priv));
 420                 for (i = 0; i < len; i++)
 421                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 422         }
 423
 424         status = i801_transaction(priv, I801_BLOCK_DATA |
 425                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 426         if (status)
 427                 return status;
 428
 429         if (read_write == I2C_SMBUS_READ) {
 430                 len = inb_p(SMBHSTDAT0(priv));
 431                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 432                         return -EPROTO;
 433
 434                 data->block[0] = len;
 435                 for (i = 0; i < len; i++)
 436                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 437         }
 438         return 0;
 439 }
 440
 441 static void i801_isr_byte_done(struct i801_priv *priv)
 442 {
 443         if (priv->is_read) {
 444                 /* For SMBus block reads, length is received with first byte */
 445                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 446                     (priv->count == 0)) {
 447                         priv->len = inb_p(SMBHSTDAT0(priv));
 448                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 449                                 dev_err(&priv->pci_dev->dev,
 450                                         "Illegal SMBus block read size %d\n",
 451                                         priv->len);
 452                                 /* FIXME: Recover */
 453                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 454                         } else {
 455                                 dev_dbg(&priv->pci_dev->dev,
 456                                         "SMBus block read size is %d\n",
 457                                         priv->len);
 458                         }
 459                         priv->data[-1] = priv->len;
 460                 }
 461
 462                 /* Read next byte */
 463                 if (priv->count < priv->len)
 464                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 465                 else
 466                         dev_dbg(&priv->pci_dev->dev,
 467                                 "Discarding extra byte on block read\n");
 468
 469                 /* Set LAST_BYTE for last byte of read transaction */
 470                 if (priv->count == priv->len - 1)
 471                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 472                                SMBHSTCNT(priv));
 473         } else if (priv->count < priv->len - 1) {
 474                 /* Write next byte, except for IRQ after last byte */
 475                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 476         }
 477
 478         /* Clear BYTE_DONE to continue with next byte */
 479         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 480 }
 481
 482 /*
 483  * There are two kinds of interrupts:
 484  *
 485  * 1) i801 signals transaction completion with one of these interrupts:
 486  *      INTR - Success
 487  *      DEV_ERR - Invalid command, NAK or communication timeout
 488  *      BUS_ERR - SMI# transaction collision
 489  *      FAILED - transaction was canceled due to a KILL request
 490  *    When any of these occur, update ->status and wake up the waitq.
 491  *    ->status must be cleared before kicking off the next transaction.
 492  *
 493  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 494  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 495  */
 496 static irqreturn_t i801_isr(int irq, void *dev_id)
 497 {
 498         struct i801_priv *priv = dev_id;
 499         u16 pcists;
 500         u8 status;
 501
 502         /* Confirm this is our interrupt */
 503         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 504         if (!(pcists & SMBPCISTS_INTS))
 505                 return IRQ_NONE;
 506
 507         status = inb_p(SMBHSTSTS(priv));
 508         if (status != 0x42)
 509                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 510
 511         if (status & SMBHSTSTS_BYTE_DONE)
 512                 i801_isr_byte_done(priv);
 513
 514         /*
 515          * Clear irq sources and report transaction result.
 516          * ->status must be cleared before the next transaction is started.
 517          */
 518         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 519         if (status) {
 520                 outb_p(status, SMBHSTSTS(priv));
 521                 priv->status |= status;
 522                 wake_up(&priv->waitq);
 523         }
 524
 525         return IRQ_HANDLED;
 526 }
 527
 528 /*
 529  * For "byte-by-byte" block transactions:
 530  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 531  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 532  */
 533 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 534                                                union i2c_smbus_data *data,
 535                                                char read_write, int command,
 536                                                int hwpec)
 537 {
 538         int i, len;
 539         int smbcmd;
 540         int status;
 541         int result;
 542         const struct i2c_adapter *adap = &priv->adapter;
 543
 544         result = i801_check_pre(priv);
 545         if (result < 0)
 546                 return result;
 547
 548         len = data->block[0];
 549
 550         if (read_write == I2C_SMBUS_WRITE) {
 551                 outb_p(len, SMBHSTDAT0(priv));
 552                 outb_p(data->block[1], SMBBLKDAT(priv));
 553         }
 554
 555         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 556             read_write == I2C_SMBUS_READ)
 557                 smbcmd = I801_I2C_BLOCK_DATA;
 558         else
 559                 smbcmd = I801_BLOCK_DATA;
 560
 561         if (priv->features & FEATURE_IRQ) {
 562                 priv->is_read = (read_write == I2C_SMBUS_READ);
 563                 if (len == 1 && priv->is_read)
 564                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 565                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 566                 priv->len = len;
 567                 priv->count = 0;
 568                 priv->data = &data->block[1];
 569
 570                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 571                 result = wait_event_timeout(priv->waitq,
 572                                             (status = priv->status),
 573                                             adap->timeout);
 574                 if (!result) {
 575                         status = -ETIMEDOUT;
 576                         dev_warn(&priv->pci_dev->dev,
 577                                  "Timeout waiting for interrupt!\n");
 578                 }
 579                 priv->status = 0;
 580                 return i801_check_post(priv, status);
 581         }
 582
 583         for (i = 1; i <= len; i++) {
 584                 if (i == len && read_write == I2C_SMBUS_READ)
 585                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 586                 outb_p(smbcmd, SMBHSTCNT(priv));
 587
 588                 if (i == 1)
 589                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 590                                SMBHSTCNT(priv));
 591
 592                 status = i801_wait_byte_done(priv);
 593                 if (status)
 594                         goto exit;
 595
 596                 if (i == 1 && read_write == I2C_SMBUS_READ
 597                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 598                         len = inb_p(SMBHSTDAT0(priv));
 599                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 600                                 dev_err(&priv->pci_dev->dev,
 601                                         "Illegal SMBus block read size %d\n",
 602                                         len);
 603                                 /* Recover */
 604                                 while (inb_p(SMBHSTSTS(priv)) &
 605                                        SMBHSTSTS_HOST_BUSY)
 606                                         outb_p(SMBHSTSTS_BYTE_DONE,
 607                                                SMBHSTSTS(priv));
 608                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 609                                 return -EPROTO;
 610                         }
 611                         data->block[0] = len;
 612                 }
 613
 614                 /* Retrieve/store value in SMBBLKDAT */
 615                 if (read_write == I2C_SMBUS_READ)
 616                         data->block[i] = inb_p(SMBBLKDAT(priv));
 617                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 618                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 619
 620                 /* signals SMBBLKDAT ready */
 621                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 622         }
 623
 624         status = i801_wait_intr(priv);
 625 exit:
 626         return i801_check_post(priv, status);
 627 }
 628
 629 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 630 {
 631         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 632         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 633                 return -EIO;
 634         return 0;
 635 }
 636
 637 /* Block transaction function */
 638 static int i801_block_transaction(struct i801_priv *priv,
 639                                   union i2c_smbus_data *data, char read_write,
 640                                   int command, int hwpec)
 641 {
 642         int result = 0;
 643         unsigned char hostc;
 644
 645         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 646                 if (read_write == I2C_SMBUS_WRITE) {
 647                         /* set I2C_EN bit in configuration register */
 648                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 649                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 650                                               hostc | SMBHSTCFG_I2C_EN);
 651                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 652                         dev_err(&priv->pci_dev->dev,
 653                                 "I2C block read is unsupported!\n");
 654                         return -EOPNOTSUPP;
 655                 }
 656         }
 657
 658         if (read_write == I2C_SMBUS_WRITE
 659          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 660                 if (data->block[0] < 1)
 661                         data->block[0] = 1;
 662                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 663                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 664         } else {
 665                 data->block[0] = 32;    /* max for SMBus block reads */
 666         }
 667
 668         /* Experience has shown that the block buffer can only be used for
 669            SMBus (not I2C) block transactions, even though the datasheet
 670            doesn't mention this limitation. */
 671         if ((priv->features & FEATURE_BLOCK_BUFFER)
 672          && command != I2C_SMBUS_I2C_BLOCK_DATA
 673          && i801_set_block_buffer_mode(priv) == 0)
 674                 result = i801_block_transaction_by_block(priv, data,
 675                                                          read_write, hwpec);
 676         else
 677                 result = i801_block_transaction_byte_by_byte(priv, data,
 678                                                              read_write,
 679                                                              command, hwpec);
 680
 681         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 682          && read_write == I2C_SMBUS_WRITE) {
 683                 /* restore saved configuration register value */
 684                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 685         }
 686         return result;
 687 }
 688
 689 /* Return negative errno on error. */
 690 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 691                        unsigned short flags, char read_write, u8 command,
 692                        int size, union i2c_smbus_data *data)
 693 {
 694         int hwpec;
 695         int block = 0;
 696         int ret, xact = 0;
 697         struct i801_priv *priv = i2c_get_adapdata(adap);
 698
 699         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 700                 && size != I2C_SMBUS_QUICK
 701                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 702
 703         switch (size) {
 704         case I2C_SMBUS_QUICK:
 705                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 706                        SMBHSTADD(priv));
 707                 xact = I801_QUICK;
 708                 break;
 709         case I2C_SMBUS_BYTE:
 710                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 711                        SMBHSTADD(priv));
 712                 if (read_write == I2C_SMBUS_WRITE)
 713                         outb_p(command, SMBHSTCMD(priv));
 714                 xact = I801_BYTE;
 715                 break;
 716         case I2C_SMBUS_BYTE_DATA:
 717                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 718                        SMBHSTADD(priv));
 719                 outb_p(command, SMBHSTCMD(priv));
 720                 if (read_write == I2C_SMBUS_WRITE)
 721                         outb_p(data->byte, SMBHSTDAT0(priv));
 722                 xact = I801_BYTE_DATA;
 723                 break;
 724         case I2C_SMBUS_WORD_DATA:
 725                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 726                        SMBHSTADD(priv));
 727                 outb_p(command, SMBHSTCMD(priv));
 728                 if (read_write == I2C_SMBUS_WRITE) {
 729                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 730                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 731                 }
 732                 xact = I801_WORD_DATA;
 733                 break;
 734         case I2C_SMBUS_BLOCK_DATA:
 735                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 736                        SMBHSTADD(priv));
 737                 outb_p(command, SMBHSTCMD(priv));
 738                 block = 1;
 739                 break;
 740         case I2C_SMBUS_I2C_BLOCK_DATA:
 741                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 742                  * bit should be cleared here, even when reading */
 743                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 744                 if (read_write == I2C_SMBUS_READ) {
 745                         /* NB: page 240 of ICH5 datasheet also shows
 746                          * that DATA1 is the cmd field when reading */
 747                         outb_p(command, SMBHSTDAT1(priv));
 748                 } else
 749                         outb_p(command, SMBHSTCMD(priv));
 750                 block = 1;
 751                 break;
 752         default:
 753                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 754                         size);
 755                 return -EOPNOTSUPP;
 756         }
 757
 758         if (hwpec)      /* enable/disable hardware PEC */
 759                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 760         else
 761                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 762                        SMBAUXCTL(priv));
 763
 764         if (block)
 765                 ret = i801_block_transaction(priv, data, read_write, size,
 766                                              hwpec);
 767         else
 768                 ret = i801_transaction(priv, xact);
 769
 770         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 771            time, so we forcibly disable it after every transaction. Turn off
 772            E32B for the same reason. */
 773         if (hwpec || block)
 774                 outb_p(inb_p(SMBAUXCTL(priv)) &
 775                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 776
 777         if (block)
 778                 return ret;
 779         if (ret)
 780                 return ret;
 781         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 782                 return 0;
 783
 784         switch (xact & 0x7f) {
 785         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 786         case I801_BYTE_DATA:
 787                 data->byte = inb_p(SMBHSTDAT0(priv));
 788                 break;
 789         case I801_WORD_DATA:
 790                 data->word = inb_p(SMBHSTDAT0(priv)) +
 791                              (inb_p(SMBHSTDAT1(priv)) << 8);
 792                 break;
 793         }
 794         return 0;
 795 }
 796
 797
 798 static u32 i801_func(struct i2c_adapter *adapter)
 799 {
 800         struct i801_priv *priv = i2c_get_adapdata(adapter);
 801
 802         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 803                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 804                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 805                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 806                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 807                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 808 }
 809
 810 static const struct i2c_algorithm smbus_algorithm = {
 811         .smbus_xfer     = i801_access,
 812         .functionality  = i801_func,
 813 };
 814
 815 static const struct pci_device_id i801_ids[] = {
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 829         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 830         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 831         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 832         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 833         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 834         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 835         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 836         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 837         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 838         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 839         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 840         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 841         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 842         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 843         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 844         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 845         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 846         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 847         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 848         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 849         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 850         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 851         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 852         { 0, }
 853 };
 854
 855 MODULE_DEVICE_TABLE(pci, i801_ids);
 856
 857 #if defined CONFIG_X86 && defined CONFIG_DMI
 858 static unsigned char apanel_addr;
 859
 860 /* Scan the system ROM for the signature "FJKEYINF" */
 861 static __init const void __iomem *bios_signature(const void __iomem *bios)
 862 {
 863         ssize_t offset;
 864         const unsigned char signature[] = "FJKEYINF";
 865
 866         for (offset = 0; offset < 0x10000; offset += 0x10) {
 867                 if (check_signature(bios + offset, signature,
 868                                     sizeof(signature)-1))
 869                         return bios + offset;
 870         }
 871         return NULL;
 872 }
 873
 874 static void __init input_apanel_init(void)
 875 {
 876         void __iomem *bios;
 877         const void __iomem *p;
 878
 879         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 880         p = bios_signature(bios);
 881         if (p) {
 882                 /* just use the first address */
 883                 apanel_addr = readb(p + 8 + 3) >> 1;
 884         }
 885         iounmap(bios);
 886 }
 887
 888 struct dmi_onboard_device_info {
 889         const char *name;
 890         u8 type;
 891         unsigned short i2c_addr;
 892         const char *i2c_type;
 893 };
 894
 895 static const struct dmi_onboard_device_info dmi_devices[] = {
 896         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 897         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 898         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 899 };
 900
 901 static void dmi_check_onboard_device(u8 type, const char *name,
 902                                      struct i2c_adapter *adap)
 903 {
 904         int i;
 905         struct i2c_board_info info;
 906
 907         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 908                 /* & ~0x80, ignore enabled/disabled bit */
 909                 if ((type & ~0x80) != dmi_devices[i].type)
 910                         continue;
 911                 if (strcasecmp(name, dmi_devices[i].name))
 912                         continue;
 913
 914                 memset(&info, 0, sizeof(struct i2c_board_info));
 915                 info.addr = dmi_devices[i].i2c_addr;
 916                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 917                 i2c_new_device(adap, &info);
 918                 break;
 919         }
 920 }
 921
 922 /* We use our own function to check for onboard devices instead of
 923    dmi_find_device() as some buggy BIOS's have the devices we are interested
 924    in marked as disabled */
 925 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 926 {
 927         int i, count;
 928
 929         if (dm->type != 10)
 930                 return;
 931
 932         count = (dm->length - sizeof(struct dmi_header)) / 2;
 933         for (i = 0; i < count; i++) {
 934                 const u8 *d = (char *)(dm + 1) + (i * 2);
 935                 const char *name = ((char *) dm) + dm->length;
 936                 u8 type = d[0];
 937                 u8 s = d[1];
 938
 939                 if (!s)
 940                         continue;
 941                 s--;
 942                 while (s > 0 && name[0]) {
 943                         name += strlen(name) + 1;
 944                         s--;
 945                 }
 946                 if (name[0] == 0) /* Bogus string reference */
 947                         continue;
 948
 949                 dmi_check_onboard_device(type, name, adap);
 950         }
 951 }
 952
 953 /* Register optional slaves */
 954 static void i801_probe_optional_slaves(struct i801_priv *priv)
 955 {
 956         /* Only register slaves on main SMBus channel */
 957         if (priv->features & FEATURE_IDF)
 958                 return;
 959
 960         if (apanel_addr) {
 961                 struct i2c_board_info info;
 962
 963                 memset(&info, 0, sizeof(struct i2c_board_info));
 964                 info.addr = apanel_addr;
 965                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 966                 i2c_new_device(&priv->adapter, &info);
 967         }
 968
 969         if (dmi_name_in_vendors("FUJITSU"))
 970                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 971 }
 972 #else
 973 static void __init input_apanel_init(void) {}
 974 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 975 #endif  /* CONFIG_X86 && CONFIG_DMI */
 976
 977 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 978                 defined CONFIG_DMI
 979 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 980         .gpio_chip = "gpio_ich",
 981         .values = { 0x02, 0x03 },
 982         .n_values = 2,
 983         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 984         .gpios = { 52, 53 },
 985         .n_gpios = 2,
 986 };
 987
 988 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 989         .gpio_chip = "gpio_ich",
 990         .values = { 0x02, 0x03, 0x01 },
 991         .n_values = 3,
 992         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 993         .gpios = { 52, 53 },
 994         .n_gpios = 2,
 995 };
 996
 997 static const struct dmi_system_id mux_dmi_table[] = {
 998         {
 999                 .matches = {
1000                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1001                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1002                 },
1003                 .driver_data = &i801_mux_config_asus_z8_d12,
1004         },
1005         {
1006                 .matches = {
1007                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1008                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1009                 },
1010                 .driver_data = &i801_mux_config_asus_z8_d12,
1011         },
1012         {
1013                 .matches = {
1014                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1015                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1016                 },
1017                 .driver_data = &i801_mux_config_asus_z8_d12,
1018         },
1019         {
1020                 .matches = {
1021                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1022                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1023                 },
1024                 .driver_data = &i801_mux_config_asus_z8_d12,
1025         },
1026         {
1027                 .matches = {
1028                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1029                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1030                 },
1031                 .driver_data = &i801_mux_config_asus_z8_d12,
1032         },
1033         {
1034                 .matches = {
1035                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1036                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1037                 },
1038                 .driver_data = &i801_mux_config_asus_z8_d12,
1039         },
1040         {
1041                 .matches = {
1042                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1043                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1044                 },
1045                 .driver_data = &i801_mux_config_asus_z8_d18,
1046         },
1047         {
1048                 .matches = {
1049                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1050                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1051                 },
1052                 .driver_data = &i801_mux_config_asus_z8_d18,
1053         },
1054         {
1055                 .matches = {
1056                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1057                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1058                 },
1059                 .driver_data = &i801_mux_config_asus_z8_d12,
1060         },
1061         { }
1062 };
1063
1064 /* Setup multiplexing if needed */
1065 static int i801_add_mux(struct i801_priv *priv)
1066 {
1067         struct device *dev = &priv->adapter.dev;
1068         const struct i801_mux_config *mux_config;
1069         struct i2c_mux_gpio_platform_data gpio_data;
1070         int err;
1071
1072         if (!priv->mux_drvdata)
1073                 return 0;
1074         mux_config = priv->mux_drvdata;
1075
1076         /* Prepare the platform data */
1077         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1078         gpio_data.parent = priv->adapter.nr;
1079         gpio_data.values = mux_config->values;
1080         gpio_data.n_values = mux_config->n_values;
1081         gpio_data.classes = mux_config->classes;
1082         gpio_data.gpio_chip = mux_config->gpio_chip;
1083         gpio_data.gpios = mux_config->gpios;
1084         gpio_data.n_gpios = mux_config->n_gpios;
1085         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1086
1087         /* Register the mux device */
1088         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1089                                 PLATFORM_DEVID_AUTO, &gpio_data,
1090                                 sizeof(struct i2c_mux_gpio_platform_data));
1091         if (IS_ERR(priv->mux_pdev)) {
1092                 err = PTR_ERR(priv->mux_pdev);
1093                 priv->mux_pdev = NULL;
1094                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1095                 return err;
1096         }
1097
1098         return 0;
1099 }
1100
1101 static void i801_del_mux(struct i801_priv *priv)
1102 {
1103         if (priv->mux_pdev)
1104                 platform_device_unregister(priv->mux_pdev);
1105 }
1106
1107 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1108 {
1109         const struct dmi_system_id *id;
1110         const struct i801_mux_config *mux_config;
1111         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1112         int i;
1113
1114         id = dmi_first_match(mux_dmi_table);
1115         if (id) {
1116                 /* Remove branch classes from trunk */
1117                 mux_config = id->driver_data;
1118                 for (i = 0; i < mux_config->n_values; i++)
1119                         class &= ~mux_config->classes[i];
1120
1121                 /* Remember for later */
1122                 priv->mux_drvdata = mux_config;
1123         }
1124
1125         return class;
1126 }
1127 #else
1128 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1129 static inline void i801_del_mux(struct i801_priv *priv) { }
1130
1131 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1132 {
1133         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1134 }
1135 #endif
1136
1137 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1138 {
1139         unsigned char temp;
1140         int err, i;
1141         struct i801_priv *priv;
1142
1143         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1144         if (!priv)
1145                 return -ENOMEM;
1146
1147         i2c_set_adapdata(&priv->adapter, priv);
1148         priv->adapter.owner = THIS_MODULE;
1149         priv->adapter.class = i801_get_adapter_class(priv);
1150         priv->adapter.algo = &smbus_algorithm;
1151
1152         priv->pci_dev = dev;
1153         switch (dev->device) {
1154         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1155         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1156         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1157         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1158         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1159         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1160                 priv->features |= FEATURE_IDF;
1161                 /* fall through */
1162         default:
1163                 priv->features |= FEATURE_I2C_BLOCK_READ;
1164                 priv->features |= FEATURE_IRQ;
1165                 /* fall through */
1166         case PCI_DEVICE_ID_INTEL_82801DB_3:
1167                 priv->features |= FEATURE_SMBUS_PEC;
1168                 priv->features |= FEATURE_BLOCK_BUFFER;
1169                 /* fall through */
1170         case PCI_DEVICE_ID_INTEL_82801CA_3:
1171         case PCI_DEVICE_ID_INTEL_82801BA_2:
1172         case PCI_DEVICE_ID_INTEL_82801AB_3:
1173         case PCI_DEVICE_ID_INTEL_82801AA_3:
1174                 break;
1175         }
1176
1177         /* Disable features on user request */
1178         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1179                 if (priv->features & disable_features & (1 << i))
1180                         dev_notice(&dev->dev, "%s disabled by user\n",
1181                                    i801_feature_names[i]);
1182         }
1183         priv->features &= ~disable_features;
1184
1185         err = pci_enable_device(dev);
1186         if (err) {
1187                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1188                         err);
1189                 goto exit;
1190         }
1191
1192         /* Determine the address of the SMBus area */
1193         priv->smba = pci_resource_start(dev, SMBBAR);
1194         if (!priv->smba) {
1195                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1196                         "upgrade BIOS\n");
1197                 err = -ENODEV;
1198                 goto exit;
1199         }
1200
1201         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1202         if (err) {
1203                 err = -ENODEV;
1204                 goto exit;
1205         }
1206
1207         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1208         if (err) {
1209                 dev_err(&dev->dev, "Failed to request SMBus region "
1210                         "0x%lx-0x%Lx\n", priv->smba,
1211                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1212                 goto exit;
1213         }
1214
1215         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1216         priv->original_hstcfg = temp;
1217         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1218         if (!(temp & SMBHSTCFG_HST_EN)) {
1219                 dev_info(&dev->dev, "Enabling SMBus device\n");
1220                 temp |= SMBHSTCFG_HST_EN;
1221         }
1222         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1223
1224         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1225                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1226                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1227                 priv->features &= ~FEATURE_IRQ;
1228         }
1229
1230         /* Clear special mode bits */
1231         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1232                 outb_p(inb_p(SMBAUXCTL(priv)) &
1233                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1234
1235         /* Default timeout in interrupt mode: 200 ms */
1236         priv->adapter.timeout = HZ / 5;
1237
1238         if (priv->features & FEATURE_IRQ) {
1239                 u16 pcictl, pcists;
1240
1241                 /* Complain if an interrupt is already pending */
1242                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1243                 if (pcists & SMBPCISTS_INTS)
1244                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1245
1246                 /* Check if interrupts have been disabled */
1247                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1248                 if (pcictl & SMBPCICTL_INTDIS) {
1249                         dev_info(&dev->dev, "Interrupts are disabled\n");
1250                         priv->features &= ~FEATURE_IRQ;
1251                 }
1252         }
1253
1254         if (priv->features & FEATURE_IRQ) {
1255                 init_waitqueue_head(&priv->waitq);
1256
1257                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1258                                   i801_driver.name, priv);
1259                 if (err) {
1260                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1261                                 dev->irq, err);
1262                         priv->features &= ~FEATURE_IRQ;
1263                 }
1264         }
1265         dev_info(&dev->dev, "SMBus using %s\n",
1266                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1267
1268         /* set up the sysfs linkage to our parent device */
1269         priv->adapter.dev.parent = &dev->dev;
1270
1271         /* Retry up to 3 times on lost arbitration */
1272         priv->adapter.retries = 3;
1273
1274         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1275                 "SMBus I801 adapter at %04lx", priv->smba);
1276         err = i2c_add_adapter(&priv->adapter);
1277         if (err) {
1278                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1279                 goto exit_free_irq;
1280         }
1281
1282         i801_probe_optional_slaves(priv);
1283         /* We ignore errors - multiplexing is optional */
1284         i801_add_mux(priv);
1285
1286         pci_set_drvdata(dev, priv);
1287
1288         return 0;
1289
1290 exit_free_irq:
1291         if (priv->features & FEATURE_IRQ)
1292                 free_irq(dev->irq, priv);
1293         pci_release_region(dev, SMBBAR);
1294 exit:
1295         kfree(priv);
1296         return err;
1297 }
1298
1299 static void i801_remove(struct pci_dev *dev)
1300 {
1301         struct i801_priv *priv = pci_get_drvdata(dev);
1302
1303         i801_del_mux(priv);
1304         i2c_del_adapter(&priv->adapter);
1305         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1306
1307         if (priv->features & FEATURE_IRQ)
1308                 free_irq(dev->irq, priv);
1309         pci_release_region(dev, SMBBAR);
1310
1311         kfree(priv);
1312         /*
1313          * do not call pci_disable_device(dev) since it can cause hard hangs on
1314          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1315          */
1316 }
1317
1318 #ifdef CONFIG_PM
1319 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1320 {
1321         struct i801_priv *priv = pci_get_drvdata(dev);
1322
1323         pci_save_state(dev);
1324         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1325         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1326         return 0;
1327 }
1328
1329 static int i801_resume(struct pci_dev *dev)
1330 {
1331         pci_set_power_state(dev, PCI_D0);
1332         pci_restore_state(dev);
1333         return pci_enable_device(dev);
1334 }
1335 #else
1336 #define i801_suspend NULL
1337 #define i801_resume NULL
1338 #endif
1339
1340 static struct pci_driver i801_driver = {
1341         .name           = "i801_smbus",
1342         .id_table       = i801_ids,
1343         .probe          = i801_probe,
1344         .remove         = i801_remove,
1345         .suspend        = i801_suspend,
1346         .resume         = i801_resume,
1347 };
1348
1349 static int __init i2c_i801_init(void)
1350 {
1351         if (dmi_name_in_vendors("FUJITSU"))
1352                 input_apanel_init();
1353         return pci_register_driver(&i801_driver);
1354 }
1355
1356 static void __exit i2c_i801_exit(void)
1357 {
1358         pci_unregister_driver(&i801_driver);
1359 }
1360
1361 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1362 MODULE_DESCRIPTION("I801 SMBus driver");
1363 MODULE_LICENSE("GPL");
1364
1365 module_init(i2c_i801_init);
1366 module_exit(i2c_i801_exit);