drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  *
  63  * Features supported by this driver:
  64  * Software PEC                         no
  65  * Hardware PEC                         yes
  66  * Block buffer                         yes
  67  * Block process call transaction       no
  68  * I2C block read transaction           yes (doesn't use the block buffer)
  69  * Slave mode                           no
  70  * Interrupt processing                 yes
  71  *
  72  * See the file Documentation/i2c/busses/i2c-i801 for details.
  73  */
  74
  75 #include <linux/interrupt.h>
  76 #include <linux/module.h>
  77 #include <linux/pci.h>
  78 #include <linux/kernel.h>
  79 #include <linux/stddef.h>
  80 #include <linux/delay.h>
  81 #include <linux/ioport.h>
  82 #include <linux/init.h>
  83 #include <linux/i2c.h>
  84 #include <linux/acpi.h>
  85 #include <linux/io.h>
  86 #include <linux/dmi.h>
  87 #include <linux/slab.h>
  88 #include <linux/wait.h>
  89 #include <linux/err.h>
  90
  91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  92                 defined CONFIG_DMI
  93 #include <linux/gpio.h>
  94 #include <linux/i2c-mux-gpio.h>
  95 #include <linux/platform_device.h>
  96 #endif
  97
  98 /* I801 SMBus address offsets */
  99 #define SMBHSTSTS(p)    (0 + (p)->smba)
 100 #define SMBHSTCNT(p)    (2 + (p)->smba)
 101 #define SMBHSTCMD(p)    (3 + (p)->smba)
 102 #define SMBHSTADD(p)    (4 + (p)->smba)
 103 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 104 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 105 #define SMBBLKDAT(p)    (7 + (p)->smba)
 106 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 107 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 108 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 109
 110 /* PCI Address Constants */
 111 #define SMBBAR          4
 112 #define SMBPCICTL       0x004
 113 #define SMBPCISTS       0x006
 114 #define SMBHSTCFG       0x040
 115
 116 /* Host status bits for SMBPCISTS */
 117 #define SMBPCISTS_INTS          0x08
 118
 119 /* Control bits for SMBPCICTL */
 120 #define SMBPCICTL_INTDIS        0x0400
 121
 122 /* Host configuration bits for SMBHSTCFG */
 123 #define SMBHSTCFG_HST_EN        1
 124 #define SMBHSTCFG_SMB_SMI_EN    2
 125 #define SMBHSTCFG_I2C_EN        4
 126
 127 /* Auxiliary control register bits, ICH4+ only */
 128 #define SMBAUXCTL_CRC           1
 129 #define SMBAUXCTL_E32B          2
 130
 131 /* Other settings */
 132 #define MAX_RETRIES             400
 133
 134 /* I801 command constants */
 135 #define I801_QUICK              0x00
 136 #define I801_BYTE               0x04
 137 #define I801_BYTE_DATA          0x08
 138 #define I801_WORD_DATA          0x0C
 139 #define I801_PROC_CALL          0x10    /* unimplemented */
 140 #define I801_BLOCK_DATA         0x14
 141 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 142
 143 /* I801 Host Control register bits */
 144 #define SMBHSTCNT_INTREN        0x01
 145 #define SMBHSTCNT_KILL          0x02
 146 #define SMBHSTCNT_LAST_BYTE     0x20
 147 #define SMBHSTCNT_START         0x40
 148 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 149
 150 /* I801 Hosts Status register bits */
 151 #define SMBHSTSTS_BYTE_DONE     0x80
 152 #define SMBHSTSTS_INUSE_STS     0x40
 153 #define SMBHSTSTS_SMBALERT_STS  0x20
 154 #define SMBHSTSTS_FAILED        0x10
 155 #define SMBHSTSTS_BUS_ERR       0x08
 156 #define SMBHSTSTS_DEV_ERR       0x04
 157 #define SMBHSTSTS_INTR          0x02
 158 #define SMBHSTSTS_HOST_BUSY     0x01
 159
 160 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 161                                  SMBHSTSTS_DEV_ERR)
 162
 163 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 164                                  STATUS_ERROR_FLAGS)
 165
 166 /* Older devices have their ID defined in <linux/pci_ids.h> */
 167 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 168 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 169 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 171 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 173 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 174 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 175 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 176 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 177 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 178 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 179 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 180 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 181 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 185 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 186 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 187 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 188 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 189
 190 struct i801_mux_config {
 191         char *gpio_chip;
 192         unsigned values[3];
 193         int n_values;
 194         unsigned classes[3];
 195         unsigned gpios[2];              /* Relative to gpio_chip->base */
 196         int n_gpios;
 197 };
 198
 199 struct i801_priv {
 200         struct i2c_adapter adapter;
 201         unsigned long smba;
 202         unsigned char original_hstcfg;
 203         struct pci_dev *pci_dev;
 204         unsigned int features;
 205
 206         /* isr processing */
 207         wait_queue_head_t waitq;
 208         u8 status;
 209
 210         /* Command state used by isr for byte-by-byte block transactions */
 211         u8 cmd;
 212         bool is_read;
 213         int count;
 214         int len;
 215         u8 *data;
 216
 217 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 218                 defined CONFIG_DMI
 219         const struct i801_mux_config *mux_drvdata;
 220         struct platform_device *mux_pdev;
 221 #endif
 222 };
 223
 224 static struct pci_driver i801_driver;
 225
 226 #define FEATURE_SMBUS_PEC       (1 << 0)
 227 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 228 #define FEATURE_BLOCK_PROC      (1 << 2)
 229 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 230 #define FEATURE_IRQ             (1 << 4)
 231 /* Not really a feature, but it's convenient to handle it as such */
 232 #define FEATURE_IDF             (1 << 15)
 233
 234 static const char *i801_feature_names[] = {
 235         "SMBus PEC",
 236         "Block buffer",
 237         "Block process call",
 238         "I2C block read",
 239         "Interrupt",
 240 };
 241
 242 static unsigned int disable_features;
 243 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 244 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 245         "\t\t  0x01  disable SMBus PEC\n"
 246         "\t\t  0x02  disable the block buffer\n"
 247         "\t\t  0x08  disable the I2C block read functionality\n"
 248         "\t\t  0x10  don't use interrupts ");
 249
 250 /* Make sure the SMBus host is ready to start transmitting.
 251    Return 0 if it is, -EBUSY if it is not. */
 252 static int i801_check_pre(struct i801_priv *priv)
 253 {
 254         int status;
 255
 256         status = inb_p(SMBHSTSTS(priv));
 257         if (status & SMBHSTSTS_HOST_BUSY) {
 258                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 259                 return -EBUSY;
 260         }
 261
 262         status &= STATUS_FLAGS;
 263         if (status) {
 264                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 265                         status);
 266                 outb_p(status, SMBHSTSTS(priv));
 267                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 268                 if (status) {
 269                         dev_err(&priv->pci_dev->dev,
 270                                 "Failed clearing status flags (%02x)\n",
 271                                 status);
 272                         return -EBUSY;
 273                 }
 274         }
 275
 276         return 0;
 277 }
 278
 279 /*
 280  * Convert the status register to an error code, and clear it.
 281  * Note that status only contains the bits we want to clear, not the
 282  * actual register value.
 283  */
 284 static int i801_check_post(struct i801_priv *priv, int status)
 285 {
 286         int result = 0;
 287
 288         /*
 289          * If the SMBus is still busy, we give up
 290          * Note: This timeout condition only happens when using polling
 291          * transactions.  For interrupt operation, NAK/timeout is indicated by
 292          * DEV_ERR.
 293          */
 294         if (unlikely(status < 0)) {
 295                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 296                 /* try to stop the current command */
 297                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 298                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 299                        SMBHSTCNT(priv));
 300                 usleep_range(1000, 2000);
 301                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 302                        SMBHSTCNT(priv));
 303
 304                 /* Check if it worked */
 305                 status = inb_p(SMBHSTSTS(priv));
 306                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 307                     !(status & SMBHSTSTS_FAILED))
 308                         dev_err(&priv->pci_dev->dev,
 309                                 "Failed terminating the transaction\n");
 310                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 311                 return -ETIMEDOUT;
 312         }
 313
 314         if (status & SMBHSTSTS_FAILED) {
 315                 result = -EIO;
 316                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 317         }
 318         if (status & SMBHSTSTS_DEV_ERR) {
 319                 result = -ENXIO;
 320                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 321         }
 322         if (status & SMBHSTSTS_BUS_ERR) {
 323                 result = -EAGAIN;
 324                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 325         }
 326
 327         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 328         outb_p(status, SMBHSTSTS(priv));
 329
 330         return result;
 331 }
 332
 333 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 334 static int i801_wait_intr(struct i801_priv *priv)
 335 {
 336         int timeout = 0;
 337         int status;
 338
 339         /* We will always wait for a fraction of a second! */
 340         do {
 341                 usleep_range(250, 500);
 342                 status = inb_p(SMBHSTSTS(priv));
 343         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 344                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 345                  (timeout++ < MAX_RETRIES));
 346
 347         if (timeout > MAX_RETRIES) {
 348                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 349                 return -ETIMEDOUT;
 350         }
 351         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 352 }
 353
 354 /* Wait for either BYTE_DONE or an error flag being set */
 355 static int i801_wait_byte_done(struct i801_priv *priv)
 356 {
 357         int timeout = 0;
 358         int status;
 359
 360         /* We will always wait for a fraction of a second! */
 361         do {
 362                 usleep_range(250, 500);
 363                 status = inb_p(SMBHSTSTS(priv));
 364         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 365                  (timeout++ < MAX_RETRIES));
 366
 367         if (timeout > MAX_RETRIES) {
 368                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 369                 return -ETIMEDOUT;
 370         }
 371         return status & STATUS_ERROR_FLAGS;
 372 }
 373
 374 static int i801_transaction(struct i801_priv *priv, int xact)
 375 {
 376         int status;
 377         int result;
 378         const struct i2c_adapter *adap = &priv->adapter;
 379
 380         result = i801_check_pre(priv);
 381         if (result < 0)
 382                 return result;
 383
 384         if (priv->features & FEATURE_IRQ) {
 385                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 386                        SMBHSTCNT(priv));
 387                 result = wait_event_timeout(priv->waitq,
 388                                             (status = priv->status),
 389                                             adap->timeout);
 390                 if (!result) {
 391                         status = -ETIMEDOUT;
 392                         dev_warn(&priv->pci_dev->dev,
 393                                  "Timeout waiting for interrupt!\n");
 394                 }
 395                 priv->status = 0;
 396                 return i801_check_post(priv, status);
 397         }
 398
 399         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 400          * SMBSCMD are passed in xact */
 401         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 402
 403         status = i801_wait_intr(priv);
 404         return i801_check_post(priv, status);
 405 }
 406
 407 static int i801_block_transaction_by_block(struct i801_priv *priv,
 408                                            union i2c_smbus_data *data,
 409                                            char read_write, int hwpec)
 410 {
 411         int i, len;
 412         int status;
 413
 414         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 415
 416         /* Use 32-byte buffer to process this transaction */
 417         if (read_write == I2C_SMBUS_WRITE) {
 418                 len = data->block[0];
 419                 outb_p(len, SMBHSTDAT0(priv));
 420                 for (i = 0; i < len; i++)
 421                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 422         }
 423
 424         status = i801_transaction(priv, I801_BLOCK_DATA |
 425                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 426         if (status)
 427                 return status;
 428
 429         if (read_write == I2C_SMBUS_READ) {
 430                 len = inb_p(SMBHSTDAT0(priv));
 431                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 432                         return -EPROTO;
 433
 434                 data->block[0] = len;
 435                 for (i = 0; i < len; i++)
 436                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 437         }
 438         return 0;
 439 }
 440
 441 static void i801_isr_byte_done(struct i801_priv *priv)
 442 {
 443         if (priv->is_read) {
 444                 /* For SMBus block reads, length is received with first byte */
 445                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 446                     (priv->count == 0)) {
 447                         priv->len = inb_p(SMBHSTDAT0(priv));
 448                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 449                                 dev_err(&priv->pci_dev->dev,
 450                                         "Illegal SMBus block read size %d\n",
 451                                         priv->len);
 452                                 /* FIXME: Recover */
 453                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 454                         } else {
 455                                 dev_dbg(&priv->pci_dev->dev,
 456                                         "SMBus block read size is %d\n",
 457                                         priv->len);
 458                         }
 459                         priv->data[-1] = priv->len;
 460                 }
 461
 462                 /* Read next byte */
 463                 if (priv->count < priv->len)
 464                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 465                 else
 466                         dev_dbg(&priv->pci_dev->dev,
 467                                 "Discarding extra byte on block read\n");
 468
 469                 /* Set LAST_BYTE for last byte of read transaction */
 470                 if (priv->count == priv->len - 1)
 471                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 472                                SMBHSTCNT(priv));
 473         } else if (priv->count < priv->len - 1) {
 474                 /* Write next byte, except for IRQ after last byte */
 475                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 476         }
 477
 478         /* Clear BYTE_DONE to continue with next byte */
 479         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 480 }
 481
 482 /*
 483  * There are two kinds of interrupts:
 484  *
 485  * 1) i801 signals transaction completion with one of these interrupts:
 486  *      INTR - Success
 487  *      DEV_ERR - Invalid command, NAK or communication timeout
 488  *      BUS_ERR - SMI# transaction collision
 489  *      FAILED - transaction was canceled due to a KILL request
 490  *    When any of these occur, update ->status and wake up the waitq.
 491  *    ->status must be cleared before kicking off the next transaction.
 492  *
 493  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 494  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 495  */
 496 static irqreturn_t i801_isr(int irq, void *dev_id)
 497 {
 498         struct i801_priv *priv = dev_id;
 499         u16 pcists;
 500         u8 status;
 501
 502         /* Confirm this is our interrupt */
 503         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 504         if (!(pcists & SMBPCISTS_INTS))
 505                 return IRQ_NONE;
 506
 507         status = inb_p(SMBHSTSTS(priv));
 508         if (status & SMBHSTSTS_BYTE_DONE)
 509                 i801_isr_byte_done(priv);
 510
 511         /*
 512          * Clear irq sources and report transaction result.
 513          * ->status must be cleared before the next transaction is started.
 514          */
 515         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 516         if (status) {
 517                 outb_p(status, SMBHSTSTS(priv));
 518                 priv->status |= status;
 519                 wake_up(&priv->waitq);
 520         }
 521
 522         return IRQ_HANDLED;
 523 }
 524
 525 /*
 526  * For "byte-by-byte" block transactions:
 527  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 528  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 529  */
 530 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 531                                                union i2c_smbus_data *data,
 532                                                char read_write, int command,
 533                                                int hwpec)
 534 {
 535         int i, len;
 536         int smbcmd;
 537         int status;
 538         int result;
 539         const struct i2c_adapter *adap = &priv->adapter;
 540
 541         result = i801_check_pre(priv);
 542         if (result < 0)
 543                 return result;
 544
 545         len = data->block[0];
 546
 547         if (read_write == I2C_SMBUS_WRITE) {
 548                 outb_p(len, SMBHSTDAT0(priv));
 549                 outb_p(data->block[1], SMBBLKDAT(priv));
 550         }
 551
 552         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 553             read_write == I2C_SMBUS_READ)
 554                 smbcmd = I801_I2C_BLOCK_DATA;
 555         else
 556                 smbcmd = I801_BLOCK_DATA;
 557
 558         if (priv->features & FEATURE_IRQ) {
 559                 priv->is_read = (read_write == I2C_SMBUS_READ);
 560                 if (len == 1 && priv->is_read)
 561                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 562                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 563                 priv->len = len;
 564                 priv->count = 0;
 565                 priv->data = &data->block[1];
 566
 567                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 568                 result = wait_event_timeout(priv->waitq,
 569                                             (status = priv->status),
 570                                             adap->timeout);
 571                 if (!result) {
 572                         status = -ETIMEDOUT;
 573                         dev_warn(&priv->pci_dev->dev,
 574                                  "Timeout waiting for interrupt!\n");
 575                 }
 576                 priv->status = 0;
 577                 return i801_check_post(priv, status);
 578         }
 579
 580         for (i = 1; i <= len; i++) {
 581                 if (i == len && read_write == I2C_SMBUS_READ)
 582                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 583                 outb_p(smbcmd, SMBHSTCNT(priv));
 584
 585                 if (i == 1)
 586                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 587                                SMBHSTCNT(priv));
 588
 589                 status = i801_wait_byte_done(priv);
 590                 if (status)
 591                         goto exit;
 592
 593                 if (i == 1 && read_write == I2C_SMBUS_READ
 594                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 595                         len = inb_p(SMBHSTDAT0(priv));
 596                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 597                                 dev_err(&priv->pci_dev->dev,
 598                                         "Illegal SMBus block read size %d\n",
 599                                         len);
 600                                 /* Recover */
 601                                 while (inb_p(SMBHSTSTS(priv)) &
 602                                        SMBHSTSTS_HOST_BUSY)
 603                                         outb_p(SMBHSTSTS_BYTE_DONE,
 604                                                SMBHSTSTS(priv));
 605                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 606                                 return -EPROTO;
 607                         }
 608                         data->block[0] = len;
 609                 }
 610
 611                 /* Retrieve/store value in SMBBLKDAT */
 612                 if (read_write == I2C_SMBUS_READ)
 613                         data->block[i] = inb_p(SMBBLKDAT(priv));
 614                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 615                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 616
 617                 /* signals SMBBLKDAT ready */
 618                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 619         }
 620
 621         status = i801_wait_intr(priv);
 622 exit:
 623         return i801_check_post(priv, status);
 624 }
 625
 626 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 627 {
 628         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 629         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 630                 return -EIO;
 631         return 0;
 632 }
 633
 634 /* Block transaction function */
 635 static int i801_block_transaction(struct i801_priv *priv,
 636                                   union i2c_smbus_data *data, char read_write,
 637                                   int command, int hwpec)
 638 {
 639         int result = 0;
 640         unsigned char hostc;
 641
 642         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 643                 if (read_write == I2C_SMBUS_WRITE) {
 644                         /* set I2C_EN bit in configuration register */
 645                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 646                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 647                                               hostc | SMBHSTCFG_I2C_EN);
 648                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 649                         dev_err(&priv->pci_dev->dev,
 650                                 "I2C block read is unsupported!\n");
 651                         return -EOPNOTSUPP;
 652                 }
 653         }
 654
 655         if (read_write == I2C_SMBUS_WRITE
 656          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 657                 if (data->block[0] < 1)
 658                         data->block[0] = 1;
 659                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 660                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 661         } else {
 662                 data->block[0] = 32;    /* max for SMBus block reads */
 663         }
 664
 665         /* Experience has shown that the block buffer can only be used for
 666            SMBus (not I2C) block transactions, even though the datasheet
 667            doesn't mention this limitation. */
 668         if ((priv->features & FEATURE_BLOCK_BUFFER)
 669          && command != I2C_SMBUS_I2C_BLOCK_DATA
 670          && i801_set_block_buffer_mode(priv) == 0)
 671                 result = i801_block_transaction_by_block(priv, data,
 672                                                          read_write, hwpec);
 673         else
 674                 result = i801_block_transaction_byte_by_byte(priv, data,
 675                                                              read_write,
 676                                                              command, hwpec);
 677
 678         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 679          && read_write == I2C_SMBUS_WRITE) {
 680                 /* restore saved configuration register value */
 681                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 682         }
 683         return result;
 684 }
 685
 686 /* Return negative errno on error. */
 687 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 688                        unsigned short flags, char read_write, u8 command,
 689                        int size, union i2c_smbus_data *data)
 690 {
 691         int hwpec;
 692         int block = 0;
 693         int ret, xact = 0;
 694         struct i801_priv *priv = i2c_get_adapdata(adap);
 695
 696         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 697                 && size != I2C_SMBUS_QUICK
 698                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 699
 700         switch (size) {
 701         case I2C_SMBUS_QUICK:
 702                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 703                        SMBHSTADD(priv));
 704                 xact = I801_QUICK;
 705                 break;
 706         case I2C_SMBUS_BYTE:
 707                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 708                        SMBHSTADD(priv));
 709                 if (read_write == I2C_SMBUS_WRITE)
 710                         outb_p(command, SMBHSTCMD(priv));
 711                 xact = I801_BYTE;
 712                 break;
 713         case I2C_SMBUS_BYTE_DATA:
 714                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 715                        SMBHSTADD(priv));
 716                 outb_p(command, SMBHSTCMD(priv));
 717                 if (read_write == I2C_SMBUS_WRITE)
 718                         outb_p(data->byte, SMBHSTDAT0(priv));
 719                 xact = I801_BYTE_DATA;
 720                 break;
 721         case I2C_SMBUS_WORD_DATA:
 722                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 723                        SMBHSTADD(priv));
 724                 outb_p(command, SMBHSTCMD(priv));
 725                 if (read_write == I2C_SMBUS_WRITE) {
 726                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 727                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 728                 }
 729                 xact = I801_WORD_DATA;
 730                 break;
 731         case I2C_SMBUS_BLOCK_DATA:
 732                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 733                        SMBHSTADD(priv));
 734                 outb_p(command, SMBHSTCMD(priv));
 735                 block = 1;
 736                 break;
 737         case I2C_SMBUS_I2C_BLOCK_DATA:
 738                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 739                  * bit should be cleared here, even when reading */
 740                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 741                 if (read_write == I2C_SMBUS_READ) {
 742                         /* NB: page 240 of ICH5 datasheet also shows
 743                          * that DATA1 is the cmd field when reading */
 744                         outb_p(command, SMBHSTDAT1(priv));
 745                 } else
 746                         outb_p(command, SMBHSTCMD(priv));
 747                 block = 1;
 748                 break;
 749         default:
 750                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 751                         size);
 752                 return -EOPNOTSUPP;
 753         }
 754
 755         if (hwpec)      /* enable/disable hardware PEC */
 756                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 757         else
 758                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 759                        SMBAUXCTL(priv));
 760
 761         if (block)
 762                 ret = i801_block_transaction(priv, data, read_write, size,
 763                                              hwpec);
 764         else
 765                 ret = i801_transaction(priv, xact);
 766
 767         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 768            time, so we forcibly disable it after every transaction. Turn off
 769            E32B for the same reason. */
 770         if (hwpec || block)
 771                 outb_p(inb_p(SMBAUXCTL(priv)) &
 772                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 773
 774         if (block)
 775                 return ret;
 776         if (ret)
 777                 return ret;
 778         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 779                 return 0;
 780
 781         switch (xact & 0x7f) {
 782         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 783         case I801_BYTE_DATA:
 784                 data->byte = inb_p(SMBHSTDAT0(priv));
 785                 break;
 786         case I801_WORD_DATA:
 787                 data->word = inb_p(SMBHSTDAT0(priv)) +
 788                              (inb_p(SMBHSTDAT1(priv)) << 8);
 789                 break;
 790         }
 791         return 0;
 792 }
 793
 794
 795 static u32 i801_func(struct i2c_adapter *adapter)
 796 {
 797         struct i801_priv *priv = i2c_get_adapdata(adapter);
 798
 799         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 800                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 801                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 802                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 803                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 804                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 805 }
 806
 807 static const struct i2c_algorithm smbus_algorithm = {
 808         .smbus_xfer     = i801_access,
 809         .functionality  = i801_func,
 810 };
 811
 812 static const struct pci_device_id i801_ids[] = {
 813         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 814         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 815         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 829         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 830         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 831         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 832         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 833         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 834         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 835         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 836         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 837         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 838         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 839         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 840         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 841         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 842         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 843         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 844         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 845         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 846         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 847         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 848         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 849         { 0, }
 850 };
 851
 852 MODULE_DEVICE_TABLE(pci, i801_ids);
 853
 854 #if defined CONFIG_X86 && defined CONFIG_DMI
 855 static unsigned char apanel_addr;
 856
 857 /* Scan the system ROM for the signature "FJKEYINF" */
 858 static __init const void __iomem *bios_signature(const void __iomem *bios)
 859 {
 860         ssize_t offset;
 861         const unsigned char signature[] = "FJKEYINF";
 862
 863         for (offset = 0; offset < 0x10000; offset += 0x10) {
 864                 if (check_signature(bios + offset, signature,
 865                                     sizeof(signature)-1))
 866                         return bios + offset;
 867         }
 868         return NULL;
 869 }
 870
 871 static void __init input_apanel_init(void)
 872 {
 873         void __iomem *bios;
 874         const void __iomem *p;
 875
 876         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 877         p = bios_signature(bios);
 878         if (p) {
 879                 /* just use the first address */
 880                 apanel_addr = readb(p + 8 + 3) >> 1;
 881         }
 882         iounmap(bios);
 883 }
 884
 885 struct dmi_onboard_device_info {
 886         const char *name;
 887         u8 type;
 888         unsigned short i2c_addr;
 889         const char *i2c_type;
 890 };
 891
 892 static const struct dmi_onboard_device_info dmi_devices[] = {
 893         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 894         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 895         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 896 };
 897
 898 static void dmi_check_onboard_device(u8 type, const char *name,
 899                                      struct i2c_adapter *adap)
 900 {
 901         int i;
 902         struct i2c_board_info info;
 903
 904         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 905                 /* & ~0x80, ignore enabled/disabled bit */
 906                 if ((type & ~0x80) != dmi_devices[i].type)
 907                         continue;
 908                 if (strcasecmp(name, dmi_devices[i].name))
 909                         continue;
 910
 911                 memset(&info, 0, sizeof(struct i2c_board_info));
 912                 info.addr = dmi_devices[i].i2c_addr;
 913                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 914                 i2c_new_device(adap, &info);
 915                 break;
 916         }
 917 }
 918
 919 /* We use our own function to check for onboard devices instead of
 920    dmi_find_device() as some buggy BIOS's have the devices we are interested
 921    in marked as disabled */
 922 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 923 {
 924         int i, count;
 925
 926         if (dm->type != 10)
 927                 return;
 928
 929         count = (dm->length - sizeof(struct dmi_header)) / 2;
 930         for (i = 0; i < count; i++) {
 931                 const u8 *d = (char *)(dm + 1) + (i * 2);
 932                 const char *name = ((char *) dm) + dm->length;
 933                 u8 type = d[0];
 934                 u8 s = d[1];
 935
 936                 if (!s)
 937                         continue;
 938                 s--;
 939                 while (s > 0 && name[0]) {
 940                         name += strlen(name) + 1;
 941                         s--;
 942                 }
 943                 if (name[0] == 0) /* Bogus string reference */
 944                         continue;
 945
 946                 dmi_check_onboard_device(type, name, adap);
 947         }
 948 }
 949
 950 /* Register optional slaves */
 951 static void i801_probe_optional_slaves(struct i801_priv *priv)
 952 {
 953         /* Only register slaves on main SMBus channel */
 954         if (priv->features & FEATURE_IDF)
 955                 return;
 956
 957         if (apanel_addr) {
 958                 struct i2c_board_info info;
 959
 960                 memset(&info, 0, sizeof(struct i2c_board_info));
 961                 info.addr = apanel_addr;
 962                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 963                 i2c_new_device(&priv->adapter, &info);
 964         }
 965
 966         if (dmi_name_in_vendors("FUJITSU"))
 967                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 968 }
 969 #else
 970 static void __init input_apanel_init(void) {}
 971 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 972 #endif  /* CONFIG_X86 && CONFIG_DMI */
 973
 974 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 975                 defined CONFIG_DMI
 976 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 977         .gpio_chip = "gpio_ich",
 978         .values = { 0x02, 0x03 },
 979         .n_values = 2,
 980         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 981         .gpios = { 52, 53 },
 982         .n_gpios = 2,
 983 };
 984
 985 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 986         .gpio_chip = "gpio_ich",
 987         .values = { 0x02, 0x03, 0x01 },
 988         .n_values = 3,
 989         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 990         .gpios = { 52, 53 },
 991         .n_gpios = 2,
 992 };
 993
 994 static const struct dmi_system_id mux_dmi_table[] = {
 995         {
 996                 .matches = {
 997                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 998                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 999                 },
1000                 .driver_data = &i801_mux_config_asus_z8_d12,
1001         },
1002         {
1003                 .matches = {
1004                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1005                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1006                 },
1007                 .driver_data = &i801_mux_config_asus_z8_d12,
1008         },
1009         {
1010                 .matches = {
1011                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1012                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1013                 },
1014                 .driver_data = &i801_mux_config_asus_z8_d12,
1015         },
1016         {
1017                 .matches = {
1018                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1019                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1020                 },
1021                 .driver_data = &i801_mux_config_asus_z8_d12,
1022         },
1023         {
1024                 .matches = {
1025                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1026                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1027                 },
1028                 .driver_data = &i801_mux_config_asus_z8_d12,
1029         },
1030         {
1031                 .matches = {
1032                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1033                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1034                 },
1035                 .driver_data = &i801_mux_config_asus_z8_d12,
1036         },
1037         {
1038                 .matches = {
1039                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1040                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1041                 },
1042                 .driver_data = &i801_mux_config_asus_z8_d18,
1043         },
1044         {
1045                 .matches = {
1046                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1047                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1048                 },
1049                 .driver_data = &i801_mux_config_asus_z8_d18,
1050         },
1051         {
1052                 .matches = {
1053                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1054                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1055                 },
1056                 .driver_data = &i801_mux_config_asus_z8_d12,
1057         },
1058         { }
1059 };
1060
1061 /* Setup multiplexing if needed */
1062 static int i801_add_mux(struct i801_priv *priv)
1063 {
1064         struct device *dev = &priv->adapter.dev;
1065         const struct i801_mux_config *mux_config;
1066         struct i2c_mux_gpio_platform_data gpio_data;
1067         int err;
1068
1069         if (!priv->mux_drvdata)
1070                 return 0;
1071         mux_config = priv->mux_drvdata;
1072
1073         /* Prepare the platform data */
1074         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1075         gpio_data.parent = priv->adapter.nr;
1076         gpio_data.values = mux_config->values;
1077         gpio_data.n_values = mux_config->n_values;
1078         gpio_data.classes = mux_config->classes;
1079         gpio_data.gpio_chip = mux_config->gpio_chip;
1080         gpio_data.gpios = mux_config->gpios;
1081         gpio_data.n_gpios = mux_config->n_gpios;
1082         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1083
1084         /* Register the mux device */
1085         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1086                                 PLATFORM_DEVID_AUTO, &gpio_data,
1087                                 sizeof(struct i2c_mux_gpio_platform_data));
1088         if (IS_ERR(priv->mux_pdev)) {
1089                 err = PTR_ERR(priv->mux_pdev);
1090                 priv->mux_pdev = NULL;
1091                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1092                 return err;
1093         }
1094
1095         return 0;
1096 }
1097
1098 static void i801_del_mux(struct i801_priv *priv)
1099 {
1100         if (priv->mux_pdev)
1101                 platform_device_unregister(priv->mux_pdev);
1102 }
1103
1104 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1105 {
1106         const struct dmi_system_id *id;
1107         const struct i801_mux_config *mux_config;
1108         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1109         int i;
1110
1111         id = dmi_first_match(mux_dmi_table);
1112         if (id) {
1113                 /* Remove branch classes from trunk */
1114                 mux_config = id->driver_data;
1115                 for (i = 0; i < mux_config->n_values; i++)
1116                         class &= ~mux_config->classes[i];
1117
1118                 /* Remember for later */
1119                 priv->mux_drvdata = mux_config;
1120         }
1121
1122         return class;
1123 }
1124 #else
1125 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1126 static inline void i801_del_mux(struct i801_priv *priv) { }
1127
1128 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1129 {
1130         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1131 }
1132 #endif
1133
1134 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1135 {
1136         unsigned char temp;
1137         int err, i;
1138         struct i801_priv *priv;
1139
1140         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1141         if (!priv)
1142                 return -ENOMEM;
1143
1144         i2c_set_adapdata(&priv->adapter, priv);
1145         priv->adapter.owner = THIS_MODULE;
1146         priv->adapter.class = i801_get_adapter_class(priv);
1147         priv->adapter.algo = &smbus_algorithm;
1148
1149         priv->pci_dev = dev;
1150         switch (dev->device) {
1151         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1152         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1153         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1154         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1155         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1156         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1157                 priv->features |= FEATURE_IDF;
1158                 /* fall through */
1159         default:
1160                 priv->features |= FEATURE_I2C_BLOCK_READ;
1161                 priv->features |= FEATURE_IRQ;
1162                 /* fall through */
1163         case PCI_DEVICE_ID_INTEL_82801DB_3:
1164                 priv->features |= FEATURE_SMBUS_PEC;
1165                 priv->features |= FEATURE_BLOCK_BUFFER;
1166                 /* fall through */
1167         case PCI_DEVICE_ID_INTEL_82801CA_3:
1168         case PCI_DEVICE_ID_INTEL_82801BA_2:
1169         case PCI_DEVICE_ID_INTEL_82801AB_3:
1170         case PCI_DEVICE_ID_INTEL_82801AA_3:
1171                 break;
1172         }
1173
1174         /* Disable features on user request */
1175         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1176                 if (priv->features & disable_features & (1 << i))
1177                         dev_notice(&dev->dev, "%s disabled by user\n",
1178                                    i801_feature_names[i]);
1179         }
1180         priv->features &= ~disable_features;
1181
1182         err = pci_enable_device(dev);
1183         if (err) {
1184                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1185                         err);
1186                 goto exit;
1187         }
1188
1189         /* Determine the address of the SMBus area */
1190         priv->smba = pci_resource_start(dev, SMBBAR);
1191         if (!priv->smba) {
1192                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1193                         "upgrade BIOS\n");
1194                 err = -ENODEV;
1195                 goto exit;
1196         }
1197
1198         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1199         if (err) {
1200                 err = -ENODEV;
1201                 goto exit;
1202         }
1203
1204         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1205         if (err) {
1206                 dev_err(&dev->dev, "Failed to request SMBus region "
1207                         "0x%lx-0x%Lx\n", priv->smba,
1208                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1209                 goto exit;
1210         }
1211
1212         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1213         priv->original_hstcfg = temp;
1214         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1215         if (!(temp & SMBHSTCFG_HST_EN)) {
1216                 dev_info(&dev->dev, "Enabling SMBus device\n");
1217                 temp |= SMBHSTCFG_HST_EN;
1218         }
1219         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1220
1221         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1222                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1223                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1224                 priv->features &= ~FEATURE_IRQ;
1225         }
1226
1227         /* Clear special mode bits */
1228         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1229                 outb_p(inb_p(SMBAUXCTL(priv)) &
1230                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1231
1232         /* Default timeout in interrupt mode: 200 ms */
1233         priv->adapter.timeout = HZ / 5;
1234
1235         if (priv->features & FEATURE_IRQ) {
1236                 u16 pcictl, pcists;
1237
1238                 /* Complain if an interrupt is already pending */
1239                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1240                 if (pcists & SMBPCISTS_INTS)
1241                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1242
1243                 /* Check if interrupts have been disabled */
1244                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1245                 if (pcictl & SMBPCICTL_INTDIS) {
1246                         dev_info(&dev->dev, "Interrupts are disabled\n");
1247                         priv->features &= ~FEATURE_IRQ;
1248                 }
1249         }
1250
1251         if (priv->features & FEATURE_IRQ) {
1252                 init_waitqueue_head(&priv->waitq);
1253
1254                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1255                                   i801_driver.name, priv);
1256                 if (err) {
1257                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1258                                 dev->irq, err);
1259                         priv->features &= ~FEATURE_IRQ;
1260                 }
1261         }
1262         dev_info(&dev->dev, "SMBus using %s\n",
1263                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1264
1265         /* set up the sysfs linkage to our parent device */
1266         priv->adapter.dev.parent = &dev->dev;
1267
1268         /* Retry up to 3 times on lost arbitration */
1269         priv->adapter.retries = 3;
1270
1271         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1272                 "SMBus I801 adapter at %04lx", priv->smba);
1273         err = i2c_add_adapter(&priv->adapter);
1274         if (err) {
1275                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1276                 goto exit_free_irq;
1277         }
1278
1279         i801_probe_optional_slaves(priv);
1280         /* We ignore errors - multiplexing is optional */
1281         i801_add_mux(priv);
1282
1283         pci_set_drvdata(dev, priv);
1284
1285         return 0;
1286
1287 exit_free_irq:
1288         if (priv->features & FEATURE_IRQ)
1289                 free_irq(dev->irq, priv);
1290         pci_release_region(dev, SMBBAR);
1291 exit:
1292         kfree(priv);
1293         return err;
1294 }
1295
1296 static void i801_remove(struct pci_dev *dev)
1297 {
1298         struct i801_priv *priv = pci_get_drvdata(dev);
1299
1300         i801_del_mux(priv);
1301         i2c_del_adapter(&priv->adapter);
1302         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1303
1304         if (priv->features & FEATURE_IRQ)
1305                 free_irq(dev->irq, priv);
1306         pci_release_region(dev, SMBBAR);
1307
1308         kfree(priv);
1309         /*
1310          * do not call pci_disable_device(dev) since it can cause hard hangs on
1311          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1312          */
1313 }
1314
1315 #ifdef CONFIG_PM
1316 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1317 {
1318         struct i801_priv *priv = pci_get_drvdata(dev);
1319
1320         pci_save_state(dev);
1321         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1322         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1323         return 0;
1324 }
1325
1326 static int i801_resume(struct pci_dev *dev)
1327 {
1328         pci_set_power_state(dev, PCI_D0);
1329         pci_restore_state(dev);
1330         return pci_enable_device(dev);
1331 }
1332 #else
1333 #define i801_suspend NULL
1334 #define i801_resume NULL
1335 #endif
1336
1337 static struct pci_driver i801_driver = {
1338         .name           = "i801_smbus",
1339         .id_table       = i801_ids,
1340         .probe          = i801_probe,
1341         .remove         = i801_remove,
1342         .suspend        = i801_suspend,
1343         .resume         = i801_resume,
1344 };
1345
1346 static int __init i2c_i801_init(void)
1347 {
1348         if (dmi_name_in_vendors("FUJITSU"))
1349                 input_apanel_init();
1350         return pci_register_driver(&i801_driver);
1351 }
1352
1353 static void __exit i2c_i801_exit(void)
1354 {
1355         pci_unregister_driver(&i801_driver);
1356 }
1357
1358 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1359 MODULE_DESCRIPTION("I801 SMBus driver");
1360 MODULE_LICENSE("GPL");
1361
1362 module_init(i2c_i801_init);
1363 module_exit(i2c_i801_exit);