drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  *
  63  * Features supported by this driver:
  64  * Software PEC                         no
  65  * Hardware PEC                         yes
  66  * Block buffer                         yes
  67  * Block process call transaction       no
  68  * I2C block read transaction           yes (doesn't use the block buffer)
  69  * Slave mode                           no
  70  * Interrupt processing                 yes
  71  *
  72  * See the file Documentation/i2c/busses/i2c-i801 for details.
  73  */
  74
  75 #include <linux/interrupt.h>
  76 #include <linux/module.h>
  77 #include <linux/pci.h>
  78 #include <linux/kernel.h>
  79 #include <linux/stddef.h>
  80 #include <linux/delay.h>
  81 #include <linux/ioport.h>
  82 #include <linux/init.h>
  83 #include <linux/i2c.h>
  84 #include <linux/acpi.h>
  85 #include <linux/io.h>
  86 #include <linux/dmi.h>
  87 #include <linux/slab.h>
  88 #include <linux/wait.h>
  89 #include <linux/err.h>
  90
  91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  92                 defined CONFIG_DMI
  93 #include <linux/gpio.h>
  94 #include <linux/i2c-mux-gpio.h>
  95 #include <linux/platform_device.h>
  96 #endif
  97
  98 /* I801 SMBus address offsets */
  99 #define SMBHSTSTS(p)    (0 + (p)->smba)
 100 #define SMBHSTCNT(p)    (2 + (p)->smba)
 101 #define SMBHSTCMD(p)    (3 + (p)->smba)
 102 #define SMBHSTADD(p)    (4 + (p)->smba)
 103 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 104 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 105 #define SMBBLKDAT(p)    (7 + (p)->smba)
 106 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 107 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 108 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 109
 110 /* PCI Address Constants */
 111 #define SMBBAR          4
 112 #define SMBPCISTS       0x006
 113 #define SMBHSTCFG       0x040
 114
 115 /* Host status bits for SMBPCISTS */
 116 #define SMBPCISTS_INTS          0x08
 117
 118 /* Host configuration bits for SMBHSTCFG */
 119 #define SMBHSTCFG_HST_EN        1
 120 #define SMBHSTCFG_SMB_SMI_EN    2
 121 #define SMBHSTCFG_I2C_EN        4
 122
 123 /* Auxiliary control register bits, ICH4+ only */
 124 #define SMBAUXCTL_CRC           1
 125 #define SMBAUXCTL_E32B          2
 126
 127 /* Other settings */
 128 #define MAX_RETRIES             400
 129
 130 /* I801 command constants */
 131 #define I801_QUICK              0x00
 132 #define I801_BYTE               0x04
 133 #define I801_BYTE_DATA          0x08
 134 #define I801_WORD_DATA          0x0C
 135 #define I801_PROC_CALL          0x10    /* unimplemented */
 136 #define I801_BLOCK_DATA         0x14
 137 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 138
 139 /* I801 Host Control register bits */
 140 #define SMBHSTCNT_INTREN        0x01
 141 #define SMBHSTCNT_KILL          0x02
 142 #define SMBHSTCNT_LAST_BYTE     0x20
 143 #define SMBHSTCNT_START         0x40
 144 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 145
 146 /* I801 Hosts Status register bits */
 147 #define SMBHSTSTS_BYTE_DONE     0x80
 148 #define SMBHSTSTS_INUSE_STS     0x40
 149 #define SMBHSTSTS_SMBALERT_STS  0x20
 150 #define SMBHSTSTS_FAILED        0x10
 151 #define SMBHSTSTS_BUS_ERR       0x08
 152 #define SMBHSTSTS_DEV_ERR       0x04
 153 #define SMBHSTSTS_INTR          0x02
 154 #define SMBHSTSTS_HOST_BUSY     0x01
 155
 156 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 157                                  SMBHSTSTS_DEV_ERR)
 158
 159 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 160                                  STATUS_ERROR_FLAGS)
 161
 162 /* Older devices have their ID defined in <linux/pci_ids.h> */
 163 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 164 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 165 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 166 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 167 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 171 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 172 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 173 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 174 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 175 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 176 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 177 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 182 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 183 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 184 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 185
 186 struct i801_mux_config {
 187         char *gpio_chip;
 188         unsigned values[3];
 189         int n_values;
 190         unsigned classes[3];
 191         unsigned gpios[2];              /* Relative to gpio_chip->base */
 192         int n_gpios;
 193 };
 194
 195 struct i801_priv {
 196         struct i2c_adapter adapter;
 197         unsigned long smba;
 198         unsigned char original_hstcfg;
 199         struct pci_dev *pci_dev;
 200         unsigned int features;
 201
 202         /* isr processing */
 203         wait_queue_head_t waitq;
 204         u8 status;
 205
 206         /* Command state used by isr for byte-by-byte block transactions */
 207         u8 cmd;
 208         bool is_read;
 209         int count;
 210         int len;
 211         u8 *data;
 212
 213 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 214                 defined CONFIG_DMI
 215         const struct i801_mux_config *mux_drvdata;
 216         struct platform_device *mux_pdev;
 217 #endif
 218 };
 219
 220 static struct pci_driver i801_driver;
 221
 222 #define FEATURE_SMBUS_PEC       (1 << 0)
 223 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 224 #define FEATURE_BLOCK_PROC      (1 << 2)
 225 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 226 #define FEATURE_IRQ             (1 << 4)
 227 /* Not really a feature, but it's convenient to handle it as such */
 228 #define FEATURE_IDF             (1 << 15)
 229
 230 static const char *i801_feature_names[] = {
 231         "SMBus PEC",
 232         "Block buffer",
 233         "Block process call",
 234         "I2C block read",
 235         "Interrupt",
 236 };
 237
 238 static unsigned int disable_features;
 239 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 240 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 241         "\t\t  0x01  disable SMBus PEC\n"
 242         "\t\t  0x02  disable the block buffer\n"
 243         "\t\t  0x08  disable the I2C block read functionality\n"
 244         "\t\t  0x10  don't use interrupts ");
 245
 246 /* Make sure the SMBus host is ready to start transmitting.
 247    Return 0 if it is, -EBUSY if it is not. */
 248 static int i801_check_pre(struct i801_priv *priv)
 249 {
 250         int status;
 251
 252         status = inb_p(SMBHSTSTS(priv));
 253         if (status & SMBHSTSTS_HOST_BUSY) {
 254                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 255                 return -EBUSY;
 256         }
 257
 258         status &= STATUS_FLAGS;
 259         if (status) {
 260                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 261                         status);
 262                 outb_p(status, SMBHSTSTS(priv));
 263                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 264                 if (status) {
 265                         dev_err(&priv->pci_dev->dev,
 266                                 "Failed clearing status flags (%02x)\n",
 267                                 status);
 268                         return -EBUSY;
 269                 }
 270         }
 271
 272         return 0;
 273 }
 274
 275 /*
 276  * Convert the status register to an error code, and clear it.
 277  * Note that status only contains the bits we want to clear, not the
 278  * actual register value.
 279  */
 280 static int i801_check_post(struct i801_priv *priv, int status)
 281 {
 282         int result = 0;
 283
 284         /*
 285          * If the SMBus is still busy, we give up
 286          * Note: This timeout condition only happens when using polling
 287          * transactions.  For interrupt operation, NAK/timeout is indicated by
 288          * DEV_ERR.
 289          */
 290         if (unlikely(status < 0)) {
 291                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 292                 /* try to stop the current command */
 293                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 294                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 295                        SMBHSTCNT(priv));
 296                 usleep_range(1000, 2000);
 297                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 298                        SMBHSTCNT(priv));
 299
 300                 /* Check if it worked */
 301                 status = inb_p(SMBHSTSTS(priv));
 302                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 303                     !(status & SMBHSTSTS_FAILED))
 304                         dev_err(&priv->pci_dev->dev,
 305                                 "Failed terminating the transaction\n");
 306                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 307                 return -ETIMEDOUT;
 308         }
 309
 310         if (status & SMBHSTSTS_FAILED) {
 311                 result = -EIO;
 312                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 313         }
 314         if (status & SMBHSTSTS_DEV_ERR) {
 315                 result = -ENXIO;
 316                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 317         }
 318         if (status & SMBHSTSTS_BUS_ERR) {
 319                 result = -EAGAIN;
 320                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 321         }
 322
 323         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 324         outb_p(status, SMBHSTSTS(priv));
 325
 326         return result;
 327 }
 328
 329 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 330 static int i801_wait_intr(struct i801_priv *priv)
 331 {
 332         int timeout = 0;
 333         int status;
 334
 335         /* We will always wait for a fraction of a second! */
 336         do {
 337                 usleep_range(250, 500);
 338                 status = inb_p(SMBHSTSTS(priv));
 339         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 340                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 341                  (timeout++ < MAX_RETRIES));
 342
 343         if (timeout > MAX_RETRIES) {
 344                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 345                 return -ETIMEDOUT;
 346         }
 347         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 348 }
 349
 350 /* Wait for either BYTE_DONE or an error flag being set */
 351 static int i801_wait_byte_done(struct i801_priv *priv)
 352 {
 353         int timeout = 0;
 354         int status;
 355
 356         /* We will always wait for a fraction of a second! */
 357         do {
 358                 usleep_range(250, 500);
 359                 status = inb_p(SMBHSTSTS(priv));
 360         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 361                  (timeout++ < MAX_RETRIES));
 362
 363         if (timeout > MAX_RETRIES) {
 364                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 365                 return -ETIMEDOUT;
 366         }
 367         return status & STATUS_ERROR_FLAGS;
 368 }
 369
 370 static int i801_transaction(struct i801_priv *priv, int xact)
 371 {
 372         int status;
 373         int result;
 374         const struct i2c_adapter *adap = &priv->adapter;
 375
 376         result = i801_check_pre(priv);
 377         if (result < 0)
 378                 return result;
 379
 380         if (priv->features & FEATURE_IRQ) {
 381                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 382                        SMBHSTCNT(priv));
 383                 result = wait_event_timeout(priv->waitq,
 384                                             (status = priv->status),
 385                                             adap->timeout);
 386                 if (!result) {
 387                         status = -ETIMEDOUT;
 388                         dev_warn(&priv->pci_dev->dev,
 389                                  "Timeout waiting for interrupt!\n");
 390                 }
 391                 priv->status = 0;
 392                 return i801_check_post(priv, status);
 393         }
 394
 395         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 396          * SMBSCMD are passed in xact */
 397         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 398
 399         status = i801_wait_intr(priv);
 400         return i801_check_post(priv, status);
 401 }
 402
 403 static int i801_block_transaction_by_block(struct i801_priv *priv,
 404                                            union i2c_smbus_data *data,
 405                                            char read_write, int hwpec)
 406 {
 407         int i, len;
 408         int status;
 409
 410         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 411
 412         /* Use 32-byte buffer to process this transaction */
 413         if (read_write == I2C_SMBUS_WRITE) {
 414                 len = data->block[0];
 415                 outb_p(len, SMBHSTDAT0(priv));
 416                 for (i = 0; i < len; i++)
 417                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 418         }
 419
 420         status = i801_transaction(priv, I801_BLOCK_DATA |
 421                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 422         if (status)
 423                 return status;
 424
 425         if (read_write == I2C_SMBUS_READ) {
 426                 len = inb_p(SMBHSTDAT0(priv));
 427                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 428                         return -EPROTO;
 429
 430                 data->block[0] = len;
 431                 for (i = 0; i < len; i++)
 432                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 433         }
 434         return 0;
 435 }
 436
 437 static void i801_isr_byte_done(struct i801_priv *priv)
 438 {
 439         if (priv->is_read) {
 440                 /* For SMBus block reads, length is received with first byte */
 441                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 442                     (priv->count == 0)) {
 443                         priv->len = inb_p(SMBHSTDAT0(priv));
 444                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 445                                 dev_err(&priv->pci_dev->dev,
 446                                         "Illegal SMBus block read size %d\n",
 447                                         priv->len);
 448                                 /* FIXME: Recover */
 449                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 450                         } else {
 451                                 dev_dbg(&priv->pci_dev->dev,
 452                                         "SMBus block read size is %d\n",
 453                                         priv->len);
 454                         }
 455                         priv->data[-1] = priv->len;
 456                 }
 457
 458                 /* Read next byte */
 459                 if (priv->count < priv->len)
 460                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 461                 else
 462                         dev_dbg(&priv->pci_dev->dev,
 463                                 "Discarding extra byte on block read\n");
 464
 465                 /* Set LAST_BYTE for last byte of read transaction */
 466                 if (priv->count == priv->len - 1)
 467                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 468                                SMBHSTCNT(priv));
 469         } else if (priv->count < priv->len - 1) {
 470                 /* Write next byte, except for IRQ after last byte */
 471                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 472         }
 473
 474         /* Clear BYTE_DONE to continue with next byte */
 475         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 476 }
 477
 478 /*
 479  * There are two kinds of interrupts:
 480  *
 481  * 1) i801 signals transaction completion with one of these interrupts:
 482  *      INTR - Success
 483  *      DEV_ERR - Invalid command, NAK or communication timeout
 484  *      BUS_ERR - SMI# transaction collision
 485  *      FAILED - transaction was canceled due to a KILL request
 486  *    When any of these occur, update ->status and wake up the waitq.
 487  *    ->status must be cleared before kicking off the next transaction.
 488  *
 489  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 490  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 491  */
 492 static irqreturn_t i801_isr(int irq, void *dev_id)
 493 {
 494         struct i801_priv *priv = dev_id;
 495         u16 pcists;
 496         u8 status;
 497
 498         /* Confirm this is our interrupt */
 499         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 500         if (!(pcists & SMBPCISTS_INTS))
 501                 return IRQ_NONE;
 502
 503         status = inb_p(SMBHSTSTS(priv));
 504         if (status != 0x42)
 505                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 506
 507         if (status & SMBHSTSTS_BYTE_DONE)
 508                 i801_isr_byte_done(priv);
 509
 510         /*
 511          * Clear irq sources and report transaction result.
 512          * ->status must be cleared before the next transaction is started.
 513          */
 514         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 515         if (status) {
 516                 outb_p(status, SMBHSTSTS(priv));
 517                 priv->status |= status;
 518                 wake_up(&priv->waitq);
 519         }
 520
 521         return IRQ_HANDLED;
 522 }
 523
 524 /*
 525  * For "byte-by-byte" block transactions:
 526  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 527  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 528  */
 529 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 530                                                union i2c_smbus_data *data,
 531                                                char read_write, int command,
 532                                                int hwpec)
 533 {
 534         int i, len;
 535         int smbcmd;
 536         int status;
 537         int result;
 538         const struct i2c_adapter *adap = &priv->adapter;
 539
 540         result = i801_check_pre(priv);
 541         if (result < 0)
 542                 return result;
 543
 544         len = data->block[0];
 545
 546         if (read_write == I2C_SMBUS_WRITE) {
 547                 outb_p(len, SMBHSTDAT0(priv));
 548                 outb_p(data->block[1], SMBBLKDAT(priv));
 549         }
 550
 551         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 552             read_write == I2C_SMBUS_READ)
 553                 smbcmd = I801_I2C_BLOCK_DATA;
 554         else
 555                 smbcmd = I801_BLOCK_DATA;
 556
 557         if (priv->features & FEATURE_IRQ) {
 558                 priv->is_read = (read_write == I2C_SMBUS_READ);
 559                 if (len == 1 && priv->is_read)
 560                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 561                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 562                 priv->len = len;
 563                 priv->count = 0;
 564                 priv->data = &data->block[1];
 565
 566                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 567                 result = wait_event_timeout(priv->waitq,
 568                                             (status = priv->status),
 569                                             adap->timeout);
 570                 if (!result) {
 571                         status = -ETIMEDOUT;
 572                         dev_warn(&priv->pci_dev->dev,
 573                                  "Timeout waiting for interrupt!\n");
 574                 }
 575                 priv->status = 0;
 576                 return i801_check_post(priv, status);
 577         }
 578
 579         for (i = 1; i <= len; i++) {
 580                 if (i == len && read_write == I2C_SMBUS_READ)
 581                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 582                 outb_p(smbcmd, SMBHSTCNT(priv));
 583
 584                 if (i == 1)
 585                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 586                                SMBHSTCNT(priv));
 587
 588                 status = i801_wait_byte_done(priv);
 589                 if (status)
 590                         goto exit;
 591
 592                 if (i == 1 && read_write == I2C_SMBUS_READ
 593                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 594                         len = inb_p(SMBHSTDAT0(priv));
 595                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 596                                 dev_err(&priv->pci_dev->dev,
 597                                         "Illegal SMBus block read size %d\n",
 598                                         len);
 599                                 /* Recover */
 600                                 while (inb_p(SMBHSTSTS(priv)) &
 601                                        SMBHSTSTS_HOST_BUSY)
 602                                         outb_p(SMBHSTSTS_BYTE_DONE,
 603                                                SMBHSTSTS(priv));
 604                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 605                                 return -EPROTO;
 606                         }
 607                         data->block[0] = len;
 608                 }
 609
 610                 /* Retrieve/store value in SMBBLKDAT */
 611                 if (read_write == I2C_SMBUS_READ)
 612                         data->block[i] = inb_p(SMBBLKDAT(priv));
 613                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 614                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 615
 616                 /* signals SMBBLKDAT ready */
 617                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 618         }
 619
 620         status = i801_wait_intr(priv);
 621 exit:
 622         return i801_check_post(priv, status);
 623 }
 624
 625 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 626 {
 627         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 628         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 629                 return -EIO;
 630         return 0;
 631 }
 632
 633 /* Block transaction function */
 634 static int i801_block_transaction(struct i801_priv *priv,
 635                                   union i2c_smbus_data *data, char read_write,
 636                                   int command, int hwpec)
 637 {
 638         int result = 0;
 639         unsigned char hostc;
 640
 641         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 642                 if (read_write == I2C_SMBUS_WRITE) {
 643                         /* set I2C_EN bit in configuration register */
 644                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 645                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 646                                               hostc | SMBHSTCFG_I2C_EN);
 647                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 648                         dev_err(&priv->pci_dev->dev,
 649                                 "I2C block read is unsupported!\n");
 650                         return -EOPNOTSUPP;
 651                 }
 652         }
 653
 654         if (read_write == I2C_SMBUS_WRITE
 655          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 656                 if (data->block[0] < 1)
 657                         data->block[0] = 1;
 658                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 659                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 660         } else {
 661                 data->block[0] = 32;    /* max for SMBus block reads */
 662         }
 663
 664         /* Experience has shown that the block buffer can only be used for
 665            SMBus (not I2C) block transactions, even though the datasheet
 666            doesn't mention this limitation. */
 667         if ((priv->features & FEATURE_BLOCK_BUFFER)
 668          && command != I2C_SMBUS_I2C_BLOCK_DATA
 669          && i801_set_block_buffer_mode(priv) == 0)
 670                 result = i801_block_transaction_by_block(priv, data,
 671                                                          read_write, hwpec);
 672         else
 673                 result = i801_block_transaction_byte_by_byte(priv, data,
 674                                                              read_write,
 675                                                              command, hwpec);
 676
 677         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 678          && read_write == I2C_SMBUS_WRITE) {
 679                 /* restore saved configuration register value */
 680                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 681         }
 682         return result;
 683 }
 684
 685 /* Return negative errno on error. */
 686 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 687                        unsigned short flags, char read_write, u8 command,
 688                        int size, union i2c_smbus_data *data)
 689 {
 690         int hwpec;
 691         int block = 0;
 692         int ret, xact = 0;
 693         struct i801_priv *priv = i2c_get_adapdata(adap);
 694
 695         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 696                 && size != I2C_SMBUS_QUICK
 697                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 698
 699         switch (size) {
 700         case I2C_SMBUS_QUICK:
 701                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 702                        SMBHSTADD(priv));
 703                 xact = I801_QUICK;
 704                 break;
 705         case I2C_SMBUS_BYTE:
 706                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 707                        SMBHSTADD(priv));
 708                 if (read_write == I2C_SMBUS_WRITE)
 709                         outb_p(command, SMBHSTCMD(priv));
 710                 xact = I801_BYTE;
 711                 break;
 712         case I2C_SMBUS_BYTE_DATA:
 713                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 714                        SMBHSTADD(priv));
 715                 outb_p(command, SMBHSTCMD(priv));
 716                 if (read_write == I2C_SMBUS_WRITE)
 717                         outb_p(data->byte, SMBHSTDAT0(priv));
 718                 xact = I801_BYTE_DATA;
 719                 break;
 720         case I2C_SMBUS_WORD_DATA:
 721                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 722                        SMBHSTADD(priv));
 723                 outb_p(command, SMBHSTCMD(priv));
 724                 if (read_write == I2C_SMBUS_WRITE) {
 725                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 726                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 727                 }
 728                 xact = I801_WORD_DATA;
 729                 break;
 730         case I2C_SMBUS_BLOCK_DATA:
 731                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 732                        SMBHSTADD(priv));
 733                 outb_p(command, SMBHSTCMD(priv));
 734                 block = 1;
 735                 break;
 736         case I2C_SMBUS_I2C_BLOCK_DATA:
 737                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 738                  * bit should be cleared here, even when reading */
 739                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 740                 if (read_write == I2C_SMBUS_READ) {
 741                         /* NB: page 240 of ICH5 datasheet also shows
 742                          * that DATA1 is the cmd field when reading */
 743                         outb_p(command, SMBHSTDAT1(priv));
 744                 } else
 745                         outb_p(command, SMBHSTCMD(priv));
 746                 block = 1;
 747                 break;
 748         default:
 749                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 750                         size);
 751                 return -EOPNOTSUPP;
 752         }
 753
 754         if (hwpec)      /* enable/disable hardware PEC */
 755                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 756         else
 757                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 758                        SMBAUXCTL(priv));
 759
 760         if (block)
 761                 ret = i801_block_transaction(priv, data, read_write, size,
 762                                              hwpec);
 763         else
 764                 ret = i801_transaction(priv, xact);
 765
 766         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 767            time, so we forcibly disable it after every transaction. Turn off
 768            E32B for the same reason. */
 769         if (hwpec || block)
 770                 outb_p(inb_p(SMBAUXCTL(priv)) &
 771                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 772
 773         if (block)
 774                 return ret;
 775         if (ret)
 776                 return ret;
 777         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 778                 return 0;
 779
 780         switch (xact & 0x7f) {
 781         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 782         case I801_BYTE_DATA:
 783                 data->byte = inb_p(SMBHSTDAT0(priv));
 784                 break;
 785         case I801_WORD_DATA:
 786                 data->word = inb_p(SMBHSTDAT0(priv)) +
 787                              (inb_p(SMBHSTDAT1(priv)) << 8);
 788                 break;
 789         }
 790         return 0;
 791 }
 792
 793
 794 static u32 i801_func(struct i2c_adapter *adapter)
 795 {
 796         struct i801_priv *priv = i2c_get_adapdata(adapter);
 797
 798         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 799                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 800                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 801                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 802                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 803                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 804 }
 805
 806 static const struct i2c_algorithm smbus_algorithm = {
 807         .smbus_xfer     = i801_access,
 808         .functionality  = i801_func,
 809 };
 810
 811 static const struct pci_device_id i801_ids[] = {
 812         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 813         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 814         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 815         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 829         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 830         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 831         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 832         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 833         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 834         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 835         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 836         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 837         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 838         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 839         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 840         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 841         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 842         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 843         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 844         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 845         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 846         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 847         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 848         { 0, }
 849 };
 850
 851 MODULE_DEVICE_TABLE(pci, i801_ids);
 852
 853 #if defined CONFIG_X86 && defined CONFIG_DMI
 854 static unsigned char apanel_addr;
 855
 856 /* Scan the system ROM for the signature "FJKEYINF" */
 857 static __init const void __iomem *bios_signature(const void __iomem *bios)
 858 {
 859         ssize_t offset;
 860         const unsigned char signature[] = "FJKEYINF";
 861
 862         for (offset = 0; offset < 0x10000; offset += 0x10) {
 863                 if (check_signature(bios + offset, signature,
 864                                     sizeof(signature)-1))
 865                         return bios + offset;
 866         }
 867         return NULL;
 868 }
 869
 870 static void __init input_apanel_init(void)
 871 {
 872         void __iomem *bios;
 873         const void __iomem *p;
 874
 875         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 876         p = bios_signature(bios);
 877         if (p) {
 878                 /* just use the first address */
 879                 apanel_addr = readb(p + 8 + 3) >> 1;
 880         }
 881         iounmap(bios);
 882 }
 883
 884 struct dmi_onboard_device_info {
 885         const char *name;
 886         u8 type;
 887         unsigned short i2c_addr;
 888         const char *i2c_type;
 889 };
 890
 891 static const struct dmi_onboard_device_info dmi_devices[] = {
 892         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 893         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 894         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 895 };
 896
 897 static void dmi_check_onboard_device(u8 type, const char *name,
 898                                      struct i2c_adapter *adap)
 899 {
 900         int i;
 901         struct i2c_board_info info;
 902
 903         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 904                 /* & ~0x80, ignore enabled/disabled bit */
 905                 if ((type & ~0x80) != dmi_devices[i].type)
 906                         continue;
 907                 if (strcasecmp(name, dmi_devices[i].name))
 908                         continue;
 909
 910                 memset(&info, 0, sizeof(struct i2c_board_info));
 911                 info.addr = dmi_devices[i].i2c_addr;
 912                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 913                 i2c_new_device(adap, &info);
 914                 break;
 915         }
 916 }
 917
 918 /* We use our own function to check for onboard devices instead of
 919    dmi_find_device() as some buggy BIOS's have the devices we are interested
 920    in marked as disabled */
 921 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 922 {
 923         int i, count;
 924
 925         if (dm->type != 10)
 926                 return;
 927
 928         count = (dm->length - sizeof(struct dmi_header)) / 2;
 929         for (i = 0; i < count; i++) {
 930                 const u8 *d = (char *)(dm + 1) + (i * 2);
 931                 const char *name = ((char *) dm) + dm->length;
 932                 u8 type = d[0];
 933                 u8 s = d[1];
 934
 935                 if (!s)
 936                         continue;
 937                 s--;
 938                 while (s > 0 && name[0]) {
 939                         name += strlen(name) + 1;
 940                         s--;
 941                 }
 942                 if (name[0] == 0) /* Bogus string reference */
 943                         continue;
 944
 945                 dmi_check_onboard_device(type, name, adap);
 946         }
 947 }
 948
 949 /* Register optional slaves */
 950 static void i801_probe_optional_slaves(struct i801_priv *priv)
 951 {
 952         /* Only register slaves on main SMBus channel */
 953         if (priv->features & FEATURE_IDF)
 954                 return;
 955
 956         if (apanel_addr) {
 957                 struct i2c_board_info info;
 958
 959                 memset(&info, 0, sizeof(struct i2c_board_info));
 960                 info.addr = apanel_addr;
 961                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 962                 i2c_new_device(&priv->adapter, &info);
 963         }
 964
 965         if (dmi_name_in_vendors("FUJITSU"))
 966                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 967 }
 968 #else
 969 static void __init input_apanel_init(void) {}
 970 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 971 #endif  /* CONFIG_X86 && CONFIG_DMI */
 972
 973 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 974                 defined CONFIG_DMI
 975 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 976         .gpio_chip = "gpio_ich",
 977         .values = { 0x02, 0x03 },
 978         .n_values = 2,
 979         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 980         .gpios = { 52, 53 },
 981         .n_gpios = 2,
 982 };
 983
 984 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 985         .gpio_chip = "gpio_ich",
 986         .values = { 0x02, 0x03, 0x01 },
 987         .n_values = 3,
 988         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 989         .gpios = { 52, 53 },
 990         .n_gpios = 2,
 991 };
 992
 993 static const struct dmi_system_id mux_dmi_table[] = {
 994         {
 995                 .matches = {
 996                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 997                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 998                 },
 999                 .driver_data = &i801_mux_config_asus_z8_d12,
1000         },
1001         {
1002                 .matches = {
1003                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1004                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1005                 },
1006                 .driver_data = &i801_mux_config_asus_z8_d12,
1007         },
1008         {
1009                 .matches = {
1010                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1011                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1012                 },
1013                 .driver_data = &i801_mux_config_asus_z8_d12,
1014         },
1015         {
1016                 .matches = {
1017                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1018                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1019                 },
1020                 .driver_data = &i801_mux_config_asus_z8_d12,
1021         },
1022         {
1023                 .matches = {
1024                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1025                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1026                 },
1027                 .driver_data = &i801_mux_config_asus_z8_d12,
1028         },
1029         {
1030                 .matches = {
1031                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1032                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1033                 },
1034                 .driver_data = &i801_mux_config_asus_z8_d12,
1035         },
1036         {
1037                 .matches = {
1038                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1039                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1040                 },
1041                 .driver_data = &i801_mux_config_asus_z8_d18,
1042         },
1043         {
1044                 .matches = {
1045                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1046                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1047                 },
1048                 .driver_data = &i801_mux_config_asus_z8_d18,
1049         },
1050         {
1051                 .matches = {
1052                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1053                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1054                 },
1055                 .driver_data = &i801_mux_config_asus_z8_d12,
1056         },
1057         { }
1058 };
1059
1060 /* Setup multiplexing if needed */
1061 static int i801_add_mux(struct i801_priv *priv)
1062 {
1063         struct device *dev = &priv->adapter.dev;
1064         const struct i801_mux_config *mux_config;
1065         struct i2c_mux_gpio_platform_data gpio_data;
1066         int err;
1067
1068         if (!priv->mux_drvdata)
1069                 return 0;
1070         mux_config = priv->mux_drvdata;
1071
1072         /* Prepare the platform data */
1073         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1074         gpio_data.parent = priv->adapter.nr;
1075         gpio_data.values = mux_config->values;
1076         gpio_data.n_values = mux_config->n_values;
1077         gpio_data.classes = mux_config->classes;
1078         gpio_data.gpio_chip = mux_config->gpio_chip;
1079         gpio_data.gpios = mux_config->gpios;
1080         gpio_data.n_gpios = mux_config->n_gpios;
1081         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1082
1083         /* Register the mux device */
1084         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1085                                 PLATFORM_DEVID_AUTO, &gpio_data,
1086                                 sizeof(struct i2c_mux_gpio_platform_data));
1087         if (IS_ERR(priv->mux_pdev)) {
1088                 err = PTR_ERR(priv->mux_pdev);
1089                 priv->mux_pdev = NULL;
1090                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1091                 return err;
1092         }
1093
1094         return 0;
1095 }
1096
1097 static void i801_del_mux(struct i801_priv *priv)
1098 {
1099         if (priv->mux_pdev)
1100                 platform_device_unregister(priv->mux_pdev);
1101 }
1102
1103 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1104 {
1105         const struct dmi_system_id *id;
1106         const struct i801_mux_config *mux_config;
1107         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1108         int i;
1109
1110         id = dmi_first_match(mux_dmi_table);
1111         if (id) {
1112                 /* Remove branch classes from trunk */
1113                 mux_config = id->driver_data;
1114                 for (i = 0; i < mux_config->n_values; i++)
1115                         class &= ~mux_config->classes[i];
1116
1117                 /* Remember for later */
1118                 priv->mux_drvdata = mux_config;
1119         }
1120
1121         return class;
1122 }
1123 #else
1124 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1125 static inline void i801_del_mux(struct i801_priv *priv) { }
1126
1127 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1128 {
1129         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1130 }
1131 #endif
1132
1133 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1134 {
1135         unsigned char temp;
1136         int err, i;
1137         struct i801_priv *priv;
1138
1139         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1140         if (!priv)
1141                 return -ENOMEM;
1142
1143         i2c_set_adapdata(&priv->adapter, priv);
1144         priv->adapter.owner = THIS_MODULE;
1145         priv->adapter.class = i801_get_adapter_class(priv);
1146         priv->adapter.algo = &smbus_algorithm;
1147
1148         priv->pci_dev = dev;
1149         switch (dev->device) {
1150         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1151         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1152         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1153         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1154         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1155         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1156                 priv->features |= FEATURE_IDF;
1157                 /* fall through */
1158         default:
1159                 priv->features |= FEATURE_I2C_BLOCK_READ;
1160                 priv->features |= FEATURE_IRQ;
1161                 /* fall through */
1162         case PCI_DEVICE_ID_INTEL_82801DB_3:
1163                 priv->features |= FEATURE_SMBUS_PEC;
1164                 priv->features |= FEATURE_BLOCK_BUFFER;
1165                 /* fall through */
1166         case PCI_DEVICE_ID_INTEL_82801CA_3:
1167         case PCI_DEVICE_ID_INTEL_82801BA_2:
1168         case PCI_DEVICE_ID_INTEL_82801AB_3:
1169         case PCI_DEVICE_ID_INTEL_82801AA_3:
1170                 break;
1171         }
1172
1173         /* Disable features on user request */
1174         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1175                 if (priv->features & disable_features & (1 << i))
1176                         dev_notice(&dev->dev, "%s disabled by user\n",
1177                                    i801_feature_names[i]);
1178         }
1179         priv->features &= ~disable_features;
1180
1181         err = pci_enable_device(dev);
1182         if (err) {
1183                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1184                         err);
1185                 goto exit;
1186         }
1187
1188         /* Determine the address of the SMBus area */
1189         priv->smba = pci_resource_start(dev, SMBBAR);
1190         if (!priv->smba) {
1191                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1192                         "upgrade BIOS\n");
1193                 err = -ENODEV;
1194                 goto exit;
1195         }
1196
1197         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1198         if (err) {
1199                 err = -ENODEV;
1200                 goto exit;
1201         }
1202
1203         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1204         if (err) {
1205                 dev_err(&dev->dev, "Failed to request SMBus region "
1206                         "0x%lx-0x%Lx\n", priv->smba,
1207                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1208                 goto exit;
1209         }
1210
1211         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1212         priv->original_hstcfg = temp;
1213         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1214         if (!(temp & SMBHSTCFG_HST_EN)) {
1215                 dev_info(&dev->dev, "Enabling SMBus device\n");
1216                 temp |= SMBHSTCFG_HST_EN;
1217         }
1218         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1219
1220         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1221                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1222                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1223                 priv->features &= ~FEATURE_IRQ;
1224         }
1225
1226         /* Clear special mode bits */
1227         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1228                 outb_p(inb_p(SMBAUXCTL(priv)) &
1229                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1230
1231         /* Default timeout in interrupt mode: 200 ms */
1232         priv->adapter.timeout = HZ / 5;
1233
1234         if (priv->features & FEATURE_IRQ) {
1235                 init_waitqueue_head(&priv->waitq);
1236
1237                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1238                                   i801_driver.name, priv);
1239                 if (err) {
1240                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1241                                 dev->irq, err);
1242                         priv->features &= ~FEATURE_IRQ;
1243                 }
1244         }
1245         dev_info(&dev->dev, "SMBus using %s\n",
1246                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1247
1248         /* set up the sysfs linkage to our parent device */
1249         priv->adapter.dev.parent = &dev->dev;
1250
1251         /* Retry up to 3 times on lost arbitration */
1252         priv->adapter.retries = 3;
1253
1254         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1255                 "SMBus I801 adapter at %04lx", priv->smba);
1256         err = i2c_add_adapter(&priv->adapter);
1257         if (err) {
1258                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1259                 goto exit_free_irq;
1260         }
1261
1262         i801_probe_optional_slaves(priv);
1263         /* We ignore errors - multiplexing is optional */
1264         i801_add_mux(priv);
1265
1266         pci_set_drvdata(dev, priv);
1267
1268         return 0;
1269
1270 exit_free_irq:
1271         if (priv->features & FEATURE_IRQ)
1272                 free_irq(dev->irq, priv);
1273         pci_release_region(dev, SMBBAR);
1274 exit:
1275         kfree(priv);
1276         return err;
1277 }
1278
1279 static void i801_remove(struct pci_dev *dev)
1280 {
1281         struct i801_priv *priv = pci_get_drvdata(dev);
1282
1283         i801_del_mux(priv);
1284         i2c_del_adapter(&priv->adapter);
1285         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1286
1287         if (priv->features & FEATURE_IRQ)
1288                 free_irq(dev->irq, priv);
1289         pci_release_region(dev, SMBBAR);
1290
1291         kfree(priv);
1292         /*
1293          * do not call pci_disable_device(dev) since it can cause hard hangs on
1294          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1295          */
1296 }
1297
1298 #ifdef CONFIG_PM
1299 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1300 {
1301         struct i801_priv *priv = pci_get_drvdata(dev);
1302
1303         pci_save_state(dev);
1304         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1305         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1306         return 0;
1307 }
1308
1309 static int i801_resume(struct pci_dev *dev)
1310 {
1311         pci_set_power_state(dev, PCI_D0);
1312         pci_restore_state(dev);
1313         return pci_enable_device(dev);
1314 }
1315 #else
1316 #define i801_suspend NULL
1317 #define i801_resume NULL
1318 #endif
1319
1320 static struct pci_driver i801_driver = {
1321         .name           = "i801_smbus",
1322         .id_table       = i801_ids,
1323         .probe          = i801_probe,
1324         .remove         = i801_remove,
1325         .suspend        = i801_suspend,
1326         .resume         = i801_resume,
1327 };
1328
1329 static int __init i2c_i801_init(void)
1330 {
1331         if (dmi_name_in_vendors("FUJITSU"))
1332                 input_apanel_init();
1333         return pci_register_driver(&i801_driver);
1334 }
1335
1336 static void __exit i2c_i801_exit(void)
1337 {
1338         pci_unregister_driver(&i801_driver);
1339 }
1340
1341 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1342 MODULE_DESCRIPTION("I801 SMBus driver");
1343 MODULE_LICENSE("GPL");
1344
1345 module_init(i2c_i801_init);
1346 module_exit(i2c_i801_exit);