drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2012  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25  * Supports the following Intel I/O Controller Hubs (ICH):
  26  *
  27  *                                      I/O                     Block   I2C
  28  *                                      region  SMBus   Block   proc.   block
  29  * Chip name                    PCI ID  size    PEC     buffer  call    read
  30  * ---------------------------------------------------------------------------
  31  * 82801AA (ICH)                0x2413  16      no      no      no      no
  32  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  33  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  34  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  35  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  36  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  37  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  38  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  39  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  40  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  41  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  42  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  43  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  44  * ICH10                        0x3a30  32      hard    yes     yes     yes
  45  * ICH10                        0x3a60  32      hard    yes     yes     yes
  46  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  47  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  48  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  49  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  50  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  51  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  52  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  53  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  54  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  55  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  56  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  57  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  58  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  59  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  60  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  61  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  62  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  63  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  64  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  65  *
  66  * Features supported by this driver:
  67  * Software PEC                         no
  68  * Hardware PEC                         yes
  69  * Block buffer                         yes
  70  * Block process call transaction       no
  71  * I2C block read transaction           yes (doesn't use the block buffer)
  72  * Slave mode                           no
  73  * Interrupt processing                 yes
  74  *
  75  * See the file Documentation/i2c/busses/i2c-i801 for details.
  76  */
  77
  78 #include <linux/interrupt.h>
  79 #include <linux/module.h>
  80 #include <linux/pci.h>
  81 #include <linux/kernel.h>
  82 #include <linux/stddef.h>
  83 #include <linux/delay.h>
  84 #include <linux/ioport.h>
  85 #include <linux/init.h>
  86 #include <linux/i2c.h>
  87 #include <linux/acpi.h>
  88 #include <linux/io.h>
  89 #include <linux/dmi.h>
  90 #include <linux/slab.h>
  91 #include <linux/wait.h>
  92 #include <linux/err.h>
  93
  94 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  95                 defined CONFIG_DMI
  96 #include <linux/gpio.h>
  97 #include <linux/i2c-mux-gpio.h>
  98 #include <linux/platform_device.h>
  99 #endif
 100
 101 /* I801 SMBus address offsets */
 102 #define SMBHSTSTS(p)    (0 + (p)->smba)
 103 #define SMBHSTCNT(p)    (2 + (p)->smba)
 104 #define SMBHSTCMD(p)    (3 + (p)->smba)
 105 #define SMBHSTADD(p)    (4 + (p)->smba)
 106 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 107 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 108 #define SMBBLKDAT(p)    (7 + (p)->smba)
 109 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 110 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 111 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 112
 113 /* PCI Address Constants */
 114 #define SMBBAR          4
 115 #define SMBPCISTS       0x006
 116 #define SMBHSTCFG       0x040
 117
 118 /* Host status bits for SMBPCISTS */
 119 #define SMBPCISTS_INTS          0x08
 120
 121 /* Host configuration bits for SMBHSTCFG */
 122 #define SMBHSTCFG_HST_EN        1
 123 #define SMBHSTCFG_SMB_SMI_EN    2
 124 #define SMBHSTCFG_I2C_EN        4
 125
 126 /* Auxiliary control register bits, ICH4+ only */
 127 #define SMBAUXCTL_CRC           1
 128 #define SMBAUXCTL_E32B          2
 129
 130 /* Other settings */
 131 #define MAX_RETRIES             400
 132
 133 /* I801 command constants */
 134 #define I801_QUICK              0x00
 135 #define I801_BYTE               0x04
 136 #define I801_BYTE_DATA          0x08
 137 #define I801_WORD_DATA          0x0C
 138 #define I801_PROC_CALL          0x10    /* unimplemented */
 139 #define I801_BLOCK_DATA         0x14
 140 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 141
 142 /* I801 Host Control register bits */
 143 #define SMBHSTCNT_INTREN        0x01
 144 #define SMBHSTCNT_KILL          0x02
 145 #define SMBHSTCNT_LAST_BYTE     0x20
 146 #define SMBHSTCNT_START         0x40
 147 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 148
 149 /* I801 Hosts Status register bits */
 150 #define SMBHSTSTS_BYTE_DONE     0x80
 151 #define SMBHSTSTS_INUSE_STS     0x40
 152 #define SMBHSTSTS_SMBALERT_STS  0x20
 153 #define SMBHSTSTS_FAILED        0x10
 154 #define SMBHSTSTS_BUS_ERR       0x08
 155 #define SMBHSTSTS_DEV_ERR       0x04
 156 #define SMBHSTSTS_INTR          0x02
 157 #define SMBHSTSTS_HOST_BUSY     0x01
 158
 159 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 160                                  SMBHSTSTS_DEV_ERR)
 161
 162 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 163                                  STATUS_ERROR_FLAGS)
 164
 165 /* Older devices have their ID defined in <linux/pci_ids.h> */
 166 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 167 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 168 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 170 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 173 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 174 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 175 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 176 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 177 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 178 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 179 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 180 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 185 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 186 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 187
 188 struct i801_mux_config {
 189         char *gpio_chip;
 190         unsigned values[3];
 191         int n_values;
 192         unsigned classes[3];
 193         unsigned gpios[2];              /* Relative to gpio_chip->base */
 194         int n_gpios;
 195 };
 196
 197 struct i801_priv {
 198         struct i2c_adapter adapter;
 199         unsigned long smba;
 200         unsigned char original_hstcfg;
 201         struct pci_dev *pci_dev;
 202         unsigned int features;
 203
 204         /* isr processing */
 205         wait_queue_head_t waitq;
 206         u8 status;
 207
 208         /* Command state used by isr for byte-by-byte block transactions */
 209         u8 cmd;
 210         bool is_read;
 211         int count;
 212         int len;
 213         u8 *data;
 214
 215 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 216                 defined CONFIG_DMI
 217         const struct i801_mux_config *mux_drvdata;
 218         struct platform_device *mux_pdev;
 219 #endif
 220 };
 221
 222 static struct pci_driver i801_driver;
 223
 224 #define FEATURE_SMBUS_PEC       (1 << 0)
 225 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 226 #define FEATURE_BLOCK_PROC      (1 << 2)
 227 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 228 #define FEATURE_IRQ             (1 << 4)
 229 /* Not really a feature, but it's convenient to handle it as such */
 230 #define FEATURE_IDF             (1 << 15)
 231
 232 static const char *i801_feature_names[] = {
 233         "SMBus PEC",
 234         "Block buffer",
 235         "Block process call",
 236         "I2C block read",
 237         "Interrupt",
 238 };
 239
 240 static unsigned int disable_features;
 241 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 242 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 243         "\t\t  0x01  disable SMBus PEC\n"
 244         "\t\t  0x02  disable the block buffer\n"
 245         "\t\t  0x08  disable the I2C block read functionality\n"
 246         "\t\t  0x10  don't use interrupts ");
 247
 248 /* Make sure the SMBus host is ready to start transmitting.
 249    Return 0 if it is, -EBUSY if it is not. */
 250 static int i801_check_pre(struct i801_priv *priv)
 251 {
 252         int status;
 253
 254         status = inb_p(SMBHSTSTS(priv));
 255         if (status & SMBHSTSTS_HOST_BUSY) {
 256                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 257                 return -EBUSY;
 258         }
 259
 260         status &= STATUS_FLAGS;
 261         if (status) {
 262                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 263                         status);
 264                 outb_p(status, SMBHSTSTS(priv));
 265                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 266                 if (status) {
 267                         dev_err(&priv->pci_dev->dev,
 268                                 "Failed clearing status flags (%02x)\n",
 269                                 status);
 270                         return -EBUSY;
 271                 }
 272         }
 273
 274         return 0;
 275 }
 276
 277 /*
 278  * Convert the status register to an error code, and clear it.
 279  * Note that status only contains the bits we want to clear, not the
 280  * actual register value.
 281  */
 282 static int i801_check_post(struct i801_priv *priv, int status)
 283 {
 284         int result = 0;
 285
 286         /*
 287          * If the SMBus is still busy, we give up
 288          * Note: This timeout condition only happens when using polling
 289          * transactions.  For interrupt operation, NAK/timeout is indicated by
 290          * DEV_ERR.
 291          */
 292         if (unlikely(status < 0)) {
 293                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 294                 /* try to stop the current command */
 295                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 296                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 297                        SMBHSTCNT(priv));
 298                 usleep_range(1000, 2000);
 299                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 300                        SMBHSTCNT(priv));
 301
 302                 /* Check if it worked */
 303                 status = inb_p(SMBHSTSTS(priv));
 304                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 305                     !(status & SMBHSTSTS_FAILED))
 306                         dev_err(&priv->pci_dev->dev,
 307                                 "Failed terminating the transaction\n");
 308                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 309                 return -ETIMEDOUT;
 310         }
 311
 312         if (status & SMBHSTSTS_FAILED) {
 313                 result = -EIO;
 314                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 315         }
 316         if (status & SMBHSTSTS_DEV_ERR) {
 317                 result = -ENXIO;
 318                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 319         }
 320         if (status & SMBHSTSTS_BUS_ERR) {
 321                 result = -EAGAIN;
 322                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 323         }
 324
 325         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 326         outb_p(status, SMBHSTSTS(priv));
 327
 328         return result;
 329 }
 330
 331 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 332 static int i801_wait_intr(struct i801_priv *priv)
 333 {
 334         int timeout = 0;
 335         int status;
 336
 337         /* We will always wait for a fraction of a second! */
 338         do {
 339                 usleep_range(250, 500);
 340                 status = inb_p(SMBHSTSTS(priv));
 341         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 342                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 343                  (timeout++ < MAX_RETRIES));
 344
 345         if (timeout > MAX_RETRIES) {
 346                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 347                 return -ETIMEDOUT;
 348         }
 349         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 350 }
 351
 352 /* Wait for either BYTE_DONE or an error flag being set */
 353 static int i801_wait_byte_done(struct i801_priv *priv)
 354 {
 355         int timeout = 0;
 356         int status;
 357
 358         /* We will always wait for a fraction of a second! */
 359         do {
 360                 usleep_range(250, 500);
 361                 status = inb_p(SMBHSTSTS(priv));
 362         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 363                  (timeout++ < MAX_RETRIES));
 364
 365         if (timeout > MAX_RETRIES) {
 366                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 367                 return -ETIMEDOUT;
 368         }
 369         return status & STATUS_ERROR_FLAGS;
 370 }
 371
 372 static int i801_transaction(struct i801_priv *priv, int xact)
 373 {
 374         int status;
 375         int result;
 376
 377         result = i801_check_pre(priv);
 378         if (result < 0)
 379                 return result;
 380
 381         if (priv->features & FEATURE_IRQ) {
 382                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 383                        SMBHSTCNT(priv));
 384                 wait_event(priv->waitq, (status = priv->status));
 385                 priv->status = 0;
 386                 return i801_check_post(priv, status);
 387         }
 388
 389         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 390          * SMBSCMD are passed in xact */
 391         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 392
 393         status = i801_wait_intr(priv);
 394         return i801_check_post(priv, status);
 395 }
 396
 397 static int i801_block_transaction_by_block(struct i801_priv *priv,
 398                                            union i2c_smbus_data *data,
 399                                            char read_write, int hwpec)
 400 {
 401         int i, len;
 402         int status;
 403
 404         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 405
 406         /* Use 32-byte buffer to process this transaction */
 407         if (read_write == I2C_SMBUS_WRITE) {
 408                 len = data->block[0];
 409                 outb_p(len, SMBHSTDAT0(priv));
 410                 for (i = 0; i < len; i++)
 411                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 412         }
 413
 414         status = i801_transaction(priv, I801_BLOCK_DATA |
 415                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 416         if (status)
 417                 return status;
 418
 419         if (read_write == I2C_SMBUS_READ) {
 420                 len = inb_p(SMBHSTDAT0(priv));
 421                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 422                         return -EPROTO;
 423
 424                 data->block[0] = len;
 425                 for (i = 0; i < len; i++)
 426                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 427         }
 428         return 0;
 429 }
 430
 431 static void i801_isr_byte_done(struct i801_priv *priv)
 432 {
 433         if (priv->is_read) {
 434                 /* For SMBus block reads, length is received with first byte */
 435                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 436                     (priv->count == 0)) {
 437                         priv->len = inb_p(SMBHSTDAT0(priv));
 438                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 439                                 dev_err(&priv->pci_dev->dev,
 440                                         "Illegal SMBus block read size %d\n",
 441                                         priv->len);
 442                                 /* FIXME: Recover */
 443                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 444                         } else {
 445                                 dev_dbg(&priv->pci_dev->dev,
 446                                         "SMBus block read size is %d\n",
 447                                         priv->len);
 448                         }
 449                         priv->data[-1] = priv->len;
 450                 }
 451
 452                 /* Read next byte */
 453                 if (priv->count < priv->len)
 454                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 455                 else
 456                         dev_dbg(&priv->pci_dev->dev,
 457                                 "Discarding extra byte on block read\n");
 458
 459                 /* Set LAST_BYTE for last byte of read transaction */
 460                 if (priv->count == priv->len - 1)
 461                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 462                                SMBHSTCNT(priv));
 463         } else if (priv->count < priv->len - 1) {
 464                 /* Write next byte, except for IRQ after last byte */
 465                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 466         }
 467
 468         /* Clear BYTE_DONE to continue with next byte */
 469         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 470 }
 471
 472 /*
 473  * There are two kinds of interrupts:
 474  *
 475  * 1) i801 signals transaction completion with one of these interrupts:
 476  *      INTR - Success
 477  *      DEV_ERR - Invalid command, NAK or communication timeout
 478  *      BUS_ERR - SMI# transaction collision
 479  *      FAILED - transaction was canceled due to a KILL request
 480  *    When any of these occur, update ->status and wake up the waitq.
 481  *    ->status must be cleared before kicking off the next transaction.
 482  *
 483  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 484  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 485  */
 486 static irqreturn_t i801_isr(int irq, void *dev_id)
 487 {
 488         struct i801_priv *priv = dev_id;
 489         u16 pcists;
 490         u8 status;
 491
 492         /* Confirm this is our interrupt */
 493         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 494         if (!(pcists & SMBPCISTS_INTS))
 495                 return IRQ_NONE;
 496
 497         status = inb_p(SMBHSTSTS(priv));
 498         if (status != 0x42)
 499                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 500
 501         if (status & SMBHSTSTS_BYTE_DONE)
 502                 i801_isr_byte_done(priv);
 503
 504         /*
 505          * Clear irq sources and report transaction result.
 506          * ->status must be cleared before the next transaction is started.
 507          */
 508         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 509         if (status) {
 510                 outb_p(status, SMBHSTSTS(priv));
 511                 priv->status |= status;
 512                 wake_up(&priv->waitq);
 513         }
 514
 515         return IRQ_HANDLED;
 516 }
 517
 518 /*
 519  * For "byte-by-byte" block transactions:
 520  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 521  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 522  */
 523 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 524                                                union i2c_smbus_data *data,
 525                                                char read_write, int command,
 526                                                int hwpec)
 527 {
 528         int i, len;
 529         int smbcmd;
 530         int status;
 531         int result;
 532
 533         result = i801_check_pre(priv);
 534         if (result < 0)
 535                 return result;
 536
 537         len = data->block[0];
 538
 539         if (read_write == I2C_SMBUS_WRITE) {
 540                 outb_p(len, SMBHSTDAT0(priv));
 541                 outb_p(data->block[1], SMBBLKDAT(priv));
 542         }
 543
 544         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 545             read_write == I2C_SMBUS_READ)
 546                 smbcmd = I801_I2C_BLOCK_DATA;
 547         else
 548                 smbcmd = I801_BLOCK_DATA;
 549
 550         if (priv->features & FEATURE_IRQ) {
 551                 priv->is_read = (read_write == I2C_SMBUS_READ);
 552                 if (len == 1 && priv->is_read)
 553                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 554                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 555                 priv->len = len;
 556                 priv->count = 0;
 557                 priv->data = &data->block[1];
 558
 559                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 560                 wait_event(priv->waitq, (status = priv->status));
 561                 priv->status = 0;
 562                 return i801_check_post(priv, status);
 563         }
 564
 565         for (i = 1; i <= len; i++) {
 566                 if (i == len && read_write == I2C_SMBUS_READ)
 567                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 568                 outb_p(smbcmd, SMBHSTCNT(priv));
 569
 570                 if (i == 1)
 571                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 572                                SMBHSTCNT(priv));
 573
 574                 status = i801_wait_byte_done(priv);
 575                 if (status)
 576                         goto exit;
 577
 578                 if (i == 1 && read_write == I2C_SMBUS_READ
 579                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 580                         len = inb_p(SMBHSTDAT0(priv));
 581                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 582                                 dev_err(&priv->pci_dev->dev,
 583                                         "Illegal SMBus block read size %d\n",
 584                                         len);
 585                                 /* Recover */
 586                                 while (inb_p(SMBHSTSTS(priv)) &
 587                                        SMBHSTSTS_HOST_BUSY)
 588                                         outb_p(SMBHSTSTS_BYTE_DONE,
 589                                                SMBHSTSTS(priv));
 590                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 591                                 return -EPROTO;
 592                         }
 593                         data->block[0] = len;
 594                 }
 595
 596                 /* Retrieve/store value in SMBBLKDAT */
 597                 if (read_write == I2C_SMBUS_READ)
 598                         data->block[i] = inb_p(SMBBLKDAT(priv));
 599                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 600                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 601
 602                 /* signals SMBBLKDAT ready */
 603                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 604         }
 605
 606         status = i801_wait_intr(priv);
 607 exit:
 608         return i801_check_post(priv, status);
 609 }
 610
 611 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 612 {
 613         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 614         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 615                 return -EIO;
 616         return 0;
 617 }
 618
 619 /* Block transaction function */
 620 static int i801_block_transaction(struct i801_priv *priv,
 621                                   union i2c_smbus_data *data, char read_write,
 622                                   int command, int hwpec)
 623 {
 624         int result = 0;
 625         unsigned char hostc;
 626
 627         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 628                 if (read_write == I2C_SMBUS_WRITE) {
 629                         /* set I2C_EN bit in configuration register */
 630                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 631                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 632                                               hostc | SMBHSTCFG_I2C_EN);
 633                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 634                         dev_err(&priv->pci_dev->dev,
 635                                 "I2C block read is unsupported!\n");
 636                         return -EOPNOTSUPP;
 637                 }
 638         }
 639
 640         if (read_write == I2C_SMBUS_WRITE
 641          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 642                 if (data->block[0] < 1)
 643                         data->block[0] = 1;
 644                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 645                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 646         } else {
 647                 data->block[0] = 32;    /* max for SMBus block reads */
 648         }
 649
 650         /* Experience has shown that the block buffer can only be used for
 651            SMBus (not I2C) block transactions, even though the datasheet
 652            doesn't mention this limitation. */
 653         if ((priv->features & FEATURE_BLOCK_BUFFER)
 654          && command != I2C_SMBUS_I2C_BLOCK_DATA
 655          && i801_set_block_buffer_mode(priv) == 0)
 656                 result = i801_block_transaction_by_block(priv, data,
 657                                                          read_write, hwpec);
 658         else
 659                 result = i801_block_transaction_byte_by_byte(priv, data,
 660                                                              read_write,
 661                                                              command, hwpec);
 662
 663         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 664          && read_write == I2C_SMBUS_WRITE) {
 665                 /* restore saved configuration register value */
 666                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 667         }
 668         return result;
 669 }
 670
 671 /* Return negative errno on error. */
 672 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 673                        unsigned short flags, char read_write, u8 command,
 674                        int size, union i2c_smbus_data *data)
 675 {
 676         int hwpec;
 677         int block = 0;
 678         int ret, xact = 0;
 679         struct i801_priv *priv = i2c_get_adapdata(adap);
 680
 681         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 682                 && size != I2C_SMBUS_QUICK
 683                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 684
 685         switch (size) {
 686         case I2C_SMBUS_QUICK:
 687                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 688                        SMBHSTADD(priv));
 689                 xact = I801_QUICK;
 690                 break;
 691         case I2C_SMBUS_BYTE:
 692                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 693                        SMBHSTADD(priv));
 694                 if (read_write == I2C_SMBUS_WRITE)
 695                         outb_p(command, SMBHSTCMD(priv));
 696                 xact = I801_BYTE;
 697                 break;
 698         case I2C_SMBUS_BYTE_DATA:
 699                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 700                        SMBHSTADD(priv));
 701                 outb_p(command, SMBHSTCMD(priv));
 702                 if (read_write == I2C_SMBUS_WRITE)
 703                         outb_p(data->byte, SMBHSTDAT0(priv));
 704                 xact = I801_BYTE_DATA;
 705                 break;
 706         case I2C_SMBUS_WORD_DATA:
 707                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 708                        SMBHSTADD(priv));
 709                 outb_p(command, SMBHSTCMD(priv));
 710                 if (read_write == I2C_SMBUS_WRITE) {
 711                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 712                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 713                 }
 714                 xact = I801_WORD_DATA;
 715                 break;
 716         case I2C_SMBUS_BLOCK_DATA:
 717                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 718                        SMBHSTADD(priv));
 719                 outb_p(command, SMBHSTCMD(priv));
 720                 block = 1;
 721                 break;
 722         case I2C_SMBUS_I2C_BLOCK_DATA:
 723                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 724                  * bit should be cleared here, even when reading */
 725                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 726                 if (read_write == I2C_SMBUS_READ) {
 727                         /* NB: page 240 of ICH5 datasheet also shows
 728                          * that DATA1 is the cmd field when reading */
 729                         outb_p(command, SMBHSTDAT1(priv));
 730                 } else
 731                         outb_p(command, SMBHSTCMD(priv));
 732                 block = 1;
 733                 break;
 734         default:
 735                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 736                         size);
 737                 return -EOPNOTSUPP;
 738         }
 739
 740         if (hwpec)      /* enable/disable hardware PEC */
 741                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 742         else
 743                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 744                        SMBAUXCTL(priv));
 745
 746         if (block)
 747                 ret = i801_block_transaction(priv, data, read_write, size,
 748                                              hwpec);
 749         else
 750                 ret = i801_transaction(priv, xact);
 751
 752         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 753            time, so we forcibly disable it after every transaction. Turn off
 754            E32B for the same reason. */
 755         if (hwpec || block)
 756                 outb_p(inb_p(SMBAUXCTL(priv)) &
 757                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 758
 759         if (block)
 760                 return ret;
 761         if (ret)
 762                 return ret;
 763         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 764                 return 0;
 765
 766         switch (xact & 0x7f) {
 767         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 768         case I801_BYTE_DATA:
 769                 data->byte = inb_p(SMBHSTDAT0(priv));
 770                 break;
 771         case I801_WORD_DATA:
 772                 data->word = inb_p(SMBHSTDAT0(priv)) +
 773                              (inb_p(SMBHSTDAT1(priv)) << 8);
 774                 break;
 775         }
 776         return 0;
 777 }
 778
 779
 780 static u32 i801_func(struct i2c_adapter *adapter)
 781 {
 782         struct i801_priv *priv = i2c_get_adapdata(adapter);
 783
 784         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 785                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 786                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 787                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 788                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 789                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 790 }
 791
 792 static const struct i2c_algorithm smbus_algorithm = {
 793         .smbus_xfer     = i801_access,
 794         .functionality  = i801_func,
 795 };
 796
 797 static const struct pci_device_id i801_ids[] = {
 798         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 799         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 800         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 801         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 802         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 803         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 804         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 805         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 806         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 807         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 808         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 809         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 810         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 811         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 812         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 813         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 814         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 815         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 829         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 830         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 831         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 832         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 833         { 0, }
 834 };
 835
 836 MODULE_DEVICE_TABLE(pci, i801_ids);
 837
 838 #if defined CONFIG_X86 && defined CONFIG_DMI
 839 static unsigned char apanel_addr;
 840
 841 /* Scan the system ROM for the signature "FJKEYINF" */
 842 static __init const void __iomem *bios_signature(const void __iomem *bios)
 843 {
 844         ssize_t offset;
 845         const unsigned char signature[] = "FJKEYINF";
 846
 847         for (offset = 0; offset < 0x10000; offset += 0x10) {
 848                 if (check_signature(bios + offset, signature,
 849                                     sizeof(signature)-1))
 850                         return bios + offset;
 851         }
 852         return NULL;
 853 }
 854
 855 static void __init input_apanel_init(void)
 856 {
 857         void __iomem *bios;
 858         const void __iomem *p;
 859
 860         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 861         p = bios_signature(bios);
 862         if (p) {
 863                 /* just use the first address */
 864                 apanel_addr = readb(p + 8 + 3) >> 1;
 865         }
 866         iounmap(bios);
 867 }
 868
 869 struct dmi_onboard_device_info {
 870         const char *name;
 871         u8 type;
 872         unsigned short i2c_addr;
 873         const char *i2c_type;
 874 };
 875
 876 static const struct dmi_onboard_device_info dmi_devices[] = {
 877         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 878         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 879         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 880 };
 881
 882 static void dmi_check_onboard_device(u8 type, const char *name,
 883                                      struct i2c_adapter *adap)
 884 {
 885         int i;
 886         struct i2c_board_info info;
 887
 888         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 889                 /* & ~0x80, ignore enabled/disabled bit */
 890                 if ((type & ~0x80) != dmi_devices[i].type)
 891                         continue;
 892                 if (strcasecmp(name, dmi_devices[i].name))
 893                         continue;
 894
 895                 memset(&info, 0, sizeof(struct i2c_board_info));
 896                 info.addr = dmi_devices[i].i2c_addr;
 897                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 898                 i2c_new_device(adap, &info);
 899                 break;
 900         }
 901 }
 902
 903 /* We use our own function to check for onboard devices instead of
 904    dmi_find_device() as some buggy BIOS's have the devices we are interested
 905    in marked as disabled */
 906 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 907 {
 908         int i, count;
 909
 910         if (dm->type != 10)
 911                 return;
 912
 913         count = (dm->length - sizeof(struct dmi_header)) / 2;
 914         for (i = 0; i < count; i++) {
 915                 const u8 *d = (char *)(dm + 1) + (i * 2);
 916                 const char *name = ((char *) dm) + dm->length;
 917                 u8 type = d[0];
 918                 u8 s = d[1];
 919
 920                 if (!s)
 921                         continue;
 922                 s--;
 923                 while (s > 0 && name[0]) {
 924                         name += strlen(name) + 1;
 925                         s--;
 926                 }
 927                 if (name[0] == 0) /* Bogus string reference */
 928                         continue;
 929
 930                 dmi_check_onboard_device(type, name, adap);
 931         }
 932 }
 933
 934 /* Register optional slaves */
 935 static void i801_probe_optional_slaves(struct i801_priv *priv)
 936 {
 937         /* Only register slaves on main SMBus channel */
 938         if (priv->features & FEATURE_IDF)
 939                 return;
 940
 941         if (apanel_addr) {
 942                 struct i2c_board_info info;
 943
 944                 memset(&info, 0, sizeof(struct i2c_board_info));
 945                 info.addr = apanel_addr;
 946                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 947                 i2c_new_device(&priv->adapter, &info);
 948         }
 949
 950         if (dmi_name_in_vendors("FUJITSU"))
 951                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 952 }
 953 #else
 954 static void __init input_apanel_init(void) {}
 955 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 956 #endif  /* CONFIG_X86 && CONFIG_DMI */
 957
 958 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 959                 defined CONFIG_DMI
 960 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 961         .gpio_chip = "gpio_ich",
 962         .values = { 0x02, 0x03 },
 963         .n_values = 2,
 964         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 965         .gpios = { 52, 53 },
 966         .n_gpios = 2,
 967 };
 968
 969 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 970         .gpio_chip = "gpio_ich",
 971         .values = { 0x02, 0x03, 0x01 },
 972         .n_values = 3,
 973         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 974         .gpios = { 52, 53 },
 975         .n_gpios = 2,
 976 };
 977
 978 static const struct dmi_system_id mux_dmi_table[] = {
 979         {
 980                 .matches = {
 981                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 982                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 983                 },
 984                 .driver_data = &i801_mux_config_asus_z8_d12,
 985         },
 986         {
 987                 .matches = {
 988                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 989                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
 990                 },
 991                 .driver_data = &i801_mux_config_asus_z8_d12,
 992         },
 993         {
 994                 .matches = {
 995                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 996                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
 997                 },
 998                 .driver_data = &i801_mux_config_asus_z8_d12,
 999         },
1000         {
1001                 .matches = {
1002                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1003                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1004                 },
1005                 .driver_data = &i801_mux_config_asus_z8_d12,
1006         },
1007         {
1008                 .matches = {
1009                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1010                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1011                 },
1012                 .driver_data = &i801_mux_config_asus_z8_d12,
1013         },
1014         {
1015                 .matches = {
1016                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1017                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1018                 },
1019                 .driver_data = &i801_mux_config_asus_z8_d12,
1020         },
1021         {
1022                 .matches = {
1023                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1024                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1025                 },
1026                 .driver_data = &i801_mux_config_asus_z8_d18,
1027         },
1028         {
1029                 .matches = {
1030                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1031                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1032                 },
1033                 .driver_data = &i801_mux_config_asus_z8_d18,
1034         },
1035         {
1036                 .matches = {
1037                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1038                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1039                 },
1040                 .driver_data = &i801_mux_config_asus_z8_d12,
1041         },
1042         { }
1043 };
1044
1045 /* Setup multiplexing if needed */
1046 static int i801_add_mux(struct i801_priv *priv)
1047 {
1048         struct device *dev = &priv->adapter.dev;
1049         const struct i801_mux_config *mux_config;
1050         struct i2c_mux_gpio_platform_data gpio_data;
1051         int err;
1052
1053         if (!priv->mux_drvdata)
1054                 return 0;
1055         mux_config = priv->mux_drvdata;
1056
1057         /* Prepare the platform data */
1058         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1059         gpio_data.parent = priv->adapter.nr;
1060         gpio_data.values = mux_config->values;
1061         gpio_data.n_values = mux_config->n_values;
1062         gpio_data.classes = mux_config->classes;
1063         gpio_data.gpio_chip = mux_config->gpio_chip;
1064         gpio_data.gpios = mux_config->gpios;
1065         gpio_data.n_gpios = mux_config->n_gpios;
1066         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1067
1068         /* Register the mux device */
1069         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1070                                 PLATFORM_DEVID_AUTO, &gpio_data,
1071                                 sizeof(struct i2c_mux_gpio_platform_data));
1072         if (IS_ERR(priv->mux_pdev)) {
1073                 err = PTR_ERR(priv->mux_pdev);
1074                 priv->mux_pdev = NULL;
1075                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1076                 return err;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static void i801_del_mux(struct i801_priv *priv)
1083 {
1084         if (priv->mux_pdev)
1085                 platform_device_unregister(priv->mux_pdev);
1086 }
1087
1088 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1089 {
1090         const struct dmi_system_id *id;
1091         const struct i801_mux_config *mux_config;
1092         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1093         int i;
1094
1095         id = dmi_first_match(mux_dmi_table);
1096         if (id) {
1097                 /* Remove branch classes from trunk */
1098                 mux_config = id->driver_data;
1099                 for (i = 0; i < mux_config->n_values; i++)
1100                         class &= ~mux_config->classes[i];
1101
1102                 /* Remember for later */
1103                 priv->mux_drvdata = mux_config;
1104         }
1105
1106         return class;
1107 }
1108 #else
1109 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1110 static inline void i801_del_mux(struct i801_priv *priv) { }
1111
1112 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1113 {
1114         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1115 }
1116 #endif
1117
1118 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1119 {
1120         unsigned char temp;
1121         int err, i;
1122         struct i801_priv *priv;
1123
1124         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1125         if (!priv)
1126                 return -ENOMEM;
1127
1128         i2c_set_adapdata(&priv->adapter, priv);
1129         priv->adapter.owner = THIS_MODULE;
1130         priv->adapter.class = i801_get_adapter_class(priv);
1131         priv->adapter.algo = &smbus_algorithm;
1132
1133         priv->pci_dev = dev;
1134         switch (dev->device) {
1135         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1136         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1137         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1138         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1139         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1140         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1141                 priv->features |= FEATURE_IDF;
1142                 /* fall through */
1143         default:
1144                 priv->features |= FEATURE_I2C_BLOCK_READ;
1145                 priv->features |= FEATURE_IRQ;
1146                 /* fall through */
1147         case PCI_DEVICE_ID_INTEL_82801DB_3:
1148                 priv->features |= FEATURE_SMBUS_PEC;
1149                 priv->features |= FEATURE_BLOCK_BUFFER;
1150                 /* fall through */
1151         case PCI_DEVICE_ID_INTEL_82801CA_3:
1152         case PCI_DEVICE_ID_INTEL_82801BA_2:
1153         case PCI_DEVICE_ID_INTEL_82801AB_3:
1154         case PCI_DEVICE_ID_INTEL_82801AA_3:
1155                 break;
1156         }
1157
1158         /* Disable features on user request */
1159         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1160                 if (priv->features & disable_features & (1 << i))
1161                         dev_notice(&dev->dev, "%s disabled by user\n",
1162                                    i801_feature_names[i]);
1163         }
1164         priv->features &= ~disable_features;
1165
1166         err = pci_enable_device(dev);
1167         if (err) {
1168                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1169                         err);
1170                 goto exit;
1171         }
1172
1173         /* Determine the address of the SMBus area */
1174         priv->smba = pci_resource_start(dev, SMBBAR);
1175         if (!priv->smba) {
1176                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1177                         "upgrade BIOS\n");
1178                 err = -ENODEV;
1179                 goto exit;
1180         }
1181
1182         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1183         if (err) {
1184                 err = -ENODEV;
1185                 goto exit;
1186         }
1187
1188         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1189         if (err) {
1190                 dev_err(&dev->dev, "Failed to request SMBus region "
1191                         "0x%lx-0x%Lx\n", priv->smba,
1192                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1193                 goto exit;
1194         }
1195
1196         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1197         priv->original_hstcfg = temp;
1198         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1199         if (!(temp & SMBHSTCFG_HST_EN)) {
1200                 dev_info(&dev->dev, "Enabling SMBus device\n");
1201                 temp |= SMBHSTCFG_HST_EN;
1202         }
1203         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1204
1205         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1206                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1207                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1208                 priv->features &= ~FEATURE_IRQ;
1209         }
1210
1211         /* Clear special mode bits */
1212         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1213                 outb_p(inb_p(SMBAUXCTL(priv)) &
1214                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1215
1216         if (priv->features & FEATURE_IRQ) {
1217                 init_waitqueue_head(&priv->waitq);
1218
1219                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1220                                   i801_driver.name, priv);
1221                 if (err) {
1222                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1223                                 dev->irq, err);
1224                         goto exit_release;
1225                 }
1226                 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1227         }
1228
1229         /* set up the sysfs linkage to our parent device */
1230         priv->adapter.dev.parent = &dev->dev;
1231
1232         /* Retry up to 3 times on lost arbitration */
1233         priv->adapter.retries = 3;
1234
1235         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1236                 "SMBus I801 adapter at %04lx", priv->smba);
1237         err = i2c_add_adapter(&priv->adapter);
1238         if (err) {
1239                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1240                 goto exit_free_irq;
1241         }
1242
1243         i801_probe_optional_slaves(priv);
1244         /* We ignore errors - multiplexing is optional */
1245         i801_add_mux(priv);
1246
1247         pci_set_drvdata(dev, priv);
1248
1249         return 0;
1250
1251 exit_free_irq:
1252         if (priv->features & FEATURE_IRQ)
1253                 free_irq(dev->irq, priv);
1254 exit_release:
1255         pci_release_region(dev, SMBBAR);
1256 exit:
1257         kfree(priv);
1258         return err;
1259 }
1260
1261 static void i801_remove(struct pci_dev *dev)
1262 {
1263         struct i801_priv *priv = pci_get_drvdata(dev);
1264
1265         i801_del_mux(priv);
1266         i2c_del_adapter(&priv->adapter);
1267         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1268
1269         if (priv->features & FEATURE_IRQ)
1270                 free_irq(dev->irq, priv);
1271         pci_release_region(dev, SMBBAR);
1272
1273         kfree(priv);
1274         /*
1275          * do not call pci_disable_device(dev) since it can cause hard hangs on
1276          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1277          */
1278 }
1279
1280 #ifdef CONFIG_PM
1281 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1282 {
1283         struct i801_priv *priv = pci_get_drvdata(dev);
1284
1285         pci_save_state(dev);
1286         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1287         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1288         return 0;
1289 }
1290
1291 static int i801_resume(struct pci_dev *dev)
1292 {
1293         pci_set_power_state(dev, PCI_D0);
1294         pci_restore_state(dev);
1295         return pci_enable_device(dev);
1296 }
1297 #else
1298 #define i801_suspend NULL
1299 #define i801_resume NULL
1300 #endif
1301
1302 static struct pci_driver i801_driver = {
1303         .name           = "i801_smbus",
1304         .id_table       = i801_ids,
1305         .probe          = i801_probe,
1306         .remove         = i801_remove,
1307         .suspend        = i801_suspend,
1308         .resume         = i801_resume,
1309 };
1310
1311 static int __init i2c_i801_init(void)
1312 {
1313         if (dmi_name_in_vendors("FUJITSU"))
1314                 input_apanel_init();
1315         return pci_register_driver(&i801_driver);
1316 }
1317
1318 static void __exit i2c_i801_exit(void)
1319 {
1320         pci_unregister_driver(&i801_driver);
1321 }
1322
1323 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1324 MODULE_DESCRIPTION("I801 SMBus driver");
1325 MODULE_LICENSE("GPL");
1326
1327 module_init(i2c_i801_init);
1328 module_exit(i2c_i801_exit);