2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This file contains the shared part of the driver for the i2c adapter in
8 * Cavium Networks' OCTEON processors and ThunderX SOCs.
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include "i2c-octeon-core.h"
23 /* interrupt service routine */
24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
26 struct octeon_i2c *i2c = dev_id;
28 i2c->int_disable(i2c);
34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
39 static bool octeon_i2c_test_ready(struct octeon_i2c *i2c, bool *first)
41 if (octeon_i2c_test_iflg(i2c))
50 * IRQ has signaled an event but IFLG hasn't changed.
51 * Sleep and retry once.
53 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
54 return octeon_i2c_test_iflg(i2c);
58 * octeon_i2c_wait - wait for the IFLG to be set
59 * @i2c: The struct octeon_i2c
61 * Returns 0 on success, otherwise a negative errno.
63 static int octeon_i2c_wait(struct octeon_i2c *i2c)
69 * Some chip revisions don't assert the irq in the interrupt
70 * controller. So we must poll for the IFLG change.
72 if (i2c->broken_irq_mode) {
73 u64 end = get_jiffies_64() + i2c->adap.timeout;
75 while (!octeon_i2c_test_iflg(i2c) &&
76 time_before64(get_jiffies_64(), end))
77 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
79 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
83 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_ready(i2c, &first),
85 i2c->int_disable(i2c);
87 if (i2c->broken_irq_check && !time_left &&
88 octeon_i2c_test_iflg(i2c)) {
89 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
90 i2c->broken_irq_mode = true;
100 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
102 return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
105 static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c, bool *first)
107 /* check if valid bit is cleared */
108 if (octeon_i2c_hlc_test_valid(i2c))
117 * IRQ has signaled an event but valid bit isn't cleared.
118 * Sleep and retry once.
120 usleep_range(I2C_OCTEON_EVENT_WAIT, 2 * I2C_OCTEON_EVENT_WAIT);
121 return octeon_i2c_hlc_test_valid(i2c);
124 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
126 /* clear ST/TS events, listen for neither */
127 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
131 * Cleanup low-level state & enable high-level controller.
133 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
138 if (i2c->hlc_enabled)
140 i2c->hlc_enabled = true;
143 val = octeon_i2c_ctl_read(i2c);
144 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
147 /* clear IFLG event */
148 if (val & TWSI_CTL_IFLG)
149 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
152 pr_err("%s: giving up\n", __func__);
156 /* spin until any start/stop has finished */
159 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
162 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
164 if (!i2c->hlc_enabled)
167 i2c->hlc_enabled = false;
168 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
172 * octeon_i2c_hlc_wait - wait for an HLC operation to complete
173 * @i2c: The struct octeon_i2c
175 * Returns 0 on success, otherwise -ETIMEDOUT.
177 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
183 * Some cn38xx boards don't assert the irq in the interrupt
184 * controller. So we must poll for the valid bit change.
186 if (i2c->broken_irq_mode) {
187 u64 end = get_jiffies_64() + i2c->adap.timeout;
189 while (!octeon_i2c_hlc_test_valid(i2c) &&
190 time_before64(get_jiffies_64(), end))
191 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
193 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
196 i2c->hlc_int_enable(i2c);
197 time_left = wait_event_timeout(i2c->queue,
198 octeon_i2c_hlc_test_ready(i2c, &first),
200 i2c->hlc_int_disable(i2c);
202 octeon_i2c_hlc_int_clear(i2c);
204 if (i2c->broken_irq_check && !time_left &&
205 octeon_i2c_hlc_test_valid(i2c)) {
206 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
207 i2c->broken_irq_mode = true;
216 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
218 u8 stat = octeon_i2c_stat_read(i2c);
221 /* Everything is fine */
224 case STAT_RXADDR_ACK:
225 case STAT_TXADDR_ACK:
226 case STAT_TXDATA_ACK:
229 /* ACK allowed on pre-terminal bytes only */
230 case STAT_RXDATA_ACK:
235 /* NAK allowed on terminal byte only */
236 case STAT_RXDATA_NAK:
241 /* Arbitration lost */
242 case STAT_LOST_ARB_38:
243 case STAT_LOST_ARB_68:
244 case STAT_LOST_ARB_78:
245 case STAT_LOST_ARB_B0:
248 /* Being addressed as slave, should back off & listen */
251 case STAT_GENDATA_ACK:
252 case STAT_GENDATA_NAK:
255 /* Core busy as slave */
260 case STAT_SLAVE_LOST:
265 case STAT_TXDATA_NAK:
267 case STAT_TXADDR_NAK:
268 case STAT_RXADDR_NAK:
272 dev_err(i2c->dev, "unhandled state: %d\n", stat);
277 static int octeon_i2c_recovery(struct octeon_i2c *i2c)
281 ret = i2c_recover_bus(&i2c->adap);
283 /* recover failed, try hardware re-init */
284 ret = octeon_i2c_init_lowlevel(i2c);
289 * octeon_i2c_start - send START to the bus
290 * @i2c: The struct octeon_i2c
292 * Returns 0 on success, otherwise a negative errno.
294 static int octeon_i2c_start(struct octeon_i2c *i2c)
299 octeon_i2c_hlc_disable(i2c);
301 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
302 ret = octeon_i2c_wait(i2c);
306 stat = octeon_i2c_stat_read(i2c);
307 if (stat == STAT_START || stat == STAT_REP_START)
308 /* START successful, bail out */
312 /* START failed, try to recover */
313 ret = octeon_i2c_recovery(i2c);
314 return (ret) ? ret : -EAGAIN;
317 /* send STOP to the bus */
318 static void octeon_i2c_stop(struct octeon_i2c *i2c)
320 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
324 * octeon_i2c_read - receive data from the bus via low-level controller
325 * @i2c: The struct octeon_i2c
326 * @target: Target address
327 * @data: Pointer to the location to store the data
328 * @rlength: Length of the data
329 * @recv_len: flag for length byte
331 * The address is sent over the bus, then the data is read.
333 * Returns 0 on success, otherwise a negative errno.
335 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
336 u8 *data, u16 *rlength, bool recv_len)
338 int i, result, length = *rlength;
339 bool final_read = false;
341 octeon_i2c_data_write(i2c, (target << 1) | 1);
342 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
344 result = octeon_i2c_wait(i2c);
349 result = octeon_i2c_check_status(i2c, false);
353 for (i = 0; i < length; i++) {
355 * For the last byte to receive TWSI_CTL_AAK must not be set.
357 * A special case is I2C_M_RECV_LEN where we don't know the
358 * additional length yet. If recv_len is set we assume we're
359 * not reading the final byte and therefore need to set
362 if ((i + 1 == length) && !(recv_len && i == 0))
365 /* clear iflg to allow next event */
367 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
369 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
371 result = octeon_i2c_wait(i2c);
375 data[i] = octeon_i2c_data_read(i2c);
376 if (recv_len && i == 0) {
377 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
382 result = octeon_i2c_check_status(i2c, final_read);
391 * octeon_i2c_write - send data to the bus via low-level controller
392 * @i2c: The struct octeon_i2c
393 * @target: Target address
394 * @data: Pointer to the data to be sent
395 * @length: Length of the data
397 * The address is sent over the bus, then the data.
399 * Returns 0 on success, otherwise a negative errno.
401 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
402 const u8 *data, int length)
406 octeon_i2c_data_write(i2c, target << 1);
407 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
409 result = octeon_i2c_wait(i2c);
413 for (i = 0; i < length; i++) {
414 result = octeon_i2c_check_status(i2c, false);
418 octeon_i2c_data_write(i2c, data[i]);
419 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
421 result = octeon_i2c_wait(i2c);
429 /* high-level-controller pure read of up to 8 bytes */
430 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
435 octeon_i2c_hlc_enable(i2c);
436 octeon_i2c_hlc_int_clear(i2c);
438 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
440 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
442 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
444 if (msgs[0].flags & I2C_M_TEN)
445 cmd |= SW_TWSI_OP_10;
449 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
450 ret = octeon_i2c_hlc_wait(i2c);
454 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
455 if ((cmd & SW_TWSI_R) == 0)
458 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
459 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
461 if (msgs[0].len > 4) {
462 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
463 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
464 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
471 /* high-level-controller pure write of up to 8 bytes */
472 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
477 octeon_i2c_hlc_enable(i2c);
478 octeon_i2c_hlc_int_clear(i2c);
480 cmd = SW_TWSI_V | SW_TWSI_SOVR;
482 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
484 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
486 if (msgs[0].flags & I2C_M_TEN)
487 cmd |= SW_TWSI_OP_10;
491 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
492 cmd |= (u64)msgs[0].buf[j] << (8 * i);
494 if (msgs[0].len > 4) {
497 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
498 ext |= (u64)msgs[0].buf[j] << (8 * i);
499 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
502 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
503 ret = octeon_i2c_hlc_wait(i2c);
507 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
508 if ((cmd & SW_TWSI_R) == 0)
511 ret = octeon_i2c_check_status(i2c, false);
517 /* high-level-controller composite write+read, msg0=addr, msg1=data */
518 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
523 octeon_i2c_hlc_enable(i2c);
525 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
527 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
529 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
531 if (msgs[0].flags & I2C_M_TEN)
532 cmd |= SW_TWSI_OP_10_IA;
534 cmd |= SW_TWSI_OP_7_IA;
536 if (msgs[0].len == 2) {
540 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
541 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
542 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
544 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
547 octeon_i2c_hlc_int_clear(i2c);
548 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
550 ret = octeon_i2c_hlc_wait(i2c);
554 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
555 if ((cmd & SW_TWSI_R) == 0)
558 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
559 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
561 if (msgs[1].len > 4) {
562 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
563 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
564 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
571 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
572 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
574 bool set_ext = false;
578 octeon_i2c_hlc_enable(i2c);
580 cmd = SW_TWSI_V | SW_TWSI_SOVR;
582 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
584 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
586 if (msgs[0].flags & I2C_M_TEN)
587 cmd |= SW_TWSI_OP_10_IA;
589 cmd |= SW_TWSI_OP_7_IA;
591 if (msgs[0].len == 2) {
593 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
595 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
597 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
600 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
601 cmd |= (u64)msgs[1].buf[j] << (8 * i);
603 if (msgs[1].len > 4) {
604 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
605 ext |= (u64)msgs[1].buf[j] << (8 * i);
609 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
611 octeon_i2c_hlc_int_clear(i2c);
612 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
614 ret = octeon_i2c_hlc_wait(i2c);
618 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
619 if ((cmd & SW_TWSI_R) == 0)
622 ret = octeon_i2c_check_status(i2c, false);
629 * octeon_i2c_xfer - The driver's master_xfer function
630 * @adap: Pointer to the i2c_adapter structure
631 * @msgs: Pointer to the messages to be processed
632 * @num: Length of the MSGS array
634 * Returns the number of messages processed, or a negative errno on failure.
636 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
638 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
642 if (msgs[0].len > 0 && msgs[0].len <= 8) {
643 if (msgs[0].flags & I2C_M_RD)
644 ret = octeon_i2c_hlc_read(i2c, msgs);
646 ret = octeon_i2c_hlc_write(i2c, msgs);
649 } else if (num == 2) {
650 if ((msgs[0].flags & I2C_M_RD) == 0 &&
651 (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
652 msgs[0].len > 0 && msgs[0].len <= 2 &&
653 msgs[1].len > 0 && msgs[1].len <= 8 &&
654 msgs[0].addr == msgs[1].addr) {
655 if (msgs[1].flags & I2C_M_RD)
656 ret = octeon_i2c_hlc_comp_read(i2c, msgs);
658 ret = octeon_i2c_hlc_comp_write(i2c, msgs);
663 for (i = 0; ret == 0 && i < num; i++) {
664 struct i2c_msg *pmsg = &msgs[i];
666 /* zero-length messages are not supported */
672 ret = octeon_i2c_start(i2c);
676 if (pmsg->flags & I2C_M_RD)
677 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
678 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
680 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
683 octeon_i2c_stop(i2c);
685 return (ret != 0) ? ret : num;
688 /* calculate and set clock divisors */
689 void octeon_i2c_set_clock(struct octeon_i2c *i2c)
691 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
692 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
694 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
696 * An mdiv value of less than 2 seems to not work well
697 * with ds1337 RTCs, so we constrain it to larger values.
699 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
701 * For given ndiv and mdiv values check the
702 * two closest thp values.
704 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
705 tclk *= (1 << ndiv_idx);
706 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
708 for (inc = 0; inc <= 1; inc++) {
709 thp_idx = thp_base + inc;
710 if (thp_idx < 5 || thp_idx > 0xff)
713 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
714 foscl = foscl / (1 << ndiv_idx);
715 foscl = foscl / (mdiv_idx + 1) / 10;
716 diff = abs(foscl - i2c->twsi_freq);
717 if (diff < delta_hz) {
726 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
727 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
730 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
735 /* reset controller */
736 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
738 for (tries = 10; tries && status != STAT_IDLE; tries--) {
740 status = octeon_i2c_stat_read(i2c);
741 if (status == STAT_IDLE)
745 if (status != STAT_IDLE) {
746 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
751 /* toggle twice to force both teardowns */
752 octeon_i2c_hlc_enable(i2c);
753 octeon_i2c_hlc_disable(i2c);
757 static int octeon_i2c_get_scl(struct i2c_adapter *adap)
759 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
762 state = octeon_i2c_read_int(i2c);
763 return state & TWSI_INT_SCL;
766 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
768 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
770 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);
773 static int octeon_i2c_get_sda(struct i2c_adapter *adap)
775 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
778 state = octeon_i2c_read_int(i2c);
779 return state & TWSI_INT_SDA;
782 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
784 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
787 * The stop resets the state machine, does not _transmit_ STOP unless
790 octeon_i2c_stop(i2c);
792 octeon_i2c_hlc_disable(i2c);
793 octeon_i2c_write_int(i2c, 0);
796 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
798 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
800 octeon_i2c_write_int(i2c, 0);
803 struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
804 .recover_bus = i2c_generic_scl_recovery,
805 .get_scl = octeon_i2c_get_scl,
806 .set_scl = octeon_i2c_set_scl,
807 .get_sda = octeon_i2c_get_sda,
808 .prepare_recovery = octeon_i2c_prepare_recovery,
809 .unprepare_recovery = octeon_i2c_unprepare_recovery,