1 #include <linux/atomic.h>
3 #include <linux/delay.h>
4 #include <linux/device.h>
7 #include <linux/kernel.h>
10 /* Register offsets */
11 #if IS_ENABLED(CONFIG_I2C_THUNDERX)
12 #define SW_TWSI 0x1000
13 #define TWSI_INT 0x1010
14 #define SW_TWSI_EXT 0x1018
18 #define SW_TWSI_EXT 0x18
21 /* Controller command patterns */
22 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
23 #define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
24 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
25 #define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
26 #define SW_TWSI_SIZE_SHIFT 52
27 #define SW_TWSI_ADDR_SHIFT 40
28 #define SW_TWSI_IA_SHIFT 32 /* Internal address */
30 /* Controller opcode word (bits 60:57) */
31 #define SW_TWSI_OP_SHIFT 57
32 #define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
33 #define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
34 #define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
35 #define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
36 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
37 #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
39 /* Controller extended opcode word (bits 34:32) */
40 #define SW_TWSI_EOP_SHIFT 32
41 #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
42 #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
43 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
44 #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
45 #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
47 /* Controller command and status bits */
48 #define TWSI_CTL_CE 0x80 /* High level controller enable */
49 #define TWSI_CTL_ENAB 0x40 /* Bus enable */
50 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
51 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
52 #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
53 #define TWSI_CTL_AAK 0x04 /* Assert ACK */
56 #define STAT_ERROR 0x00
57 #define STAT_START 0x08
58 #define STAT_REP_START 0x10
59 #define STAT_TXADDR_ACK 0x18
60 #define STAT_TXADDR_NAK 0x20
61 #define STAT_TXDATA_ACK 0x28
62 #define STAT_TXDATA_NAK 0x30
63 #define STAT_LOST_ARB_38 0x38
64 #define STAT_RXADDR_ACK 0x40
65 #define STAT_RXADDR_NAK 0x48
66 #define STAT_RXDATA_ACK 0x50
67 #define STAT_RXDATA_NAK 0x58
68 #define STAT_SLAVE_60 0x60
69 #define STAT_LOST_ARB_68 0x68
70 #define STAT_SLAVE_70 0x70
71 #define STAT_LOST_ARB_78 0x78
72 #define STAT_SLAVE_80 0x80
73 #define STAT_SLAVE_88 0x88
74 #define STAT_GENDATA_ACK 0x90
75 #define STAT_GENDATA_NAK 0x98
76 #define STAT_SLAVE_A0 0xA0
77 #define STAT_SLAVE_A8 0xA8
78 #define STAT_LOST_ARB_B0 0xB0
79 #define STAT_SLAVE_LOST 0xB8
80 #define STAT_SLAVE_NAK 0xC0
81 #define STAT_SLAVE_ACK 0xC8
82 #define STAT_AD2W_ACK 0xD0
83 #define STAT_AD2W_NAK 0xD8
84 #define STAT_IDLE 0xF8
87 #define TWSI_INT_ST_INT BIT_ULL(0)
88 #define TWSI_INT_TS_INT BIT_ULL(1)
89 #define TWSI_INT_CORE_INT BIT_ULL(2)
90 #define TWSI_INT_ST_EN BIT_ULL(4)
91 #define TWSI_INT_TS_EN BIT_ULL(5)
92 #define TWSI_INT_CORE_EN BIT_ULL(6)
93 #define TWSI_INT_SDA_OVR BIT_ULL(8)
94 #define TWSI_INT_SCL_OVR BIT_ULL(9)
95 #define TWSI_INT_SDA BIT_ULL(10)
96 #define TWSI_INT_SCL BIT_ULL(11)
98 #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
101 wait_queue_head_t queue;
102 struct i2c_adapter adap;
105 int hlc_irq; /* For cn7890 only */
108 void __iomem *twsi_base;
111 bool broken_irq_mode;
112 bool broken_irq_check;
113 void (*int_enable)(struct octeon_i2c *);
114 void (*int_disable)(struct octeon_i2c *);
115 void (*hlc_int_enable)(struct octeon_i2c *);
116 void (*hlc_int_disable)(struct octeon_i2c *);
117 atomic_t int_enable_cnt;
118 atomic_t hlc_int_enable_cnt;
119 #if IS_ENABLED(CONFIG_I2C_THUNDERX)
120 struct msix_entry i2c_msix;
124 static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
126 __raw_writeq(val, addr);
127 __raw_readq(addr); /* wait for write to land */
131 * octeon_i2c_reg_write - write an I2C core register
132 * @i2c: The struct octeon_i2c
133 * @eop_reg: Register selector
134 * @data: Value to be written
136 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
138 static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
142 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
144 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
145 } while ((tmp & SW_TWSI_V) != 0);
148 #define octeon_i2c_ctl_write(i2c, val) \
149 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
150 #define octeon_i2c_data_write(i2c, val) \
151 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
154 * octeon_i2c_reg_read - read lower bits of an I2C core register
155 * @i2c: The struct octeon_i2c
156 * @eop_reg: Register selector
160 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
162 static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
166 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
168 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
169 } while ((tmp & SW_TWSI_V) != 0);
174 #define octeon_i2c_ctl_read(i2c) \
175 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
176 #define octeon_i2c_data_read(i2c) \
177 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
178 #define octeon_i2c_stat_read(i2c) \
179 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
182 * octeon_i2c_read_int - read the TWSI_INT register
183 * @i2c: The struct octeon_i2c
185 * Returns the value of the register.
187 static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
189 return __raw_readq(i2c->twsi_base + TWSI_INT);
193 * octeon_i2c_write_int - write the TWSI_INT register
194 * @i2c: The struct octeon_i2c
195 * @data: Value to be written
197 static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
199 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
203 irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
204 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
205 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
206 void octeon_i2c_set_clock(struct octeon_i2c *i2c);
207 extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;