drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/init.h>
  28 #include <linux/time.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/errno.h>
  32 #include <linux/err.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <linux/of_i2c.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/pinctrl/consumer.h>
  42
  43 #include <asm/irq.h>
  44
  45 #include <plat/regs-iic.h>
  46 #include <linux/platform_data/i2c-s3c2410.h>
  47
  48 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  49 #define QUIRK_S3C2440           (1 << 0)
  50 #define QUIRK_HDMIPHY           (1 << 1)
  51 #define QUIRK_NO_GPIO           (1 << 2)
  52
  53 /* Max time to wait for bus to become idle after a xfer (in us) */
  54 #define S3C2410_IDLE_TIMEOUT    5000
  55
  56 /* i2c controller state */
  57 enum s3c24xx_i2c_state {
  58         STATE_IDLE,
  59         STATE_START,
  60         STATE_READ,
  61         STATE_WRITE,
  62         STATE_STOP
  63 };
  64
  65 struct s3c24xx_i2c {
  66         wait_queue_head_t       wait;
  67         unsigned int            quirks;
  68         unsigned int            suspended:1;
  69
  70         struct i2c_msg          *msg;
  71         unsigned int            msg_num;
  72         unsigned int            msg_idx;
  73         unsigned int            msg_ptr;
  74
  75         unsigned int            tx_setup;
  76         unsigned int            irq;
  77
  78         enum s3c24xx_i2c_state  state;
  79         unsigned long           clkrate;
  80
  81         void __iomem            *regs;
  82         struct clk              *clk;
  83         struct device           *dev;
  84         struct i2c_adapter      adap;
  85
  86         struct s3c2410_platform_i2c     *pdata;
  87         int                     gpios[2];
  88         struct pinctrl          *pctrl;
  89 #ifdef CONFIG_CPU_FREQ
  90         struct notifier_block   freq_transition;
  91 #endif
  92 };
  93
  94 static struct platform_device_id s3c24xx_driver_ids[] = {
  95         {
  96                 .name           = "s3c2410-i2c",
  97                 .driver_data    = 0,
  98         }, {
  99                 .name           = "s3c2440-i2c",
 100                 .driver_data    = QUIRK_S3C2440,
 101         }, {
 102                 .name           = "s3c2440-hdmiphy-i2c",
 103                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 104         }, { },
 105 };
 106 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 107
 108 #ifdef CONFIG_OF
 109 static const struct of_device_id s3c24xx_i2c_match[] = {
 110         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 111         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 112         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 113           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 114         {},
 115 };
 116 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 117 #endif
 118
 119 /* s3c24xx_get_device_quirks
 120  *
 121  * Get controller type either from device tree or platform device variant.
 122 */
 123
 124 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev)
 125 {
 126         if (pdev->dev.of_node) {
 127                 const struct of_device_id *match;
 128                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 129                 return (unsigned int)match->data;
 130         }
 131
 132         return platform_get_device_id(pdev)->driver_data;
 133 }
 134
 135 /* s3c24xx_i2c_master_complete
 136  *
 137  * complete the message and wake up the caller, using the given return code,
 138  * or zero to mean ok.
 139 */
 140
 141 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 142 {
 143         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 144
 145         i2c->msg_ptr = 0;
 146         i2c->msg = NULL;
 147         i2c->msg_idx++;
 148         i2c->msg_num = 0;
 149         if (ret)
 150                 i2c->msg_idx = ret;
 151
 152         wake_up(&i2c->wait);
 153 }
 154
 155 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 156 {
 157         unsigned long tmp;
 158
 159         tmp = readl(i2c->regs + S3C2410_IICCON);
 160         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 161 }
 162
 163 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 164 {
 165         unsigned long tmp;
 166
 167         tmp = readl(i2c->regs + S3C2410_IICCON);
 168         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 169 }
 170
 171 /* irq enable/disable functions */
 172
 173 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 174 {
 175         unsigned long tmp;
 176
 177         tmp = readl(i2c->regs + S3C2410_IICCON);
 178         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 179 }
 180
 181 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 182 {
 183         unsigned long tmp;
 184
 185         tmp = readl(i2c->regs + S3C2410_IICCON);
 186         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 187 }
 188
 189
 190 /* s3c24xx_i2c_message_start
 191  *
 192  * put the start of a message onto the bus
 193 */
 194
 195 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 196                                       struct i2c_msg *msg)
 197 {
 198         unsigned int addr = (msg->addr & 0x7f) << 1;
 199         unsigned long stat;
 200         unsigned long iiccon;
 201
 202         stat = 0;
 203         stat |=  S3C2410_IICSTAT_TXRXEN;
 204
 205         if (msg->flags & I2C_M_RD) {
 206                 stat |= S3C2410_IICSTAT_MASTER_RX;
 207                 addr |= 1;
 208         } else
 209                 stat |= S3C2410_IICSTAT_MASTER_TX;
 210
 211         if (msg->flags & I2C_M_REV_DIR_ADDR)
 212                 addr ^= 1;
 213
 214         /* todo - check for wether ack wanted or not */
 215         s3c24xx_i2c_enable_ack(i2c);
 216
 217         iiccon = readl(i2c->regs + S3C2410_IICCON);
 218         writel(stat, i2c->regs + S3C2410_IICSTAT);
 219
 220         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 221         writeb(addr, i2c->regs + S3C2410_IICDS);
 222
 223         /* delay here to ensure the data byte has gotten onto the bus
 224          * before the transaction is started */
 225
 226         ndelay(i2c->tx_setup);
 227
 228         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 229         writel(iiccon, i2c->regs + S3C2410_IICCON);
 230
 231         stat |= S3C2410_IICSTAT_START;
 232         writel(stat, i2c->regs + S3C2410_IICSTAT);
 233 }
 234
 235 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 236 {
 237         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 238
 239         dev_dbg(i2c->dev, "STOP\n");
 240
 241         /*
 242          * The datasheet says that the STOP sequence should be:
 243          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 244          *  2) I2CCON.4 = 0     - Clear IRQPEND
 245          *  3) Wait until the stop condition takes effect.
 246          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 247          *
 248          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 249          *
 250          * However, after much experimentation, it appears that:
 251          * a) normal buses automatically clear BUSY and transition from
 252          *    Master->Slave when they complete generating a STOP condition.
 253          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 254          *    after starting the STOP generation here.
 255          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 256          *    There is no indication when this bus has finished generating
 257          *    STOP.
 258          *
 259          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 260          * step 2, the HDMIPHY bus generates the STOP condition, and then
 261          * immediately starts transferring another data byte, even though the
 262          * bus is supposedly stopped.  This is presumably because the bus is
 263          * still in "Master" mode, and its BUSY bit is still set.
 264          *
 265          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 266          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 267          * instead of first generating a proper STOP condition.  This should
 268          * float SDA & SCK terminating the transfer.  Subsequent transfers
 269          *  start with a proper START condition, and proceed normally.
 270          *
 271          * The HDMIPHY bus is an internal bus that always has exactly two
 272          * devices, the host as Master and the HDMIPHY device as the slave.
 273          * Skipping the STOP condition has been tested on this bus and works.
 274          */
 275         if (i2c->quirks & QUIRK_HDMIPHY) {
 276                 /* Stop driving the I2C pins */
 277                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 278         } else {
 279                 /* stop the transfer */
 280                 iicstat &= ~S3C2410_IICSTAT_START;
 281         }
 282         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 283
 284         i2c->state = STATE_STOP;
 285
 286         s3c24xx_i2c_master_complete(i2c, ret);
 287         s3c24xx_i2c_disable_irq(i2c);
 288 }
 289
 290 /* helper functions to determine the current state in the set of
 291  * messages we are sending */
 292
 293 /* is_lastmsg()
 294  *
 295  * returns TRUE if the current message is the last in the set
 296 */
 297
 298 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 299 {
 300         return i2c->msg_idx >= (i2c->msg_num - 1);
 301 }
 302
 303 /* is_msglast
 304  *
 305  * returns TRUE if we this is the last byte in the current message
 306 */
 307
 308 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 309 {
 310         return i2c->msg_ptr == i2c->msg->len-1;
 311 }
 312
 313 /* is_msgend
 314  *
 315  * returns TRUE if we reached the end of the current message
 316 */
 317
 318 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 319 {
 320         return i2c->msg_ptr >= i2c->msg->len;
 321 }
 322
 323 /* i2c_s3c_irq_nextbyte
 324  *
 325  * process an interrupt and work out what to do
 326  */
 327
 328 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 329 {
 330         unsigned long tmp;
 331         unsigned char byte;
 332         int ret = 0;
 333
 334         switch (i2c->state) {
 335
 336         case STATE_IDLE:
 337                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 338                 goto out;
 339
 340         case STATE_STOP:
 341                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 342                 s3c24xx_i2c_disable_irq(i2c);
 343                 goto out_ack;
 344
 345         case STATE_START:
 346                 /* last thing we did was send a start condition on the
 347                  * bus, or started a new i2c message
 348                  */
 349
 350                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 351                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 352                         /* ack was not received... */
 353
 354                         dev_dbg(i2c->dev, "ack was not received\n");
 355                         s3c24xx_i2c_stop(i2c, -ENXIO);
 356                         goto out_ack;
 357                 }
 358
 359                 if (i2c->msg->flags & I2C_M_RD)
 360                         i2c->state = STATE_READ;
 361                 else
 362                         i2c->state = STATE_WRITE;
 363
 364                 /* terminate the transfer if there is nothing to do
 365                  * as this is used by the i2c probe to find devices. */
 366
 367                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 368                         s3c24xx_i2c_stop(i2c, 0);
 369                         goto out_ack;
 370                 }
 371
 372                 if (i2c->state == STATE_READ)
 373                         goto prepare_read;
 374
 375                 /* fall through to the write state, as we will need to
 376                  * send a byte as well */
 377
 378         case STATE_WRITE:
 379                 /* we are writing data to the device... check for the
 380                  * end of the message, and if so, work out what to do
 381                  */
 382
 383                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 384                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 385                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 386
 387                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 388                                 goto out_ack;
 389                         }
 390                 }
 391
 392  retry_write:
 393
 394                 if (!is_msgend(i2c)) {
 395                         byte = i2c->msg->buf[i2c->msg_ptr++];
 396                         writeb(byte, i2c->regs + S3C2410_IICDS);
 397
 398                         /* delay after writing the byte to allow the
 399                          * data setup time on the bus, as writing the
 400                          * data to the register causes the first bit
 401                          * to appear on SDA, and SCL will change as
 402                          * soon as the interrupt is acknowledged */
 403
 404                         ndelay(i2c->tx_setup);
 405
 406                 } else if (!is_lastmsg(i2c)) {
 407                         /* we need to go to the next i2c message */
 408
 409                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 410
 411                         i2c->msg_ptr = 0;
 412                         i2c->msg_idx++;
 413                         i2c->msg++;
 414
 415                         /* check to see if we need to do another message */
 416                         if (i2c->msg->flags & I2C_M_NOSTART) {
 417
 418                                 if (i2c->msg->flags & I2C_M_RD) {
 419                                         /* cannot do this, the controller
 420                                          * forces us to send a new START
 421                                          * when we change direction */
 422
 423                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 424                                 }
 425
 426                                 goto retry_write;
 427                         } else {
 428                                 /* send the new start */
 429                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 430                                 i2c->state = STATE_START;
 431                         }
 432
 433                 } else {
 434                         /* send stop */
 435
 436                         s3c24xx_i2c_stop(i2c, 0);
 437                 }
 438                 break;
 439
 440         case STATE_READ:
 441                 /* we have a byte of data in the data register, do
 442                  * something with it, and then work out wether we are
 443                  * going to do any more read/write
 444                  */
 445
 446                 byte = readb(i2c->regs + S3C2410_IICDS);
 447                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 448
 449  prepare_read:
 450                 if (is_msglast(i2c)) {
 451                         /* last byte of buffer */
 452
 453                         if (is_lastmsg(i2c))
 454                                 s3c24xx_i2c_disable_ack(i2c);
 455
 456                 } else if (is_msgend(i2c)) {
 457                         /* ok, we've read the entire buffer, see if there
 458                          * is anything else we need to do */
 459
 460                         if (is_lastmsg(i2c)) {
 461                                 /* last message, send stop and complete */
 462                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 463
 464                                 s3c24xx_i2c_stop(i2c, 0);
 465                         } else {
 466                                 /* go to the next transfer */
 467                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 468
 469                                 i2c->msg_ptr = 0;
 470                                 i2c->msg_idx++;
 471                                 i2c->msg++;
 472                         }
 473                 }
 474
 475                 break;
 476         }
 477
 478         /* acknowlegde the IRQ and get back on with the work */
 479
 480  out_ack:
 481         tmp = readl(i2c->regs + S3C2410_IICCON);
 482         tmp &= ~S3C2410_IICCON_IRQPEND;
 483         writel(tmp, i2c->regs + S3C2410_IICCON);
 484  out:
 485         return ret;
 486 }
 487
 488 /* s3c24xx_i2c_irq
 489  *
 490  * top level IRQ servicing routine
 491 */
 492
 493 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 494 {
 495         struct s3c24xx_i2c *i2c = dev_id;
 496         unsigned long status;
 497         unsigned long tmp;
 498
 499         status = readl(i2c->regs + S3C2410_IICSTAT);
 500
 501         if (status & S3C2410_IICSTAT_ARBITR) {
 502                 /* deal with arbitration loss */
 503                 dev_err(i2c->dev, "deal with arbitration loss\n");
 504         }
 505
 506         if (i2c->state == STATE_IDLE) {
 507                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 508
 509                 tmp = readl(i2c->regs + S3C2410_IICCON);
 510                 tmp &= ~S3C2410_IICCON_IRQPEND;
 511                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 512                 goto out;
 513         }
 514
 515         /* pretty much this leaves us with the fact that we've
 516          * transmitted or received whatever byte we last sent */
 517
 518         i2c_s3c_irq_nextbyte(i2c, status);
 519
 520  out:
 521         return IRQ_HANDLED;
 522 }
 523
 524
 525 /* s3c24xx_i2c_set_master
 526  *
 527  * get the i2c bus for a master transaction
 528 */
 529
 530 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 531 {
 532         unsigned long iicstat;
 533         int timeout = 400;
 534
 535         while (timeout-- > 0) {
 536                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 537
 538                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 539                         return 0;
 540
 541                 msleep(1);
 542         }
 543
 544         return -ETIMEDOUT;
 545 }
 546
 547 /* s3c24xx_i2c_wait_idle
 548  *
 549  * wait for the i2c bus to become idle.
 550 */
 551
 552 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 553 {
 554         unsigned long iicstat;
 555         ktime_t start, now;
 556         unsigned long delay;
 557
 558         /* ensure the stop has been through the bus */
 559
 560         dev_dbg(i2c->dev, "waiting for bus idle\n");
 561
 562         start = now = ktime_get();
 563
 564         /*
 565          * Most of the time, the bus is already idle within a few usec of the
 566          * end of a transaction.  However, really slow i2c devices can stretch
 567          * the clock, delaying STOP generation.
 568          *
 569          * As a compromise between idle detection latency for the normal, fast
 570          * case, and system load in the slow device case, use an exponential
 571          * back off in the polling loop, up to 1/10th of the total timeout,
 572          * then continue to poll at a constant rate up to the timeout.
 573          */
 574         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 575         delay = 1;
 576         while ((iicstat & S3C2410_IICSTAT_START) &&
 577                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 578                 usleep_range(delay, 2 * delay);
 579                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 580                         delay <<= 1;
 581                 now = ktime_get();
 582                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 583         }
 584
 585         if (iicstat & S3C2410_IICSTAT_START)
 586                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 587 }
 588
 589 /* s3c24xx_i2c_doxfer
 590  *
 591  * this starts an i2c transfer
 592 */
 593
 594 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 595                               struct i2c_msg *msgs, int num)
 596 {
 597         unsigned long timeout;
 598         int ret;
 599
 600         if (i2c->suspended)
 601                 return -EIO;
 602
 603         ret = s3c24xx_i2c_set_master(i2c);
 604         if (ret != 0) {
 605                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 606                 ret = -EAGAIN;
 607                 goto out;
 608         }
 609
 610         i2c->msg     = msgs;
 611         i2c->msg_num = num;
 612         i2c->msg_ptr = 0;
 613         i2c->msg_idx = 0;
 614         i2c->state   = STATE_START;
 615
 616         s3c24xx_i2c_enable_irq(i2c);
 617         s3c24xx_i2c_message_start(i2c, msgs);
 618
 619         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 620
 621         ret = i2c->msg_idx;
 622
 623         /* having these next two as dev_err() makes life very
 624          * noisy when doing an i2cdetect */
 625
 626         if (timeout == 0)
 627                 dev_dbg(i2c->dev, "timeout\n");
 628         else if (ret != num)
 629                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 630
 631         /* For QUIRK_HDMIPHY, bus is already disabled */
 632         if (i2c->quirks & QUIRK_HDMIPHY)
 633                 goto out;
 634
 635         s3c24xx_i2c_wait_idle(i2c);
 636
 637  out:
 638         return ret;
 639 }
 640
 641 /* s3c24xx_i2c_xfer
 642  *
 643  * first port of call from the i2c bus code when an message needs
 644  * transferring across the i2c bus.
 645 */
 646
 647 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 648                         struct i2c_msg *msgs, int num)
 649 {
 650         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 651         int retry;
 652         int ret;
 653
 654         pm_runtime_get_sync(&adap->dev);
 655         clk_prepare_enable(i2c->clk);
 656
 657         for (retry = 0; retry < adap->retries; retry++) {
 658
 659                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 660
 661                 if (ret != -EAGAIN) {
 662                         clk_disable_unprepare(i2c->clk);
 663                         pm_runtime_put(&adap->dev);
 664                         return ret;
 665                 }
 666
 667                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 668
 669                 udelay(100);
 670         }
 671
 672         clk_disable_unprepare(i2c->clk);
 673         pm_runtime_put(&adap->dev);
 674         return -EREMOTEIO;
 675 }
 676
 677 /* declare our i2c functionality */
 678 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 679 {
 680         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 681                 I2C_FUNC_PROTOCOL_MANGLING;
 682 }
 683
 684 /* i2c bus registration info */
 685
 686 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 687         .master_xfer            = s3c24xx_i2c_xfer,
 688         .functionality          = s3c24xx_i2c_func,
 689 };
 690
 691 /* s3c24xx_i2c_calcdivisor
 692  *
 693  * return the divisor settings for a given frequency
 694 */
 695
 696 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 697                                    unsigned int *div1, unsigned int *divs)
 698 {
 699         unsigned int calc_divs = clkin / wanted;
 700         unsigned int calc_div1;
 701
 702         if (calc_divs > (16*16))
 703                 calc_div1 = 512;
 704         else
 705                 calc_div1 = 16;
 706
 707         calc_divs += calc_div1-1;
 708         calc_divs /= calc_div1;
 709
 710         if (calc_divs == 0)
 711                 calc_divs = 1;
 712         if (calc_divs > 17)
 713                 calc_divs = 17;
 714
 715         *divs = calc_divs;
 716         *div1 = calc_div1;
 717
 718         return clkin / (calc_divs * calc_div1);
 719 }
 720
 721 /* s3c24xx_i2c_clockrate
 722  *
 723  * work out a divisor for the user requested frequency setting,
 724  * either by the requested frequency, or scanning the acceptable
 725  * range of frequencies until something is found
 726 */
 727
 728 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 729 {
 730         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 731         unsigned long clkin = clk_get_rate(i2c->clk);
 732         unsigned int divs, div1;
 733         unsigned long target_frequency;
 734         u32 iiccon;
 735         int freq;
 736
 737         i2c->clkrate = clkin;
 738         clkin /= 1000;          /* clkin now in KHz */
 739
 740         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 741
 742         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 743
 744         target_frequency /= 1000; /* Target frequency now in KHz */
 745
 746         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 747
 748         if (freq > target_frequency) {
 749                 dev_err(i2c->dev,
 750                         "Unable to achieve desired frequency %luKHz."   \
 751                         " Lowest achievable %dKHz\n", target_frequency, freq);
 752                 return -EINVAL;
 753         }
 754
 755         *got = freq;
 756
 757         iiccon = readl(i2c->regs + S3C2410_IICCON);
 758         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 759         iiccon |= (divs-1);
 760
 761         if (div1 == 512)
 762                 iiccon |= S3C2410_IICCON_TXDIV_512;
 763
 764         writel(iiccon, i2c->regs + S3C2410_IICCON);
 765
 766         if (i2c->quirks & QUIRK_S3C2440) {
 767                 unsigned long sda_delay;
 768
 769                 if (pdata->sda_delay) {
 770                         sda_delay = clkin * pdata->sda_delay;
 771                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 772                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 773                         if (sda_delay > 3)
 774                                 sda_delay = 3;
 775                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 776                 } else
 777                         sda_delay = 0;
 778
 779                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 780                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 781         }
 782
 783         return 0;
 784 }
 785
 786 #ifdef CONFIG_CPU_FREQ
 787
 788 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 789
 790 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 791                                           unsigned long val, void *data)
 792 {
 793         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 794         unsigned int got;
 795         int delta_f;
 796         int ret;
 797
 798         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 799
 800         /* if we're post-change and the input clock has slowed down
 801          * or at pre-change and the clock is about to speed up, then
 802          * adjust our clock rate. <0 is slow, >0 speedup.
 803          */
 804
 805         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 806             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 807                 i2c_lock_adapter(&i2c->adap);
 808                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 809                 i2c_unlock_adapter(&i2c->adap);
 810
 811                 if (ret < 0)
 812                         dev_err(i2c->dev, "cannot find frequency\n");
 813                 else
 814                         dev_info(i2c->dev, "setting freq %d\n", got);
 815         }
 816
 817         return 0;
 818 }
 819
 820 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 821 {
 822         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 823
 824         return cpufreq_register_notifier(&i2c->freq_transition,
 825                                          CPUFREQ_TRANSITION_NOTIFIER);
 826 }
 827
 828 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 829 {
 830         cpufreq_unregister_notifier(&i2c->freq_transition,
 831                                     CPUFREQ_TRANSITION_NOTIFIER);
 832 }
 833
 834 #else
 835 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 836 {
 837         return 0;
 838 }
 839
 840 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 841 {
 842 }
 843 #endif
 844
 845 #ifdef CONFIG_OF
 846 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 847 {
 848         int idx, gpio, ret;
 849
 850         if (i2c->quirks & QUIRK_NO_GPIO)
 851                 return 0;
 852
 853         for (idx = 0; idx < 2; idx++) {
 854                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 855                 if (!gpio_is_valid(gpio)) {
 856                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 857                         goto free_gpio;
 858                 }
 859                 i2c->gpios[idx] = gpio;
 860
 861                 ret = gpio_request(gpio, "i2c-bus");
 862                 if (ret) {
 863                         dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
 864                         goto free_gpio;
 865                 }
 866         }
 867         return 0;
 868
 869 free_gpio:
 870         while (--idx >= 0)
 871                 gpio_free(i2c->gpios[idx]);
 872         return -EINVAL;
 873 }
 874
 875 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 876 {
 877         unsigned int idx;
 878
 879         if (i2c->quirks & QUIRK_NO_GPIO)
 880                 return;
 881
 882         for (idx = 0; idx < 2; idx++)
 883                 gpio_free(i2c->gpios[idx]);
 884 }
 885 #else
 886 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 887 {
 888         return 0;
 889 }
 890
 891 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 892 {
 893 }
 894 #endif
 895
 896 /* s3c24xx_i2c_init
 897  *
 898  * initialise the controller, set the IO lines and frequency
 899 */
 900
 901 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 902 {
 903         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 904         struct s3c2410_platform_i2c *pdata;
 905         unsigned int freq;
 906
 907         /* get the plafrom data */
 908
 909         pdata = i2c->pdata;
 910
 911         /* inititalise the gpio */
 912
 913         if (pdata->cfg_gpio)
 914                 pdata->cfg_gpio(to_platform_device(i2c->dev));
 915         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
 916                 return -EINVAL;
 917
 918         /* write slave address */
 919
 920         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 921
 922         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 923
 924         writel(iicon, i2c->regs + S3C2410_IICCON);
 925
 926         /* we need to work out the divisors for the clock... */
 927
 928         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 929                 writel(0, i2c->regs + S3C2410_IICCON);
 930                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 931                 return -EINVAL;
 932         }
 933
 934         /* todo - check that the i2c lines aren't being dragged anywhere */
 935
 936         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 937         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 938
 939         return 0;
 940 }
 941
 942 #ifdef CONFIG_OF
 943 /* s3c24xx_i2c_parse_dt
 944  *
 945  * Parse the device tree node and retreive the platform data.
 946 */
 947
 948 static void
 949 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
 950 {
 951         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 952
 953         if (!np)
 954                 return;
 955
 956         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
 957         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
 958         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
 959         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
 960                                 (u32 *)&pdata->frequency);
 961 }
 962 #else
 963 static void
 964 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
 965 {
 966         return;
 967 }
 968 #endif
 969
 970 /* s3c24xx_i2c_probe
 971  *
 972  * called by the bus driver when a suitable device is found
 973 */
 974
 975 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 976 {
 977         struct s3c24xx_i2c *i2c;
 978         struct s3c2410_platform_i2c *pdata = NULL;
 979         struct resource *res;
 980         int ret;
 981
 982         if (!pdev->dev.of_node) {
 983                 pdata = pdev->dev.platform_data;
 984                 if (!pdata) {
 985                         dev_err(&pdev->dev, "no platform data\n");
 986                         return -EINVAL;
 987                 }
 988         }
 989
 990         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
 991         if (!i2c) {
 992                 dev_err(&pdev->dev, "no memory for state\n");
 993                 return -ENOMEM;
 994         }
 995
 996         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 997         if (!i2c->pdata) {
 998                 ret = -ENOMEM;
 999                 goto err_noclk;
1000         }
1001
1002         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1003         if (pdata)
1004                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1005         else
1006                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1007
1008         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1009         i2c->adap.owner   = THIS_MODULE;
1010         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
1011         i2c->adap.retries = 2;
1012         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1013         i2c->tx_setup     = 50;
1014
1015         init_waitqueue_head(&i2c->wait);
1016
1017         /* find the clock and enable it */
1018
1019         i2c->dev = &pdev->dev;
1020         i2c->clk = clk_get(&pdev->dev, "i2c");
1021         if (IS_ERR(i2c->clk)) {
1022                 dev_err(&pdev->dev, "cannot get clock\n");
1023                 ret = -ENOENT;
1024                 goto err_noclk;
1025         }
1026
1027         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1028
1029         clk_prepare_enable(i2c->clk);
1030
1031         /* map the registers */
1032
1033         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034         if (res == NULL) {
1035                 dev_err(&pdev->dev, "cannot find IO resource\n");
1036                 ret = -ENOENT;
1037                 goto err_clk;
1038         }
1039
1040         i2c->regs = devm_request_and_ioremap(&pdev->dev, res);
1041
1042         if (i2c->regs == NULL) {
1043                 dev_err(&pdev->dev, "cannot map IO\n");
1044                 ret = -ENXIO;
1045                 goto err_clk;
1046         }
1047
1048         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1049                 i2c->regs, res);
1050
1051         /* setup info block for the i2c core */
1052
1053         i2c->adap.algo_data = i2c;
1054         i2c->adap.dev.parent = &pdev->dev;
1055
1056         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1057
1058         /* initialise the i2c controller */
1059
1060         ret = s3c24xx_i2c_init(i2c);
1061         if (ret != 0)
1062                 goto err_clk;
1063
1064         /* find the IRQ for this unit (note, this relies on the init call to
1065          * ensure no current IRQs pending
1066          */
1067
1068         i2c->irq = ret = platform_get_irq(pdev, 0);
1069         if (ret <= 0) {
1070                 dev_err(&pdev->dev, "cannot find IRQ\n");
1071                 goto err_clk;
1072         }
1073
1074         ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
1075                           dev_name(&pdev->dev), i2c);
1076
1077         if (ret != 0) {
1078                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1079                 goto err_clk;
1080         }
1081
1082         ret = s3c24xx_i2c_register_cpufreq(i2c);
1083         if (ret < 0) {
1084                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1085                 goto err_irq;
1086         }
1087
1088         /* Note, previous versions of the driver used i2c_add_adapter()
1089          * to add the bus at any number. We now pass the bus number via
1090          * the platform data, so if unset it will now default to always
1091          * being bus 0.
1092          */
1093
1094         i2c->adap.nr = i2c->pdata->bus_num;
1095         i2c->adap.dev.of_node = pdev->dev.of_node;
1096
1097         ret = i2c_add_numbered_adapter(&i2c->adap);
1098         if (ret < 0) {
1099                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1100                 goto err_cpufreq;
1101         }
1102
1103         of_i2c_register_devices(&i2c->adap);
1104         platform_set_drvdata(pdev, i2c);
1105
1106         pm_runtime_enable(&pdev->dev);
1107         pm_runtime_enable(&i2c->adap.dev);
1108
1109         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1110         clk_disable_unprepare(i2c->clk);
1111         return 0;
1112
1113  err_cpufreq:
1114         s3c24xx_i2c_deregister_cpufreq(i2c);
1115
1116  err_irq:
1117         free_irq(i2c->irq, i2c);
1118
1119  err_clk:
1120         clk_disable_unprepare(i2c->clk);
1121         clk_put(i2c->clk);
1122
1123  err_noclk:
1124         return ret;
1125 }
1126
1127 /* s3c24xx_i2c_remove
1128  *
1129  * called when device is removed from the bus
1130 */
1131
1132 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1133 {
1134         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1135
1136         pm_runtime_disable(&i2c->adap.dev);
1137         pm_runtime_disable(&pdev->dev);
1138
1139         s3c24xx_i2c_deregister_cpufreq(i2c);
1140
1141         i2c_del_adapter(&i2c->adap);
1142         free_irq(i2c->irq, i2c);
1143
1144         clk_disable_unprepare(i2c->clk);
1145         clk_put(i2c->clk);
1146
1147         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1148                 s3c24xx_i2c_dt_gpio_free(i2c);
1149
1150         return 0;
1151 }
1152
1153 #ifdef CONFIG_PM_SLEEP
1154 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1155 {
1156         struct platform_device *pdev = to_platform_device(dev);
1157         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1158
1159         i2c->suspended = 1;
1160
1161         return 0;
1162 }
1163
1164 static int s3c24xx_i2c_resume(struct device *dev)
1165 {
1166         struct platform_device *pdev = to_platform_device(dev);
1167         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1168
1169         i2c->suspended = 0;
1170         clk_prepare_enable(i2c->clk);
1171         s3c24xx_i2c_init(i2c);
1172         clk_disable_unprepare(i2c->clk);
1173
1174         return 0;
1175 }
1176 #endif
1177
1178 #ifdef CONFIG_PM
1179 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1180 #ifdef CONFIG_PM_SLEEP
1181         .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1182         .resume = s3c24xx_i2c_resume,
1183 #endif
1184 };
1185
1186 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1187 #else
1188 #define S3C24XX_DEV_PM_OPS NULL
1189 #endif
1190
1191 /* device driver for platform bus bits */
1192
1193 static struct platform_driver s3c24xx_i2c_driver = {
1194         .probe          = s3c24xx_i2c_probe,
1195         .remove         = s3c24xx_i2c_remove,
1196         .id_table       = s3c24xx_driver_ids,
1197         .driver         = {
1198                 .owner  = THIS_MODULE,
1199                 .name   = "s3c-i2c",
1200                 .pm     = S3C24XX_DEV_PM_OPS,
1201                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1202         },
1203 };
1204
1205 static int __init i2c_adap_s3c_init(void)
1206 {
1207         return platform_driver_register(&s3c24xx_i2c_driver);
1208 }
1209 subsys_initcall(i2c_adap_s3c_init);
1210
1211 static void __exit i2c_adap_s3c_exit(void)
1212 {
1213         platform_driver_unregister(&s3c24xx_i2c_driver);
1214 }
1215 module_exit(i2c_adap_s3c_exit);
1216
1217 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1218 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1219 MODULE_LICENSE("GPL");