drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/init.h>
  28 #include <linux/time.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <linux/errno.h>
  32 #include <linux/err.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clk.h>
  36 #include <linux/cpufreq.h>
  37 #include <linux/slab.h>
  38 #include <linux/io.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/pinctrl/consumer.h>
  41
  42 #include <asm/irq.h>
  43
  44 #include <linux/platform_data/i2c-s3c2410.h>
  45
  46 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  47
  48 #define S3C2410_IICCON                  0x00
  49 #define S3C2410_IICSTAT                 0x04
  50 #define S3C2410_IICADD                  0x08
  51 #define S3C2410_IICDS                   0x0C
  52 #define S3C2440_IICLC                   0x10
  53
  54 #define S3C2410_IICCON_ACKEN            (1 << 7)
  55 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  56 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  57 #define S3C2410_IICCON_IRQEN            (1 << 5)
  58 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  59 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  60 #define S3C2410_IICCON_SCALEMASK        (0xf)
  61
  62 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  63 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  64 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  65 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  66 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  67
  68 #define S3C2410_IICSTAT_START           (1 << 5)
  69 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  70 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  71 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  72 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  73 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  74 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  75
  76 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  77 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  78 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  79 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  80 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  81
  82 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  83
  84 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  85 #define QUIRK_S3C2440           (1 << 0)
  86 #define QUIRK_HDMIPHY           (1 << 1)
  87 #define QUIRK_NO_GPIO           (1 << 2)
  88
  89 /* Max time to wait for bus to become idle after a xfer (in us) */
  90 #define S3C2410_IDLE_TIMEOUT    5000
  91
  92 /* i2c controller state */
  93 enum s3c24xx_i2c_state {
  94         STATE_IDLE,
  95         STATE_START,
  96         STATE_READ,
  97         STATE_WRITE,
  98         STATE_STOP
  99 };
 100
 101 struct s3c24xx_i2c {
 102         wait_queue_head_t       wait;
 103         unsigned int            quirks;
 104         unsigned int            suspended:1;
 105
 106         struct i2c_msg          *msg;
 107         unsigned int            msg_num;
 108         unsigned int            msg_idx;
 109         unsigned int            msg_ptr;
 110
 111         unsigned int            tx_setup;
 112         unsigned int            irq;
 113
 114         enum s3c24xx_i2c_state  state;
 115         unsigned long           clkrate;
 116
 117         void __iomem            *regs;
 118         struct clk              *clk;
 119         struct device           *dev;
 120         struct i2c_adapter      adap;
 121
 122         struct s3c2410_platform_i2c     *pdata;
 123         int                     gpios[2];
 124         struct pinctrl          *pctrl;
 125 #ifdef CONFIG_CPU_FREQ
 126         struct notifier_block   freq_transition;
 127 #endif
 128 };
 129
 130 static struct platform_device_id s3c24xx_driver_ids[] = {
 131         {
 132                 .name           = "s3c2410-i2c",
 133                 .driver_data    = 0,
 134         }, {
 135                 .name           = "s3c2440-i2c",
 136                 .driver_data    = QUIRK_S3C2440,
 137         }, {
 138                 .name           = "s3c2440-hdmiphy-i2c",
 139                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 140         }, { },
 141 };
 142 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 143
 144 #ifdef CONFIG_OF
 145 static const struct of_device_id s3c24xx_i2c_match[] = {
 146         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 147         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 148         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 149           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 150         { .compatible = "samsung,exynos5440-i2c",
 151           .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
 152         {},
 153 };
 154 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 155 #endif
 156
 157 /* s3c24xx_get_device_quirks
 158  *
 159  * Get controller type either from device tree or platform device variant.
 160 */
 161
 162 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev)
 163 {
 164         if (pdev->dev.of_node) {
 165                 const struct of_device_id *match;
 166                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 167                 return (unsigned int)match->data;
 168         }
 169
 170         return platform_get_device_id(pdev)->driver_data;
 171 }
 172
 173 /* s3c24xx_i2c_master_complete
 174  *
 175  * complete the message and wake up the caller, using the given return code,
 176  * or zero to mean ok.
 177 */
 178
 179 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 180 {
 181         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 182
 183         i2c->msg_ptr = 0;
 184         i2c->msg = NULL;
 185         i2c->msg_idx++;
 186         i2c->msg_num = 0;
 187         if (ret)
 188                 i2c->msg_idx = ret;
 189
 190         wake_up(&i2c->wait);
 191 }
 192
 193 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 194 {
 195         unsigned long tmp;
 196
 197         tmp = readl(i2c->regs + S3C2410_IICCON);
 198         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 199 }
 200
 201 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 202 {
 203         unsigned long tmp;
 204
 205         tmp = readl(i2c->regs + S3C2410_IICCON);
 206         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 207 }
 208
 209 /* irq enable/disable functions */
 210
 211 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 212 {
 213         unsigned long tmp;
 214
 215         tmp = readl(i2c->regs + S3C2410_IICCON);
 216         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 217 }
 218
 219 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 220 {
 221         unsigned long tmp;
 222
 223         tmp = readl(i2c->regs + S3C2410_IICCON);
 224         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 225 }
 226
 227
 228 /* s3c24xx_i2c_message_start
 229  *
 230  * put the start of a message onto the bus
 231 */
 232
 233 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 234                                       struct i2c_msg *msg)
 235 {
 236         unsigned int addr = (msg->addr & 0x7f) << 1;
 237         unsigned long stat;
 238         unsigned long iiccon;
 239
 240         stat = 0;
 241         stat |=  S3C2410_IICSTAT_TXRXEN;
 242
 243         if (msg->flags & I2C_M_RD) {
 244                 stat |= S3C2410_IICSTAT_MASTER_RX;
 245                 addr |= 1;
 246         } else
 247                 stat |= S3C2410_IICSTAT_MASTER_TX;
 248
 249         if (msg->flags & I2C_M_REV_DIR_ADDR)
 250                 addr ^= 1;
 251
 252         /* todo - check for whether ack wanted or not */
 253         s3c24xx_i2c_enable_ack(i2c);
 254
 255         iiccon = readl(i2c->regs + S3C2410_IICCON);
 256         writel(stat, i2c->regs + S3C2410_IICSTAT);
 257
 258         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 259         writeb(addr, i2c->regs + S3C2410_IICDS);
 260
 261         /* delay here to ensure the data byte has gotten onto the bus
 262          * before the transaction is started */
 263
 264         ndelay(i2c->tx_setup);
 265
 266         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 267         writel(iiccon, i2c->regs + S3C2410_IICCON);
 268
 269         stat |= S3C2410_IICSTAT_START;
 270         writel(stat, i2c->regs + S3C2410_IICSTAT);
 271 }
 272
 273 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 274 {
 275         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 276
 277         dev_dbg(i2c->dev, "STOP\n");
 278
 279         /*
 280          * The datasheet says that the STOP sequence should be:
 281          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 282          *  2) I2CCON.4 = 0     - Clear IRQPEND
 283          *  3) Wait until the stop condition takes effect.
 284          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 285          *
 286          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 287          *
 288          * However, after much experimentation, it appears that:
 289          * a) normal buses automatically clear BUSY and transition from
 290          *    Master->Slave when they complete generating a STOP condition.
 291          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 292          *    after starting the STOP generation here.
 293          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 294          *    There is no indication when this bus has finished generating
 295          *    STOP.
 296          *
 297          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 298          * step 2, the HDMIPHY bus generates the STOP condition, and then
 299          * immediately starts transferring another data byte, even though the
 300          * bus is supposedly stopped.  This is presumably because the bus is
 301          * still in "Master" mode, and its BUSY bit is still set.
 302          *
 303          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 304          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 305          * instead of first generating a proper STOP condition.  This should
 306          * float SDA & SCK terminating the transfer.  Subsequent transfers
 307          *  start with a proper START condition, and proceed normally.
 308          *
 309          * The HDMIPHY bus is an internal bus that always has exactly two
 310          * devices, the host as Master and the HDMIPHY device as the slave.
 311          * Skipping the STOP condition has been tested on this bus and works.
 312          */
 313         if (i2c->quirks & QUIRK_HDMIPHY) {
 314                 /* Stop driving the I2C pins */
 315                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 316         } else {
 317                 /* stop the transfer */
 318                 iicstat &= ~S3C2410_IICSTAT_START;
 319         }
 320         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 321
 322         i2c->state = STATE_STOP;
 323
 324         s3c24xx_i2c_master_complete(i2c, ret);
 325         s3c24xx_i2c_disable_irq(i2c);
 326 }
 327
 328 /* helper functions to determine the current state in the set of
 329  * messages we are sending */
 330
 331 /* is_lastmsg()
 332  *
 333  * returns TRUE if the current message is the last in the set
 334 */
 335
 336 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 337 {
 338         return i2c->msg_idx >= (i2c->msg_num - 1);
 339 }
 340
 341 /* is_msglast
 342  *
 343  * returns TRUE if we this is the last byte in the current message
 344 */
 345
 346 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 347 {
 348         /* msg->len is always 1 for the first byte of smbus block read.
 349          * Actual length will be read from slave. More bytes will be
 350          * read according to the length then. */
 351         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 352                 return 0;
 353
 354         return i2c->msg_ptr == i2c->msg->len-1;
 355 }
 356
 357 /* is_msgend
 358  *
 359  * returns TRUE if we reached the end of the current message
 360 */
 361
 362 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 363 {
 364         return i2c->msg_ptr >= i2c->msg->len;
 365 }
 366
 367 /* i2c_s3c_irq_nextbyte
 368  *
 369  * process an interrupt and work out what to do
 370  */
 371
 372 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 373 {
 374         unsigned long tmp;
 375         unsigned char byte;
 376         int ret = 0;
 377
 378         switch (i2c->state) {
 379
 380         case STATE_IDLE:
 381                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 382                 goto out;
 383
 384         case STATE_STOP:
 385                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 386                 s3c24xx_i2c_disable_irq(i2c);
 387                 goto out_ack;
 388
 389         case STATE_START:
 390                 /* last thing we did was send a start condition on the
 391                  * bus, or started a new i2c message
 392                  */
 393
 394                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 395                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 396                         /* ack was not received... */
 397
 398                         dev_dbg(i2c->dev, "ack was not received\n");
 399                         s3c24xx_i2c_stop(i2c, -ENXIO);
 400                         goto out_ack;
 401                 }
 402
 403                 if (i2c->msg->flags & I2C_M_RD)
 404                         i2c->state = STATE_READ;
 405                 else
 406                         i2c->state = STATE_WRITE;
 407
 408                 /* terminate the transfer if there is nothing to do
 409                  * as this is used by the i2c probe to find devices. */
 410
 411                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 412                         s3c24xx_i2c_stop(i2c, 0);
 413                         goto out_ack;
 414                 }
 415
 416                 if (i2c->state == STATE_READ)
 417                         goto prepare_read;
 418
 419                 /* fall through to the write state, as we will need to
 420                  * send a byte as well */
 421
 422         case STATE_WRITE:
 423                 /* we are writing data to the device... check for the
 424                  * end of the message, and if so, work out what to do
 425                  */
 426
 427                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 428                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 429                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 430
 431                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 432                                 goto out_ack;
 433                         }
 434                 }
 435
 436  retry_write:
 437
 438                 if (!is_msgend(i2c)) {
 439                         byte = i2c->msg->buf[i2c->msg_ptr++];
 440                         writeb(byte, i2c->regs + S3C2410_IICDS);
 441
 442                         /* delay after writing the byte to allow the
 443                          * data setup time on the bus, as writing the
 444                          * data to the register causes the first bit
 445                          * to appear on SDA, and SCL will change as
 446                          * soon as the interrupt is acknowledged */
 447
 448                         ndelay(i2c->tx_setup);
 449
 450                 } else if (!is_lastmsg(i2c)) {
 451                         /* we need to go to the next i2c message */
 452
 453                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 454
 455                         i2c->msg_ptr = 0;
 456                         i2c->msg_idx++;
 457                         i2c->msg++;
 458
 459                         /* check to see if we need to do another message */
 460                         if (i2c->msg->flags & I2C_M_NOSTART) {
 461
 462                                 if (i2c->msg->flags & I2C_M_RD) {
 463                                         /* cannot do this, the controller
 464                                          * forces us to send a new START
 465                                          * when we change direction */
 466
 467                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 468                                 }
 469
 470                                 goto retry_write;
 471                         } else {
 472                                 /* send the new start */
 473                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 474                                 i2c->state = STATE_START;
 475                         }
 476
 477                 } else {
 478                         /* send stop */
 479
 480                         s3c24xx_i2c_stop(i2c, 0);
 481                 }
 482                 break;
 483
 484         case STATE_READ:
 485                 /* we have a byte of data in the data register, do
 486                  * something with it, and then work out whether we are
 487                  * going to do any more read/write
 488                  */
 489
 490                 byte = readb(i2c->regs + S3C2410_IICDS);
 491                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 492
 493                 /* Add actual length to read for smbus block read */
 494                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 495                         i2c->msg->len += byte;
 496  prepare_read:
 497                 if (is_msglast(i2c)) {
 498                         /* last byte of buffer */
 499
 500                         if (is_lastmsg(i2c))
 501                                 s3c24xx_i2c_disable_ack(i2c);
 502
 503                 } else if (is_msgend(i2c)) {
 504                         /* ok, we've read the entire buffer, see if there
 505                          * is anything else we need to do */
 506
 507                         if (is_lastmsg(i2c)) {
 508                                 /* last message, send stop and complete */
 509                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 510
 511                                 s3c24xx_i2c_stop(i2c, 0);
 512                         } else {
 513                                 /* go to the next transfer */
 514                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 515
 516                                 i2c->msg_ptr = 0;
 517                                 i2c->msg_idx++;
 518                                 i2c->msg++;
 519                         }
 520                 }
 521
 522                 break;
 523         }
 524
 525         /* acknowlegde the IRQ and get back on with the work */
 526
 527  out_ack:
 528         tmp = readl(i2c->regs + S3C2410_IICCON);
 529         tmp &= ~S3C2410_IICCON_IRQPEND;
 530         writel(tmp, i2c->regs + S3C2410_IICCON);
 531  out:
 532         return ret;
 533 }
 534
 535 /* s3c24xx_i2c_irq
 536  *
 537  * top level IRQ servicing routine
 538 */
 539
 540 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 541 {
 542         struct s3c24xx_i2c *i2c = dev_id;
 543         unsigned long status;
 544         unsigned long tmp;
 545
 546         status = readl(i2c->regs + S3C2410_IICSTAT);
 547
 548         if (status & S3C2410_IICSTAT_ARBITR) {
 549                 /* deal with arbitration loss */
 550                 dev_err(i2c->dev, "deal with arbitration loss\n");
 551         }
 552
 553         if (i2c->state == STATE_IDLE) {
 554                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 555
 556                 tmp = readl(i2c->regs + S3C2410_IICCON);
 557                 tmp &= ~S3C2410_IICCON_IRQPEND;
 558                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 559                 goto out;
 560         }
 561
 562         /* pretty much this leaves us with the fact that we've
 563          * transmitted or received whatever byte we last sent */
 564
 565         i2c_s3c_irq_nextbyte(i2c, status);
 566
 567  out:
 568         return IRQ_HANDLED;
 569 }
 570
 571
 572 /* s3c24xx_i2c_set_master
 573  *
 574  * get the i2c bus for a master transaction
 575 */
 576
 577 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 578 {
 579         unsigned long iicstat;
 580         int timeout = 400;
 581
 582         while (timeout-- > 0) {
 583                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 584
 585                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 586                         return 0;
 587
 588                 msleep(1);
 589         }
 590
 591         return -ETIMEDOUT;
 592 }
 593
 594 /* s3c24xx_i2c_wait_idle
 595  *
 596  * wait for the i2c bus to become idle.
 597 */
 598
 599 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 600 {
 601         unsigned long iicstat;
 602         ktime_t start, now;
 603         unsigned long delay;
 604         int spins;
 605
 606         /* ensure the stop has been through the bus */
 607
 608         dev_dbg(i2c->dev, "waiting for bus idle\n");
 609
 610         start = now = ktime_get();
 611
 612         /*
 613          * Most of the time, the bus is already idle within a few usec of the
 614          * end of a transaction.  However, really slow i2c devices can stretch
 615          * the clock, delaying STOP generation.
 616          *
 617          * On slower SoCs this typically happens within a very small number of
 618          * instructions so busy wait briefly to avoid scheduling overhead.
 619          */
 620         spins = 3;
 621         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 622         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 623                 cpu_relax();
 624                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 625         }
 626
 627         /*
 628          * If we do get an appreciable delay as a compromise between idle
 629          * detection latency for the normal, fast case, and system load in the
 630          * slow device case, use an exponential back off in the polling loop,
 631          * up to 1/10th of the total timeout, then continue to poll at a
 632          * constant rate up to the timeout.
 633          */
 634         delay = 1;
 635         while ((iicstat & S3C2410_IICSTAT_START) &&
 636                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 637                 usleep_range(delay, 2 * delay);
 638                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 639                         delay <<= 1;
 640                 now = ktime_get();
 641                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 642         }
 643
 644         if (iicstat & S3C2410_IICSTAT_START)
 645                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 646 }
 647
 648 /* s3c24xx_i2c_doxfer
 649  *
 650  * this starts an i2c transfer
 651 */
 652
 653 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 654                               struct i2c_msg *msgs, int num)
 655 {
 656         unsigned long timeout;
 657         int ret;
 658
 659         if (i2c->suspended)
 660                 return -EIO;
 661
 662         ret = s3c24xx_i2c_set_master(i2c);
 663         if (ret != 0) {
 664                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 665                 ret = -EAGAIN;
 666                 goto out;
 667         }
 668
 669         i2c->msg     = msgs;
 670         i2c->msg_num = num;
 671         i2c->msg_ptr = 0;
 672         i2c->msg_idx = 0;
 673         i2c->state   = STATE_START;
 674
 675         s3c24xx_i2c_enable_irq(i2c);
 676         s3c24xx_i2c_message_start(i2c, msgs);
 677
 678         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 679
 680         ret = i2c->msg_idx;
 681
 682         /* having these next two as dev_err() makes life very
 683          * noisy when doing an i2cdetect */
 684
 685         if (timeout == 0)
 686                 dev_dbg(i2c->dev, "timeout\n");
 687         else if (ret != num)
 688                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 689
 690         /* For QUIRK_HDMIPHY, bus is already disabled */
 691         if (i2c->quirks & QUIRK_HDMIPHY)
 692                 goto out;
 693
 694         s3c24xx_i2c_wait_idle(i2c);
 695
 696  out:
 697         return ret;
 698 }
 699
 700 /* s3c24xx_i2c_xfer
 701  *
 702  * first port of call from the i2c bus code when an message needs
 703  * transferring across the i2c bus.
 704 */
 705
 706 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 707                         struct i2c_msg *msgs, int num)
 708 {
 709         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 710         int retry;
 711         int ret;
 712
 713         pm_runtime_get_sync(&adap->dev);
 714         clk_prepare_enable(i2c->clk);
 715
 716         for (retry = 0; retry < adap->retries; retry++) {
 717
 718                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 719
 720                 if (ret != -EAGAIN) {
 721                         clk_disable_unprepare(i2c->clk);
 722                         pm_runtime_put(&adap->dev);
 723                         return ret;
 724                 }
 725
 726                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 727
 728                 udelay(100);
 729         }
 730
 731         clk_disable_unprepare(i2c->clk);
 732         pm_runtime_put(&adap->dev);
 733         return -EREMOTEIO;
 734 }
 735
 736 /* declare our i2c functionality */
 737 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 738 {
 739         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 740                 I2C_FUNC_PROTOCOL_MANGLING;
 741 }
 742
 743 /* i2c bus registration info */
 744
 745 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 746         .master_xfer            = s3c24xx_i2c_xfer,
 747         .functionality          = s3c24xx_i2c_func,
 748 };
 749
 750 /* s3c24xx_i2c_calcdivisor
 751  *
 752  * return the divisor settings for a given frequency
 753 */
 754
 755 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 756                                    unsigned int *div1, unsigned int *divs)
 757 {
 758         unsigned int calc_divs = clkin / wanted;
 759         unsigned int calc_div1;
 760
 761         if (calc_divs > (16*16))
 762                 calc_div1 = 512;
 763         else
 764                 calc_div1 = 16;
 765
 766         calc_divs += calc_div1-1;
 767         calc_divs /= calc_div1;
 768
 769         if (calc_divs == 0)
 770                 calc_divs = 1;
 771         if (calc_divs > 17)
 772                 calc_divs = 17;
 773
 774         *divs = calc_divs;
 775         *div1 = calc_div1;
 776
 777         return clkin / (calc_divs * calc_div1);
 778 }
 779
 780 /* s3c24xx_i2c_clockrate
 781  *
 782  * work out a divisor for the user requested frequency setting,
 783  * either by the requested frequency, or scanning the acceptable
 784  * range of frequencies until something is found
 785 */
 786
 787 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 788 {
 789         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 790         unsigned long clkin = clk_get_rate(i2c->clk);
 791         unsigned int divs, div1;
 792         unsigned long target_frequency;
 793         u32 iiccon;
 794         int freq;
 795
 796         i2c->clkrate = clkin;
 797         clkin /= 1000;          /* clkin now in KHz */
 798
 799         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 800
 801         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 802
 803         target_frequency /= 1000; /* Target frequency now in KHz */
 804
 805         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 806
 807         if (freq > target_frequency) {
 808                 dev_err(i2c->dev,
 809                         "Unable to achieve desired frequency %luKHz."   \
 810                         " Lowest achievable %dKHz\n", target_frequency, freq);
 811                 return -EINVAL;
 812         }
 813
 814         *got = freq;
 815
 816         iiccon = readl(i2c->regs + S3C2410_IICCON);
 817         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 818         iiccon |= (divs-1);
 819
 820         if (div1 == 512)
 821                 iiccon |= S3C2410_IICCON_TXDIV_512;
 822
 823         writel(iiccon, i2c->regs + S3C2410_IICCON);
 824
 825         if (i2c->quirks & QUIRK_S3C2440) {
 826                 unsigned long sda_delay;
 827
 828                 if (pdata->sda_delay) {
 829                         sda_delay = clkin * pdata->sda_delay;
 830                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 831                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 832                         if (sda_delay > 3)
 833                                 sda_delay = 3;
 834                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 835                 } else
 836                         sda_delay = 0;
 837
 838                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 839                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 840         }
 841
 842         return 0;
 843 }
 844
 845 #ifdef CONFIG_CPU_FREQ
 846
 847 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 848
 849 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 850                                           unsigned long val, void *data)
 851 {
 852         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 853         unsigned int got;
 854         int delta_f;
 855         int ret;
 856
 857         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 858
 859         /* if we're post-change and the input clock has slowed down
 860          * or at pre-change and the clock is about to speed up, then
 861          * adjust our clock rate. <0 is slow, >0 speedup.
 862          */
 863
 864         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 865             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 866                 i2c_lock_adapter(&i2c->adap);
 867                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 868                 i2c_unlock_adapter(&i2c->adap);
 869
 870                 if (ret < 0)
 871                         dev_err(i2c->dev, "cannot find frequency\n");
 872                 else
 873                         dev_info(i2c->dev, "setting freq %d\n", got);
 874         }
 875
 876         return 0;
 877 }
 878
 879 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 880 {
 881         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 882
 883         return cpufreq_register_notifier(&i2c->freq_transition,
 884                                          CPUFREQ_TRANSITION_NOTIFIER);
 885 }
 886
 887 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 888 {
 889         cpufreq_unregister_notifier(&i2c->freq_transition,
 890                                     CPUFREQ_TRANSITION_NOTIFIER);
 891 }
 892
 893 #else
 894 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 895 {
 896         return 0;
 897 }
 898
 899 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 900 {
 901 }
 902 #endif
 903
 904 #ifdef CONFIG_OF
 905 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 906 {
 907         int idx, gpio, ret;
 908
 909         if (i2c->quirks & QUIRK_NO_GPIO)
 910                 return 0;
 911
 912         for (idx = 0; idx < 2; idx++) {
 913                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 914                 if (!gpio_is_valid(gpio)) {
 915                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 916                         goto free_gpio;
 917                 }
 918                 i2c->gpios[idx] = gpio;
 919
 920                 ret = gpio_request(gpio, "i2c-bus");
 921                 if (ret) {
 922                         dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
 923                         goto free_gpio;
 924                 }
 925         }
 926         return 0;
 927
 928 free_gpio:
 929         while (--idx >= 0)
 930                 gpio_free(i2c->gpios[idx]);
 931         return -EINVAL;
 932 }
 933
 934 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 935 {
 936         unsigned int idx;
 937
 938         if (i2c->quirks & QUIRK_NO_GPIO)
 939                 return;
 940
 941         for (idx = 0; idx < 2; idx++)
 942                 gpio_free(i2c->gpios[idx]);
 943 }
 944 #else
 945 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 946 {
 947         return 0;
 948 }
 949
 950 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 951 {
 952 }
 953 #endif
 954
 955 /* s3c24xx_i2c_init
 956  *
 957  * initialise the controller, set the IO lines and frequency
 958 */
 959
 960 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 961 {
 962         unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
 963         struct s3c2410_platform_i2c *pdata;
 964         unsigned int freq;
 965
 966         /* get the plafrom data */
 967
 968         pdata = i2c->pdata;
 969
 970         /* write slave address */
 971
 972         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 973
 974         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 975
 976         writel(iicon, i2c->regs + S3C2410_IICCON);
 977
 978         /* we need to work out the divisors for the clock... */
 979
 980         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 981                 writel(0, i2c->regs + S3C2410_IICCON);
 982                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
 983                 return -EINVAL;
 984         }
 985
 986         /* todo - check that the i2c lines aren't being dragged anywhere */
 987
 988         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
 989         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
 990
 991         return 0;
 992 }
 993
 994 #ifdef CONFIG_OF
 995 /* s3c24xx_i2c_parse_dt
 996  *
 997  * Parse the device tree node and retreive the platform data.
 998 */
 999
1000 static void
1001 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1002 {
1003         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1004
1005         if (!np)
1006                 return;
1007
1008         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1009         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1010         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1011         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1012                                 (u32 *)&pdata->frequency);
1013 }
1014 #else
1015 static void
1016 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1017 {
1018         return;
1019 }
1020 #endif
1021
1022 /* s3c24xx_i2c_probe
1023  *
1024  * called by the bus driver when a suitable device is found
1025 */
1026
1027 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1028 {
1029         struct s3c24xx_i2c *i2c;
1030         struct s3c2410_platform_i2c *pdata = NULL;
1031         struct resource *res;
1032         int ret;
1033
1034         if (!pdev->dev.of_node) {
1035                 pdata = dev_get_platdata(&pdev->dev);
1036                 if (!pdata) {
1037                         dev_err(&pdev->dev, "no platform data\n");
1038                         return -EINVAL;
1039                 }
1040         }
1041
1042         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1043         if (!i2c) {
1044                 dev_err(&pdev->dev, "no memory for state\n");
1045                 return -ENOMEM;
1046         }
1047
1048         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1049         if (!i2c->pdata) {
1050                 dev_err(&pdev->dev, "no memory for platform data\n");
1051                 return -ENOMEM;
1052         }
1053
1054         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1055         if (pdata)
1056                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1057         else
1058                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1059
1060         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1061         i2c->adap.owner   = THIS_MODULE;
1062         i2c->adap.algo    = &s3c24xx_i2c_algorithm;
1063         i2c->adap.retries = 2;
1064         i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1065         i2c->tx_setup     = 50;
1066
1067         init_waitqueue_head(&i2c->wait);
1068
1069         /* find the clock and enable it */
1070
1071         i2c->dev = &pdev->dev;
1072         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1073         if (IS_ERR(i2c->clk)) {
1074                 dev_err(&pdev->dev, "cannot get clock\n");
1075                 return -ENOENT;
1076         }
1077
1078         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1079
1080
1081         /* map the registers */
1082
1083         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1084         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1085
1086         if (IS_ERR(i2c->regs))
1087                 return PTR_ERR(i2c->regs);
1088
1089         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1090                 i2c->regs, res);
1091
1092         /* setup info block for the i2c core */
1093
1094         i2c->adap.algo_data = i2c;
1095         i2c->adap.dev.parent = &pdev->dev;
1096
1097         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1098
1099         /* inititalise the i2c gpio lines */
1100
1101         if (i2c->pdata->cfg_gpio) {
1102                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1103         } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1104                 return -EINVAL;
1105         }
1106
1107         /* initialise the i2c controller */
1108
1109         clk_prepare_enable(i2c->clk);
1110         ret = s3c24xx_i2c_init(i2c);
1111         clk_disable_unprepare(i2c->clk);
1112         if (ret != 0) {
1113                 dev_err(&pdev->dev, "I2C controller init failed\n");
1114                 return ret;
1115         }
1116         /* find the IRQ for this unit (note, this relies on the init call to
1117          * ensure no current IRQs pending
1118          */
1119
1120         i2c->irq = ret = platform_get_irq(pdev, 0);
1121         if (ret <= 0) {
1122                 dev_err(&pdev->dev, "cannot find IRQ\n");
1123                 return ret;
1124         }
1125
1126         ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
1127                                dev_name(&pdev->dev), i2c);
1128
1129         if (ret != 0) {
1130                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1131                 return ret;
1132         }
1133
1134         ret = s3c24xx_i2c_register_cpufreq(i2c);
1135         if (ret < 0) {
1136                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1137                 return ret;
1138         }
1139
1140         /* Note, previous versions of the driver used i2c_add_adapter()
1141          * to add the bus at any number. We now pass the bus number via
1142          * the platform data, so if unset it will now default to always
1143          * being bus 0.
1144          */
1145
1146         i2c->adap.nr = i2c->pdata->bus_num;
1147         i2c->adap.dev.of_node = pdev->dev.of_node;
1148
1149         ret = i2c_add_numbered_adapter(&i2c->adap);
1150         if (ret < 0) {
1151                 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1152                 s3c24xx_i2c_deregister_cpufreq(i2c);
1153                 return ret;
1154         }
1155
1156         platform_set_drvdata(pdev, i2c);
1157
1158         pm_runtime_enable(&pdev->dev);
1159         pm_runtime_enable(&i2c->adap.dev);
1160
1161         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1162         return 0;
1163 }
1164
1165 /* s3c24xx_i2c_remove
1166  *
1167  * called when device is removed from the bus
1168 */
1169
1170 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1171 {
1172         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1173
1174         pm_runtime_disable(&i2c->adap.dev);
1175         pm_runtime_disable(&pdev->dev);
1176
1177         s3c24xx_i2c_deregister_cpufreq(i2c);
1178
1179         i2c_del_adapter(&i2c->adap);
1180
1181         clk_disable_unprepare(i2c->clk);
1182
1183         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1184                 s3c24xx_i2c_dt_gpio_free(i2c);
1185
1186         return 0;
1187 }
1188
1189 #ifdef CONFIG_PM_SLEEP
1190 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1191 {
1192         struct platform_device *pdev = to_platform_device(dev);
1193         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1194
1195         i2c->suspended = 1;
1196
1197         return 0;
1198 }
1199
1200 static int s3c24xx_i2c_resume(struct device *dev)
1201 {
1202         struct platform_device *pdev = to_platform_device(dev);
1203         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1204
1205         i2c->suspended = 0;
1206         clk_prepare_enable(i2c->clk);
1207         s3c24xx_i2c_init(i2c);
1208         clk_disable_unprepare(i2c->clk);
1209
1210         return 0;
1211 }
1212 #endif
1213
1214 #ifdef CONFIG_PM
1215 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1216 #ifdef CONFIG_PM_SLEEP
1217         .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1218         .resume = s3c24xx_i2c_resume,
1219 #endif
1220 };
1221
1222 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1223 #else
1224 #define S3C24XX_DEV_PM_OPS NULL
1225 #endif
1226
1227 /* device driver for platform bus bits */
1228
1229 static struct platform_driver s3c24xx_i2c_driver = {
1230         .probe          = s3c24xx_i2c_probe,
1231         .remove         = s3c24xx_i2c_remove,
1232         .id_table       = s3c24xx_driver_ids,
1233         .driver         = {
1234                 .owner  = THIS_MODULE,
1235                 .name   = "s3c-i2c",
1236                 .pm     = S3C24XX_DEV_PM_OPS,
1237                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1238         },
1239 };
1240
1241 static int __init i2c_adap_s3c_init(void)
1242 {
1243         return platform_driver_register(&s3c24xx_i2c_driver);
1244 }
1245 subsys_initcall(i2c_adap_s3c_init);
1246
1247 static void __exit i2c_adap_s3c_exit(void)
1248 {
1249         platform_driver_unregister(&s3c24xx_i2c_driver);
1250 }
1251 module_exit(i2c_adap_s3c_exit);
1252
1253 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1254 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1255 MODULE_LICENSE("GPL");