drivers/i2c/busses/i2c-sh_mobile.c

   1 /*
   2  * SuperH Mobile I2C Controller
   3  *
   4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  *
   8  * Portions of the code based on out-of-tree driver i2c-sh7343.c
   9  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/err.h>
  26 #include <linux/i2c.h>
  27 #include <linux/i2c/i2c-sh_mobile.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/of_device.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/slab.h>
  37
  38 /* Transmit operation:                                                      */
  39 /*                                                                          */
  40 /* 0 byte transmit                                                          */
  41 /* BUS:     S     A8     ACK   P(*)                                         */
  42 /* IRQ:       DTE   WAIT                                                    */
  43 /* ICIC:                                                                    */
  44 /* ICCR: 0x94 0x90                                                          */
  45 /* ICDR:      A8                                                            */
  46 /*                                                                          */
  47 /* 1 byte transmit                                                          */
  48 /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  49 /* IRQ:       DTE   WAIT         WAIT                                       */
  50 /* ICIC:      -DTE                                                          */
  51 /* ICCR: 0x94       0x90                                                    */
  52 /* ICDR:      A8    D8(1)                                                   */
  53 /*                                                                          */
  54 /* 2 byte transmit                                                          */
  55 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  56 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  57 /* ICIC:      -DTE                                                          */
  58 /* ICCR: 0x94                    0x90                                       */
  59 /* ICDR:      A8    D8(1)        D8(2)                                      */
  60 /*                                                                          */
  61 /* 3 bytes or more, +---------+ gets repeated                               */
  62 /*                                                                          */
  63 /*                                                                          */
  64 /* Receive operation:                                                       */
  65 /*                                                                          */
  66 /* 0 byte receive - not supported since slave may hold SDA low              */
  67 /*                                                                          */
  68 /* 1 byte receive       [TX] | [RX]                                         */
  69 /* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  70 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  71 /* ICIC:      -DTE           |   +DTE                                       */
  72 /* ICCR: 0x94       0x81     |   0xc0                                       */
  73 /* ICDR:      A8             |            D8(1)                             */
  74 /*                                                                          */
  75 /* 2 byte receive        [TX]| [RX]                                         */
  76 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  77 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  78 /* ICIC:      -DTE           |                 +DTE                         */
  79 /* ICCR: 0x94       0x81     |                 0xc0                         */
  80 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  81 /*                                                                          */
  82 /* 3 byte receive       [TX] | [RX]                                     (*) */
  83 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  84 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  85 /* ICIC:      -DTE           |                              +DTE            */
  86 /* ICCR: 0x94       0x81     |                              0xc0            */
  87 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  88 /*                                                                          */
  89 /* 4 bytes or more, this part is repeated    +---------+                    */
  90 /*                                                                          */
  91 /*                                                                          */
  92 /* Interrupt order and BUSY flag                                            */
  93 /*     ___                                                 _                */
  94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  95 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  96 /*                                                                          */
  97 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  98 /*                                           ___                            */
  99 /* WAIT IRQ ________________________________/   \___________                */
 100 /* TACK IRQ ____________________________________/   \_______                */
 101 /* DTE  IRQ __________________________________________/   \_                */
 102 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 103 /*         _______________________________________________                  */
 104 /* BUSY __/                                               \_                */
 105 /*                                                                          */
 106 /* (*) The STOP condition is only sent by the master at the end of the last */
 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
 108 /* only cleared after the STOP condition, so, between messages we have to   */
 109 /* poll for the DTE bit.                                                    */
 110 /*                                                                          */
 111
 112 enum sh_mobile_i2c_op {
 113         OP_START = 0,
 114         OP_TX_FIRST,
 115         OP_TX,
 116         OP_TX_STOP,
 117         OP_TX_STOP_DATA,
 118         OP_TX_TO_RX,
 119         OP_RX,
 120         OP_RX_STOP,
 121         OP_RX_STOP_DATA,
 122 };
 123
 124 struct sh_mobile_i2c_data {
 125         struct device *dev;
 126         void __iomem *reg;
 127         struct i2c_adapter adap;
 128         unsigned long bus_speed;
 129         unsigned int clks_per_count;
 130         struct clk *clk;
 131         u_int8_t icic;
 132         u_int8_t flags;
 133         u_int16_t iccl;
 134         u_int16_t icch;
 135
 136         spinlock_t lock;
 137         wait_queue_head_t wait;
 138         struct i2c_msg *msg;
 139         int pos;
 140         int sr;
 141         bool send_stop;
 142         bool stop_after_dma;
 143
 144         struct resource *res;
 145         struct dma_chan *dma_tx;
 146         struct dma_chan *dma_rx;
 147         struct scatterlist sg;
 148         enum dma_data_direction dma_direction;
 149 };
 150
 151 struct sh_mobile_dt_config {
 152         int clks_per_count;
 153         void (*setup)(struct sh_mobile_i2c_data *pd);
 154 };
 155
 156 #define IIC_FLAG_HAS_ICIC67     (1 << 0)
 157
 158 #define STANDARD_MODE           100000
 159 #define FAST_MODE               400000
 160
 161 /* Register offsets */
 162 #define ICDR                    0x00
 163 #define ICCR                    0x04
 164 #define ICSR                    0x08
 165 #define ICIC                    0x0c
 166 #define ICCL                    0x10
 167 #define ICCH                    0x14
 168 #define ICSTART                 0x70
 169
 170 /* Register bits */
 171 #define ICCR_ICE                0x80
 172 #define ICCR_RACK               0x40
 173 #define ICCR_TRS                0x10
 174 #define ICCR_BBSY               0x04
 175 #define ICCR_SCP                0x01
 176
 177 #define ICSR_SCLM               0x80
 178 #define ICSR_SDAM               0x40
 179 #define SW_DONE                 0x20
 180 #define ICSR_BUSY               0x10
 181 #define ICSR_AL                 0x08
 182 #define ICSR_TACK               0x04
 183 #define ICSR_WAIT               0x02
 184 #define ICSR_DTE                0x01
 185
 186 #define ICIC_ICCLB8             0x80
 187 #define ICIC_ICCHB8             0x40
 188 #define ICIC_TDMAE              0x20
 189 #define ICIC_RDMAE              0x10
 190 #define ICIC_ALE                0x08
 191 #define ICIC_TACKE              0x04
 192 #define ICIC_WAITE              0x02
 193 #define ICIC_DTEE               0x01
 194
 195 #define ICSTART_ICSTART         0x10
 196
 197 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 198 {
 199         if (offs == ICIC)
 200                 data |= pd->icic;
 201
 202         iowrite8(data, pd->reg + offs);
 203 }
 204
 205 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 206 {
 207         return ioread8(pd->reg + offs);
 208 }
 209
 210 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 211                         unsigned char set, unsigned char clr)
 212 {
 213         iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 214 }
 215
 216 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 217 {
 218         /*
 219          * Conditional expression:
 220          *   ICCL >= COUNT_CLK * (tLOW + tf)
 221          *
 222          * SH-Mobile IIC hardware starts counting the LOW period of
 223          * the SCL signal (tLOW) as soon as it pulls the SCL line.
 224          * In order to meet the tLOW timing spec, we need to take into
 225          * account the fall time of SCL signal (tf).  Default tf value
 226          * should be 0.3 us, for safety.
 227          */
 228         return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 229 }
 230
 231 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 232 {
 233         /*
 234          * Conditional expression:
 235          *   ICCH >= COUNT_CLK * (tHIGH + tf)
 236          *
 237          * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 238          * and can ignore it.  SH-Mobile IIC controller starts counting
 239          * the HIGH period of the SCL signal (tHIGH) after the SCL input
 240          * voltage increases at VIH.
 241          *
 242          * Afterward it turned out calculating ICCH using only tHIGH spec
 243          * will result in violation of the tHD;STA timing spec.  We need
 244          * to take into account the fall time of SDA signal (tf) at START
 245          * condition, in order to meet both tHIGH and tHD;STA specs.
 246          */
 247         return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 248 }
 249
 250 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 251 {
 252         unsigned long i2c_clk_khz;
 253         u32 tHIGH, tLOW, tf;
 254         uint16_t max_val;
 255
 256         /* Get clock rate after clock is enabled */
 257         clk_prepare_enable(pd->clk);
 258         i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
 259         clk_disable_unprepare(pd->clk);
 260         i2c_clk_khz /= pd->clks_per_count;
 261
 262         if (pd->bus_speed == STANDARD_MODE) {
 263                 tLOW    = 47;   /* tLOW = 4.7 us */
 264                 tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 265                 tf      = 3;    /* tf = 0.3 us */
 266         } else if (pd->bus_speed == FAST_MODE) {
 267                 tLOW    = 13;   /* tLOW = 1.3 us */
 268                 tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 269                 tf      = 3;    /* tf = 0.3 us */
 270         } else {
 271                 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 272                         pd->bus_speed);
 273                 return -EINVAL;
 274         }
 275
 276         pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 277         pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 278
 279         max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 280         if (pd->iccl > max_val || pd->icch > max_val) {
 281                 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 282                         pd->iccl, pd->icch);
 283                 return -EINVAL;
 284         }
 285
 286         /* one more bit of ICCL in ICIC */
 287         if (pd->iccl & 0x100)
 288                 pd->icic |= ICIC_ICCLB8;
 289         else
 290                 pd->icic &= ~ICIC_ICCLB8;
 291
 292         /* one more bit of ICCH in ICIC */
 293         if (pd->icch & 0x100)
 294                 pd->icic |= ICIC_ICCHB8;
 295         else
 296                 pd->icic &= ~ICIC_ICCHB8;
 297
 298         dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 299         return 0;
 300 }
 301
 302 static void activate_ch(struct sh_mobile_i2c_data *pd)
 303 {
 304         /* Wake up device and enable clock */
 305         pm_runtime_get_sync(pd->dev);
 306         clk_prepare_enable(pd->clk);
 307
 308         /* Enable channel and configure rx ack */
 309         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 310
 311         /* Mask all interrupts */
 312         iic_wr(pd, ICIC, 0);
 313
 314         /* Set the clock */
 315         iic_wr(pd, ICCL, pd->iccl & 0xff);
 316         iic_wr(pd, ICCH, pd->icch & 0xff);
 317 }
 318
 319 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 320 {
 321         /* Clear/disable interrupts */
 322         iic_wr(pd, ICSR, 0);
 323         iic_wr(pd, ICIC, 0);
 324
 325         /* Disable channel */
 326         iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 327
 328         /* Disable clock and mark device as idle */
 329         clk_disable_unprepare(pd->clk);
 330         pm_runtime_put_sync(pd->dev);
 331 }
 332
 333 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 334                             enum sh_mobile_i2c_op op, unsigned char data)
 335 {
 336         unsigned char ret = 0;
 337         unsigned long flags;
 338
 339         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 340
 341         spin_lock_irqsave(&pd->lock, flags);
 342
 343         switch (op) {
 344         case OP_START: /* issue start and trigger DTE interrupt */
 345                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 346                 break;
 347         case OP_TX_FIRST: /* disable DTE interrupt and write data */
 348                 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 349                 iic_wr(pd, ICDR, data);
 350                 break;
 351         case OP_TX: /* write data */
 352                 iic_wr(pd, ICDR, data);
 353                 break;
 354         case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
 355                 iic_wr(pd, ICDR, data);
 356                 /* fallthrough */
 357         case OP_TX_STOP: /* issue a stop */
 358                 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 359                                                : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 360                 break;
 361         case OP_TX_TO_RX: /* select read mode */
 362                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 363                 break;
 364         case OP_RX: /* just read data */
 365                 ret = iic_rd(pd, ICDR);
 366                 break;
 367         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 368                 iic_wr(pd, ICIC,
 369                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 370                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 371                 break;
 372         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 373                 iic_wr(pd, ICIC,
 374                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 375                 ret = iic_rd(pd, ICDR);
 376                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 377                 break;
 378         }
 379
 380         spin_unlock_irqrestore(&pd->lock, flags);
 381
 382         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 383         return ret;
 384 }
 385
 386 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 387 {
 388         return pd->pos == -1;
 389 }
 390
 391 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
 392 {
 393         return pd->pos == pd->msg->len - 1;
 394 }
 395
 396 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 397                                    unsigned char *buf)
 398 {
 399         switch (pd->pos) {
 400         case -1:
 401                 *buf = i2c_8bit_addr_from_msg(pd->msg);
 402                 break;
 403         default:
 404                 *buf = pd->msg->buf[pd->pos];
 405         }
 406 }
 407
 408 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 409 {
 410         unsigned char data;
 411
 412         if (pd->pos == pd->msg->len) {
 413                 /* Send stop if we haven't yet (DMA case) */
 414                 if (pd->send_stop && pd->stop_after_dma)
 415                         i2c_op(pd, OP_TX_STOP, 0);
 416                 return 1;
 417         }
 418
 419         sh_mobile_i2c_get_data(pd, &data);
 420
 421         if (sh_mobile_i2c_is_last_byte(pd))
 422                 i2c_op(pd, OP_TX_STOP_DATA, data);
 423         else if (sh_mobile_i2c_is_first_byte(pd))
 424                 i2c_op(pd, OP_TX_FIRST, data);
 425         else
 426                 i2c_op(pd, OP_TX, data);
 427
 428         pd->pos++;
 429         return 0;
 430 }
 431
 432 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 433 {
 434         unsigned char data;
 435         int real_pos;
 436
 437         do {
 438                 if (pd->pos <= -1) {
 439                         sh_mobile_i2c_get_data(pd, &data);
 440
 441                         if (sh_mobile_i2c_is_first_byte(pd))
 442                                 i2c_op(pd, OP_TX_FIRST, data);
 443                         else
 444                                 i2c_op(pd, OP_TX, data);
 445                         break;
 446                 }
 447
 448                 if (pd->pos == 0) {
 449                         i2c_op(pd, OP_TX_TO_RX, 0);
 450                         break;
 451                 }
 452
 453                 real_pos = pd->pos - 2;
 454
 455                 if (pd->pos == pd->msg->len) {
 456                         if (pd->stop_after_dma) {
 457                                 /* Simulate PIO end condition after DMA transfer */
 458                                 i2c_op(pd, OP_RX_STOP, 0);
 459                                 pd->pos++;
 460                                 break;
 461                         }
 462
 463                         if (real_pos < 0) {
 464                                 i2c_op(pd, OP_RX_STOP, 0);
 465                                 break;
 466                         }
 467                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 468                 } else
 469                         data = i2c_op(pd, OP_RX, 0);
 470
 471                 if (real_pos >= 0)
 472                         pd->msg->buf[real_pos] = data;
 473         } while (0);
 474
 475         pd->pos++;
 476         return pd->pos == (pd->msg->len + 2);
 477 }
 478
 479 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 480 {
 481         struct sh_mobile_i2c_data *pd = dev_id;
 482         unsigned char sr;
 483         int wakeup = 0;
 484
 485         sr = iic_rd(pd, ICSR);
 486         pd->sr |= sr; /* remember state */
 487
 488         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 489                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 490                pd->pos, pd->msg->len);
 491
 492         /* Kick off TxDMA after preface was done */
 493         if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 494                 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 495         else if (sr & (ICSR_AL | ICSR_TACK))
 496                 /* don't interrupt transaction - continue to issue stop */
 497                 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 498         else if (pd->msg->flags & I2C_M_RD)
 499                 wakeup = sh_mobile_i2c_isr_rx(pd);
 500         else
 501                 wakeup = sh_mobile_i2c_isr_tx(pd);
 502
 503         /* Kick off RxDMA after preface was done */
 504         if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 505                 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 506
 507         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 508                 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 509
 510         if (wakeup) {
 511                 pd->sr |= SW_DONE;
 512                 wake_up(&pd->wait);
 513         }
 514
 515         /* defeat write posting to avoid spurious WAIT interrupts */
 516         iic_rd(pd, ICSR);
 517
 518         return IRQ_HANDLED;
 519 }
 520
 521 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 522 {
 523         struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 524                                 ? pd->dma_rx : pd->dma_tx;
 525
 526         dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 527                          pd->msg->len, pd->dma_direction);
 528
 529         pd->dma_direction = DMA_NONE;
 530 }
 531
 532 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 533 {
 534         if (pd->dma_direction == DMA_NONE)
 535                 return;
 536         else if (pd->dma_direction == DMA_FROM_DEVICE)
 537                 dmaengine_terminate_all(pd->dma_rx);
 538         else if (pd->dma_direction == DMA_TO_DEVICE)
 539                 dmaengine_terminate_all(pd->dma_tx);
 540
 541         sh_mobile_i2c_dma_unmap(pd);
 542 }
 543
 544 static void sh_mobile_i2c_dma_callback(void *data)
 545 {
 546         struct sh_mobile_i2c_data *pd = data;
 547
 548         sh_mobile_i2c_dma_unmap(pd);
 549         pd->pos = pd->msg->len;
 550         pd->stop_after_dma = true;
 551
 552         iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 553 }
 554
 555 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 556                                 enum dma_transfer_direction dir, dma_addr_t port_addr)
 557 {
 558         struct dma_chan *chan;
 559         struct dma_slave_config cfg;
 560         char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 561         int ret;
 562
 563         chan = dma_request_slave_channel_reason(dev, chan_name);
 564         if (IS_ERR(chan)) {
 565                 ret = PTR_ERR(chan);
 566                 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
 567                 return chan;
 568         }
 569
 570         memset(&cfg, 0, sizeof(cfg));
 571         cfg.direction = dir;
 572         if (dir == DMA_MEM_TO_DEV) {
 573                 cfg.dst_addr = port_addr;
 574                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 575         } else {
 576                 cfg.src_addr = port_addr;
 577                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 578         }
 579
 580         ret = dmaengine_slave_config(chan, &cfg);
 581         if (ret) {
 582                 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 583                 dma_release_channel(chan);
 584                 return ERR_PTR(ret);
 585         }
 586
 587         dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 588         return chan;
 589 }
 590
 591 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 592 {
 593         bool read = pd->msg->flags & I2C_M_RD;
 594         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 595         struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 596         struct dma_async_tx_descriptor *txdesc;
 597         dma_addr_t dma_addr;
 598         dma_cookie_t cookie;
 599
 600         if (PTR_ERR(chan) == -EPROBE_DEFER) {
 601                 if (read)
 602                         chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 603                                                                            pd->res->start + ICDR);
 604                 else
 605                         chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 606                                                                            pd->res->start + ICDR);
 607         }
 608
 609         if (IS_ERR(chan))
 610                 return;
 611
 612         dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
 613         if (dma_mapping_error(chan->device->dev, dma_addr)) {
 614                 dev_dbg(pd->dev, "dma map failed, using PIO\n");
 615                 return;
 616         }
 617
 618         sg_dma_len(&pd->sg) = pd->msg->len;
 619         sg_dma_address(&pd->sg) = dma_addr;
 620
 621         pd->dma_direction = dir;
 622
 623         txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 624                                          read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 625                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 626         if (!txdesc) {
 627                 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 628                 sh_mobile_i2c_cleanup_dma(pd);
 629                 return;
 630         }
 631
 632         txdesc->callback = sh_mobile_i2c_dma_callback;
 633         txdesc->callback_param = pd;
 634
 635         cookie = dmaengine_submit(txdesc);
 636         if (dma_submit_error(cookie)) {
 637                 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 638                 sh_mobile_i2c_cleanup_dma(pd);
 639                 return;
 640         }
 641
 642         dma_async_issue_pending(chan);
 643 }
 644
 645 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 646                     bool do_init)
 647 {
 648         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 649                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
 650                 return -EOPNOTSUPP;
 651         }
 652
 653         if (do_init) {
 654                 /* Initialize channel registers */
 655                 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 656
 657                 /* Enable channel and configure rx ack */
 658                 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 659
 660                 /* Set the clock */
 661                 iic_wr(pd, ICCL, pd->iccl & 0xff);
 662                 iic_wr(pd, ICCH, pd->icch & 0xff);
 663         }
 664
 665         pd->msg = usr_msg;
 666         pd->pos = -1;
 667         pd->sr = 0;
 668
 669         if (pd->msg->len > 8)
 670                 sh_mobile_i2c_xfer_dma(pd);
 671
 672         /* Enable all interrupts to begin with */
 673         iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 674         return 0;
 675 }
 676
 677 static int poll_dte(struct sh_mobile_i2c_data *pd)
 678 {
 679         int i;
 680
 681         for (i = 1000; i; i--) {
 682                 u_int8_t val = iic_rd(pd, ICSR);
 683
 684                 if (val & ICSR_DTE)
 685                         break;
 686
 687                 if (val & ICSR_TACK)
 688                         return -ENXIO;
 689
 690                 udelay(10);
 691         }
 692
 693         return i ? 0 : -ETIMEDOUT;
 694 }
 695
 696 static int poll_busy(struct sh_mobile_i2c_data *pd)
 697 {
 698         int i;
 699
 700         for (i = 1000; i; i--) {
 701                 u_int8_t val = iic_rd(pd, ICSR);
 702
 703                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 704
 705                 /* the interrupt handler may wake us up before the
 706                  * transfer is finished, so poll the hardware
 707                  * until we're done.
 708                  */
 709                 if (!(val & ICSR_BUSY)) {
 710                         /* handle missing acknowledge and arbitration lost */
 711                         val |= pd->sr;
 712                         if (val & ICSR_TACK)
 713                                 return -ENXIO;
 714                         if (val & ICSR_AL)
 715                                 return -EAGAIN;
 716                         break;
 717                 }
 718
 719                 udelay(10);
 720         }
 721
 722         return i ? 0 : -ETIMEDOUT;
 723 }
 724
 725 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 726                               struct i2c_msg *msgs,
 727                               int num)
 728 {
 729         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 730         struct i2c_msg  *msg;
 731         int err = 0;
 732         int i;
 733         long timeout;
 734
 735         activate_ch(pd);
 736
 737         /* Process all messages */
 738         for (i = 0; i < num; i++) {
 739                 bool do_start = pd->send_stop || !i;
 740                 msg = &msgs[i];
 741                 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 742                 pd->stop_after_dma = false;
 743
 744                 err = start_ch(pd, msg, do_start);
 745                 if (err)
 746                         break;
 747
 748                 if (do_start)
 749                         i2c_op(pd, OP_START, 0);
 750
 751                 /* The interrupt handler takes care of the rest... */
 752                 timeout = wait_event_timeout(pd->wait,
 753                                        pd->sr & (ICSR_TACK | SW_DONE),
 754                                        adapter->timeout);
 755                 if (!timeout) {
 756                         dev_err(pd->dev, "Transfer request timed out\n");
 757                         if (pd->dma_direction != DMA_NONE)
 758                                 sh_mobile_i2c_cleanup_dma(pd);
 759
 760                         err = -ETIMEDOUT;
 761                         break;
 762                 }
 763
 764                 if (pd->send_stop)
 765                         err = poll_busy(pd);
 766                 else
 767                         err = poll_dte(pd);
 768                 if (err < 0)
 769                         break;
 770         }
 771
 772         deactivate_ch(pd);
 773
 774         if (!err)
 775                 err = num;
 776         return err;
 777 }
 778
 779 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 780 {
 781         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 782 }
 783
 784 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
 785         .functionality  = sh_mobile_i2c_func,
 786         .master_xfer    = sh_mobile_i2c_xfer,
 787 };
 788
 789 /*
 790  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 791  * this is work-around for it.
 792  */
 793 static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 794 {
 795         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 796         iic_rd(pd, ICCR); /* dummy read */
 797
 798         iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 799         iic_rd(pd, ICSTART); /* dummy read */
 800
 801         udelay(10);
 802
 803         iic_wr(pd, ICCR, ICCR_SCP);
 804         iic_wr(pd, ICSTART, 0);
 805
 806         udelay(10);
 807
 808         iic_wr(pd, ICCR, ICCR_TRS);
 809         udelay(10);
 810         iic_wr(pd, ICCR, 0);
 811         udelay(10);
 812         iic_wr(pd, ICCR, ICCR_TRS);
 813         udelay(10);
 814 }
 815
 816 static const struct sh_mobile_dt_config default_dt_config = {
 817         .clks_per_count = 1,
 818 };
 819
 820 static const struct sh_mobile_dt_config fast_clock_dt_config = {
 821         .clks_per_count = 2,
 822 };
 823
 824 static const struct sh_mobile_dt_config r8a7740_dt_config = {
 825         .clks_per_count = 1,
 826         .setup = sh_mobile_i2c_r8a7740_workaround,
 827 };
 828
 829 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 830         { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 831         { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 832         { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 833         { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
 834         { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 835         { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 836         { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 837         { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 838         { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
 839         { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 840         {},
 841 };
 842 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 843
 844 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 845 {
 846         if (!IS_ERR(pd->dma_tx)) {
 847                 dma_release_channel(pd->dma_tx);
 848                 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 849         }
 850
 851         if (!IS_ERR(pd->dma_rx)) {
 852                 dma_release_channel(pd->dma_rx);
 853                 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 854         }
 855 }
 856
 857 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 858 {
 859         struct resource *res;
 860         resource_size_t n;
 861         int k = 0, ret;
 862
 863         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 864                 for (n = res->start; n <= res->end; n++) {
 865                         ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 866                                           0, dev_name(&dev->dev), pd);
 867                         if (ret) {
 868                                 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 869                                 return ret;
 870                         }
 871                 }
 872                 k++;
 873         }
 874
 875         return k > 0 ? 0 : -ENOENT;
 876 }
 877
 878 static int sh_mobile_i2c_probe(struct platform_device *dev)
 879 {
 880         struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
 881         struct sh_mobile_i2c_data *pd;
 882         struct i2c_adapter *adap;
 883         struct resource *res;
 884         int ret;
 885         u32 bus_speed;
 886
 887         pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 888         if (!pd)
 889                 return -ENOMEM;
 890
 891         pd->clk = devm_clk_get(&dev->dev, NULL);
 892         if (IS_ERR(pd->clk)) {
 893                 dev_err(&dev->dev, "cannot get clock\n");
 894                 return PTR_ERR(pd->clk);
 895         }
 896
 897         ret = sh_mobile_i2c_hook_irqs(dev, pd);
 898         if (ret)
 899                 return ret;
 900
 901         pd->dev = &dev->dev;
 902         platform_set_drvdata(dev, pd);
 903
 904         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 905
 906         pd->res = res;
 907         pd->reg = devm_ioremap_resource(&dev->dev, res);
 908         if (IS_ERR(pd->reg))
 909                 return PTR_ERR(pd->reg);
 910
 911         /* Use platform data bus speed or STANDARD_MODE */
 912         ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 913         pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
 914
 915         pd->clks_per_count = 1;
 916
 917         if (dev->dev.of_node) {
 918                 const struct of_device_id *match;
 919
 920                 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
 921                 if (match) {
 922                         const struct sh_mobile_dt_config *config;
 923
 924                         config = match->data;
 925                         pd->clks_per_count = config->clks_per_count;
 926
 927                         if (config->setup)
 928                                 config->setup(pd);
 929                 }
 930         } else {
 931                 if (pdata && pdata->bus_speed)
 932                         pd->bus_speed = pdata->bus_speed;
 933                 if (pdata && pdata->clks_per_count)
 934                         pd->clks_per_count = pdata->clks_per_count;
 935         }
 936
 937         /* The IIC blocks on SH-Mobile ARM processors
 938          * come with two new bits in ICIC.
 939          */
 940         if (resource_size(res) > 0x17)
 941                 pd->flags |= IIC_FLAG_HAS_ICIC67;
 942
 943         ret = sh_mobile_i2c_init(pd);
 944         if (ret)
 945                 return ret;
 946
 947         /* Init DMA */
 948         sg_init_table(&pd->sg, 1);
 949         pd->dma_direction = DMA_NONE;
 950         pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 951
 952         /* Enable Runtime PM for this device.
 953          *
 954          * Also tell the Runtime PM core to ignore children
 955          * for this device since it is valid for us to suspend
 956          * this I2C master driver even though the slave devices
 957          * on the I2C bus may not be suspended.
 958          *
 959          * The state of the I2C hardware bus is unaffected by
 960          * the Runtime PM state.
 961          */
 962         pm_suspend_ignore_children(&dev->dev, true);
 963         pm_runtime_enable(&dev->dev);
 964
 965         /* setup the private data */
 966         adap = &pd->adap;
 967         i2c_set_adapdata(adap, pd);
 968
 969         adap->owner = THIS_MODULE;
 970         adap->algo = &sh_mobile_i2c_algorithm;
 971         adap->dev.parent = &dev->dev;
 972         adap->retries = 5;
 973         adap->nr = dev->id;
 974         adap->dev.of_node = dev->dev.of_node;
 975
 976         strlcpy(adap->name, dev->name, sizeof(adap->name));
 977
 978         spin_lock_init(&pd->lock);
 979         init_waitqueue_head(&pd->wait);
 980
 981         ret = i2c_add_numbered_adapter(adap);
 982         if (ret < 0) {
 983                 sh_mobile_i2c_release_dma(pd);
 984                 dev_err(&dev->dev, "cannot add numbered adapter\n");
 985                 return ret;
 986         }
 987
 988         dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 989
 990         return 0;
 991 }
 992
 993 static int sh_mobile_i2c_remove(struct platform_device *dev)
 994 {
 995         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 996
 997         i2c_del_adapter(&pd->adap);
 998         sh_mobile_i2c_release_dma(pd);
 999         pm_runtime_disable(&dev->dev);
1000         return 0;
1001 }
1002
1003 static int sh_mobile_i2c_runtime_nop(struct device *dev)
1004 {
1005         /* Runtime PM callback shared between ->runtime_suspend()
1006          * and ->runtime_resume(). Simply returns success.
1007          *
1008          * This driver re-initializes all registers after
1009          * pm_runtime_get_sync() anyway so there is no need
1010          * to save and restore registers here.
1011          */
1012         return 0;
1013 }
1014
1015 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
1016         .runtime_suspend = sh_mobile_i2c_runtime_nop,
1017         .runtime_resume = sh_mobile_i2c_runtime_nop,
1018 };
1019
1020 static struct platform_driver sh_mobile_i2c_driver = {
1021         .driver         = {
1022                 .name           = "i2c-sh_mobile",
1023                 .pm             = &sh_mobile_i2c_dev_pm_ops,
1024                 .of_match_table = sh_mobile_i2c_dt_ids,
1025         },
1026         .probe          = sh_mobile_i2c_probe,
1027         .remove         = sh_mobile_i2c_remove,
1028 };
1029
1030 static int __init sh_mobile_i2c_adap_init(void)
1031 {
1032         return platform_driver_register(&sh_mobile_i2c_driver);
1033 }
1034 subsys_initcall(sh_mobile_i2c_adap_init);
1035
1036 static void __exit sh_mobile_i2c_adap_exit(void)
1037 {
1038         platform_driver_unregister(&sh_mobile_i2c_driver);
1039 }
1040 module_exit(sh_mobile_i2c_adap_exit);
1041
1042 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
1043 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
1044 MODULE_LICENSE("GPL v2");
1045 MODULE_ALIAS("platform:i2c-sh_mobile");