drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/reset.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/iopoll.h>
  34
  35 #include <asm/unaligned.h>
  36
  37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  38 #define BYTES_PER_FIFO_WORD 4
  39
  40 #define I2C_CNFG                                0x000
  41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  42 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  43 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  44 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  45 #define I2C_STATUS                              0x01C
  46 #define I2C_SL_CNFG                             0x020
  47 #define I2C_SL_CNFG_NACK                        BIT(1)
  48 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  49 #define I2C_SL_ADDR1                            0x02c
  50 #define I2C_SL_ADDR2                            0x030
  51 #define I2C_TX_FIFO                             0x050
  52 #define I2C_RX_FIFO                             0x054
  53 #define I2C_PACKET_TRANSFER_STATUS              0x058
  54 #define I2C_FIFO_CONTROL                        0x05c
  55 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  56 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  59 #define I2C_FIFO_STATUS                         0x060
  60 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  61 #define I2C_FIFO_STATUS_TX_SHIFT                4
  62 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  63 #define I2C_FIFO_STATUS_RX_SHIFT                0
  64 #define I2C_INT_MASK                            0x064
  65 #define I2C_INT_STATUS                          0x068
  66 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       BIT(6)
  68 #define I2C_INT_TX_FIFO_OVERFLOW                BIT(5)
  69 #define I2C_INT_RX_FIFO_UNDERFLOW               BIT(4)
  70 #define I2C_INT_NO_ACK                          BIT(3)
  71 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  72 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  73 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  74 #define I2C_CLK_DIVISOR                         0x06c
  75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  77
  78 #define DVC_CTRL_REG1                           0x000
  79 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  80 #define DVC_CTRL_REG2                           0x004
  81 #define DVC_CTRL_REG3                           0x008
  82 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  84 #define DVC_STATUS                              0x00c
  85 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  86
  87 #define I2C_ERR_NONE                            0x00
  88 #define I2C_ERR_NO_ACK                          0x01
  89 #define I2C_ERR_ARBITRATION_LOST                0x02
  90 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  91
  92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  93 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  94 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  95 #define PACKET_HEADER0_PROTOCOL_I2C             BIT(4)
  96
  97 #define I2C_HEADER_HIGHSPEED_MODE               BIT(22)
  98 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  99 #define I2C_HEADER_SEND_START_BYTE              BIT(20)
 100 #define I2C_HEADER_READ                         BIT(19)
 101 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
 102 #define I2C_HEADER_IE_ENABLE                    BIT(17)
 103 #define I2C_HEADER_REPEAT_START                 BIT(16)
 104 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
 105 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 106 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 107
 108 #define I2C_CONFIG_LOAD                         0x08C
 109 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 110 #define I2C_SLV_CONFIG_LOAD                     BIT(1)
 111 #define I2C_TIMEOUT_CONFIG_LOAD                 BIT(2)
 112
 113 #define I2C_CLKEN_OVERRIDE                      0x090
 114 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 115
 116 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 117
 118 /*
 119  * msg_end_type: The bus control which need to be send at end of transfer.
 120  * @MSG_END_STOP: Send stop pulse at end of transfer.
 121  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 122  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 123  *              stop or repeat start.
 124  */
 125 enum msg_end_type {
 126         MSG_END_STOP,
 127         MSG_END_REPEAT_START,
 128         MSG_END_CONTINUE,
 129 };
 130
 131 /**
 132  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 133  * @has_continue_xfer_support: Continue transfer supports.
 134  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 135  *              complete interrupt per packet basis.
 136  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 137  *              and earlier Socs has two clock sources i.e. div-clk and
 138  *              fast-clk.
 139  * @has_config_load_reg: Has the config load register to load the new
 140  *              configuration.
 141  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 142  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 143  *              applicable if there is no fast clock source i.e. single clock
 144  *              source.
 145  */
 146
 147 struct tegra_i2c_hw_feature {
 148         bool has_continue_xfer_support;
 149         bool has_per_pkt_xfer_complete_irq;
 150         bool has_single_clk_source;
 151         bool has_config_load_reg;
 152         int clk_divisor_hs_mode;
 153         int clk_divisor_std_fast_mode;
 154         u16 clk_divisor_fast_plus_mode;
 155         bool has_multi_master_mode;
 156         bool has_slcg_override_reg;
 157 };
 158
 159 /**
 160  * struct tegra_i2c_dev - per device i2c context
 161  * @dev: device reference for power management
 162  * @hw: Tegra i2c hw feature.
 163  * @adapter: core i2c layer adapter information
 164  * @div_clk: clock reference for div clock of i2c controller.
 165  * @fast_clk: clock reference for fast clock of i2c controller.
 166  * @base: ioremapped registers cookie
 167  * @cont_id: i2c controller id, used for for packet header
 168  * @irq: irq number of transfer complete interrupt
 169  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 170  * @msg_complete: transfer completion notifier
 171  * @msg_err: error code for completed message
 172  * @msg_buf: pointer to current message data
 173  * @msg_buf_remaining: size of unsent data in the message buffer
 174  * @msg_read: identifies read transfers
 175  * @bus_clk_rate: current i2c bus clock rate
 176  * @is_suspended: prevents i2c controller accesses after suspend is called
 177  */
 178 struct tegra_i2c_dev {
 179         struct device *dev;
 180         const struct tegra_i2c_hw_feature *hw;
 181         struct i2c_adapter adapter;
 182         struct clk *div_clk;
 183         struct clk *fast_clk;
 184         struct reset_control *rst;
 185         void __iomem *base;
 186         int cont_id;
 187         int irq;
 188         bool irq_disabled;
 189         int is_dvc;
 190         struct completion msg_complete;
 191         int msg_err;
 192         u8 *msg_buf;
 193         size_t msg_buf_remaining;
 194         int msg_read;
 195         u32 bus_clk_rate;
 196         u16 clk_divisor_non_hs_mode;
 197         bool is_suspended;
 198         bool is_multimaster_mode;
 199 };
 200
 201 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 202                        unsigned long reg)
 203 {
 204         writel(val, i2c_dev->base + reg);
 205 }
 206
 207 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 208 {
 209         return readl(i2c_dev->base + reg);
 210 }
 211
 212 /*
 213  * i2c_writel and i2c_readl will offset the register if necessary to talk
 214  * to the I2C block inside the DVC block
 215  */
 216 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 217         unsigned long reg)
 218 {
 219         if (i2c_dev->is_dvc)
 220                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 221         return reg;
 222 }
 223
 224 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 225         unsigned long reg)
 226 {
 227         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 228
 229         /* Read back register to make sure that register writes completed */
 230         if (reg != I2C_TX_FIFO)
 231                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 232 }
 233
 234 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 235 {
 236         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 237 }
 238
 239 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 240         unsigned long reg, int len)
 241 {
 242         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 243 }
 244
 245 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 246         unsigned long reg, int len)
 247 {
 248         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 249 }
 250
 251 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 252 {
 253         u32 int_mask;
 254
 255         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 256         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 257 }
 258
 259 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 260 {
 261         u32 int_mask;
 262
 263         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 264         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 265 }
 266
 267 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 268 {
 269         unsigned long timeout = jiffies + HZ;
 270         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 271
 272         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 273         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 274
 275         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 276                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 277                 if (time_after(jiffies, timeout)) {
 278                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 279                         return -ETIMEDOUT;
 280                 }
 281                 msleep(1);
 282         }
 283         return 0;
 284 }
 285
 286 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 287 {
 288         u32 val;
 289         int rx_fifo_avail;
 290         u8 *buf = i2c_dev->msg_buf;
 291         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 292         int words_to_transfer;
 293
 294         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 295         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 296                 I2C_FIFO_STATUS_RX_SHIFT;
 297
 298         /* Rounds down to not include partial word at the end of buf */
 299         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 300         if (words_to_transfer > rx_fifo_avail)
 301                 words_to_transfer = rx_fifo_avail;
 302
 303         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 304
 305         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 306         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 307         rx_fifo_avail -= words_to_transfer;
 308
 309         /*
 310          * If there is a partial word at the end of buf, handle it manually to
 311          * prevent overwriting past the end of buf
 312          */
 313         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 314                 BUG_ON(buf_remaining > 3);
 315                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 316                 val = cpu_to_le32(val);
 317                 memcpy(buf, &val, buf_remaining);
 318                 buf_remaining = 0;
 319                 rx_fifo_avail--;
 320         }
 321
 322         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 323         i2c_dev->msg_buf_remaining = buf_remaining;
 324         i2c_dev->msg_buf = buf;
 325         return 0;
 326 }
 327
 328 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 329 {
 330         u32 val;
 331         int tx_fifo_avail;
 332         u8 *buf = i2c_dev->msg_buf;
 333         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 334         int words_to_transfer;
 335
 336         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 337         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 338                 I2C_FIFO_STATUS_TX_SHIFT;
 339
 340         /* Rounds down to not include partial word at the end of buf */
 341         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 342
 343         /* It's very common to have < 4 bytes, so optimize that case. */
 344         if (words_to_transfer) {
 345                 if (words_to_transfer > tx_fifo_avail)
 346                         words_to_transfer = tx_fifo_avail;
 347
 348                 /*
 349                  * Update state before writing to FIFO.  If this casues us
 350                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 351                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 352                  * not maskable).  We need to make sure that the isr sees
 353                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 354                  */
 355                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 356                 tx_fifo_avail -= words_to_transfer;
 357                 i2c_dev->msg_buf_remaining = buf_remaining;
 358                 i2c_dev->msg_buf = buf +
 359                         words_to_transfer * BYTES_PER_FIFO_WORD;
 360                 barrier();
 361
 362                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 363
 364                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 365         }
 366
 367         /*
 368          * If there is a partial word at the end of buf, handle it manually to
 369          * prevent reading past the end of buf, which could cross a page
 370          * boundary and fault.
 371          */
 372         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 373                 BUG_ON(buf_remaining > 3);
 374                 memcpy(&val, buf, buf_remaining);
 375                 val = le32_to_cpu(val);
 376
 377                 /* Again update before writing to FIFO to make sure isr sees. */
 378                 i2c_dev->msg_buf_remaining = 0;
 379                 i2c_dev->msg_buf = NULL;
 380                 barrier();
 381
 382                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 383         }
 384
 385         return 0;
 386 }
 387
 388 /*
 389  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 390  * block.  This block is identical to the rest of the I2C blocks, except that
 391  * it only supports master mode, it has registers moved around, and it needs
 392  * some extra init to get it into I2C mode.  The register moves are handled
 393  * by i2c_readl and i2c_writel
 394  */
 395 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 396 {
 397         u32 val;
 398
 399         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 400         val |= DVC_CTRL_REG3_SW_PROG;
 401         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 402         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 403
 404         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 405         val |= DVC_CTRL_REG1_INTR_EN;
 406         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 407 }
 408
 409 static int tegra_i2c_runtime_resume(struct device *dev)
 410 {
 411         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 412         int ret;
 413
 414         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
 415         if (ret)
 416                 return ret;
 417
 418         if (!i2c_dev->hw->has_single_clk_source) {
 419                 ret = clk_enable(i2c_dev->fast_clk);
 420                 if (ret < 0) {
 421                         dev_err(i2c_dev->dev,
 422                                 "Enabling fast clk failed, err %d\n", ret);
 423                         return ret;
 424                 }
 425         }
 426
 427         ret = clk_enable(i2c_dev->div_clk);
 428         if (ret < 0) {
 429                 dev_err(i2c_dev->dev,
 430                         "Enabling div clk failed, err %d\n", ret);
 431                 clk_disable(i2c_dev->fast_clk);
 432                 return ret;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int tegra_i2c_runtime_suspend(struct device *dev)
 439 {
 440         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 441
 442         clk_disable(i2c_dev->div_clk);
 443         if (!i2c_dev->hw->has_single_clk_source)
 444                 clk_disable(i2c_dev->fast_clk);
 445
 446         return pinctrl_pm_select_idle_state(i2c_dev->dev);
 447 }
 448
 449 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 450 {
 451         u32 val;
 452         int err;
 453         u32 clk_divisor;
 454
 455         err = pm_runtime_get_sync(i2c_dev->dev);
 456         if (err < 0) {
 457                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
 458                 return err;
 459         }
 460
 461         reset_control_assert(i2c_dev->rst);
 462         udelay(2);
 463         reset_control_deassert(i2c_dev->rst);
 464
 465         if (i2c_dev->is_dvc)
 466                 tegra_dvc_init(i2c_dev);
 467
 468         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 469                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 470
 471         if (i2c_dev->hw->has_multi_master_mode)
 472                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 473
 474         i2c_writel(i2c_dev, val, I2C_CNFG);
 475         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 476
 477         /* Make sure clock divisor programmed correctly */
 478         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 479         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 480                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 481         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 482
 483         if (!i2c_dev->is_dvc) {
 484                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 485
 486                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 487                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 488                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 489                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 490         }
 491
 492         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 493                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 494         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 495
 496         err = tegra_i2c_flush_fifos(i2c_dev);
 497         if (err)
 498                 goto err;
 499
 500         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 501                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 502
 503         if (i2c_dev->hw->has_config_load_reg) {
 504                 unsigned long reg_offset;
 505                 void __iomem *addr;
 506
 507                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 508                 addr = i2c_dev->base + reg_offset;
 509                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 510                 err = readl_poll_timeout(addr, val, val == 0, 1000,
 511                                          I2C_CONFIG_LOAD_TIMEOUT);
 512                 if (err) {
 513                         dev_warn(i2c_dev->dev,
 514                                  "timeout waiting for config load\n");
 515                         goto err;
 516                 }
 517         }
 518
 519         if (i2c_dev->irq_disabled) {
 520                 i2c_dev->irq_disabled = 0;
 521                 enable_irq(i2c_dev->irq);
 522         }
 523
 524 err:
 525         pm_runtime_put(i2c_dev->dev);
 526         return err;
 527 }
 528
 529 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 530 {
 531         u32 status;
 532         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 533         struct tegra_i2c_dev *i2c_dev = dev_id;
 534
 535         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 536
 537         if (status == 0) {
 538                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 539                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 540                          i2c_readl(i2c_dev, I2C_STATUS),
 541                          i2c_readl(i2c_dev, I2C_CNFG));
 542                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 543
 544                 if (!i2c_dev->irq_disabled) {
 545                         disable_irq_nosync(i2c_dev->irq);
 546                         i2c_dev->irq_disabled = 1;
 547                 }
 548                 goto err;
 549         }
 550
 551         if (unlikely(status & status_err)) {
 552                 if (status & I2C_INT_NO_ACK)
 553                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 554                 if (status & I2C_INT_ARBITRATION_LOST)
 555                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 556                 goto err;
 557         }
 558
 559         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 560                 if (i2c_dev->msg_buf_remaining)
 561                         tegra_i2c_empty_rx_fifo(i2c_dev);
 562                 else
 563                         BUG();
 564         }
 565
 566         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 567                 if (i2c_dev->msg_buf_remaining)
 568                         tegra_i2c_fill_tx_fifo(i2c_dev);
 569                 else
 570                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 571         }
 572
 573         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 574         if (i2c_dev->is_dvc)
 575                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 576
 577         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 578                 BUG_ON(i2c_dev->msg_buf_remaining);
 579                 complete(&i2c_dev->msg_complete);
 580         }
 581         return IRQ_HANDLED;
 582 err:
 583         /* An error occurred, mask all interrupts */
 584         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 585                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 586                 I2C_INT_RX_FIFO_DATA_REQ);
 587         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 588         if (i2c_dev->is_dvc)
 589                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 590
 591         complete(&i2c_dev->msg_complete);
 592         return IRQ_HANDLED;
 593 }
 594
 595 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 596         struct i2c_msg *msg, enum msg_end_type end_state)
 597 {
 598         u32 packet_header;
 599         u32 int_mask;
 600         unsigned long time_left;
 601
 602         tegra_i2c_flush_fifos(i2c_dev);
 603
 604         if (msg->len == 0)
 605                 return -EINVAL;
 606
 607         i2c_dev->msg_buf = msg->buf;
 608         i2c_dev->msg_buf_remaining = msg->len;
 609         i2c_dev->msg_err = I2C_ERR_NONE;
 610         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 611         reinit_completion(&i2c_dev->msg_complete);
 612
 613         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 614                         PACKET_HEADER0_PROTOCOL_I2C |
 615                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 616                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 617         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 618
 619         packet_header = msg->len - 1;
 620         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 621
 622         packet_header = I2C_HEADER_IE_ENABLE;
 623         if (end_state == MSG_END_CONTINUE)
 624                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 625         else if (end_state == MSG_END_REPEAT_START)
 626                 packet_header |= I2C_HEADER_REPEAT_START;
 627         if (msg->flags & I2C_M_TEN) {
 628                 packet_header |= msg->addr;
 629                 packet_header |= I2C_HEADER_10BIT_ADDR;
 630         } else {
 631                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 632         }
 633         if (msg->flags & I2C_M_IGNORE_NAK)
 634                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 635         if (msg->flags & I2C_M_RD)
 636                 packet_header |= I2C_HEADER_READ;
 637         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 638
 639         if (!(msg->flags & I2C_M_RD))
 640                 tegra_i2c_fill_tx_fifo(i2c_dev);
 641
 642         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 643         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 644                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 645         if (msg->flags & I2C_M_RD)
 646                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 647         else if (i2c_dev->msg_buf_remaining)
 648                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 649         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 650         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 651                 i2c_readl(i2c_dev, I2C_INT_MASK));
 652
 653         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 654                                                 TEGRA_I2C_TIMEOUT);
 655         tegra_i2c_mask_irq(i2c_dev, int_mask);
 656
 657         if (time_left == 0) {
 658                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 659
 660                 tegra_i2c_init(i2c_dev);
 661                 return -ETIMEDOUT;
 662         }
 663
 664         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 665                 time_left, completion_done(&i2c_dev->msg_complete),
 666                 i2c_dev->msg_err);
 667
 668         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 669                 return 0;
 670
 671         /*
 672          * NACK interrupt is generated before the I2C controller generates
 673          * the STOP condition on the bus. So wait for 2 clock periods
 674          * before resetting the controller so that the STOP condition has
 675          * been delivered properly.
 676          */
 677         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 678                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 679
 680         tegra_i2c_init(i2c_dev);
 681         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 682                 if (msg->flags & I2C_M_IGNORE_NAK)
 683                         return 0;
 684                 return -EREMOTEIO;
 685         }
 686
 687         return -EIO;
 688 }
 689
 690 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 691         int num)
 692 {
 693         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 694         int i;
 695         int ret = 0;
 696
 697         if (i2c_dev->is_suspended)
 698                 return -EBUSY;
 699
 700         ret = pm_runtime_get_sync(i2c_dev->dev);
 701         if (ret < 0) {
 702                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
 703                 return ret;
 704         }
 705
 706         for (i = 0; i < num; i++) {
 707                 enum msg_end_type end_type = MSG_END_STOP;
 708
 709                 if (i < (num - 1)) {
 710                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 711                                 end_type = MSG_END_CONTINUE;
 712                         else
 713                                 end_type = MSG_END_REPEAT_START;
 714                 }
 715                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 716                 if (ret)
 717                         break;
 718         }
 719
 720         pm_runtime_put(i2c_dev->dev);
 721
 722         return ret ?: i;
 723 }
 724
 725 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 726 {
 727         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 728         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 729                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 730
 731         if (i2c_dev->hw->has_continue_xfer_support)
 732                 ret |= I2C_FUNC_NOSTART;
 733         return ret;
 734 }
 735
 736 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 737 {
 738         struct device_node *np = i2c_dev->dev->of_node;
 739         int ret;
 740
 741         ret = of_property_read_u32(np, "clock-frequency",
 742                         &i2c_dev->bus_clk_rate);
 743         if (ret)
 744                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 745
 746         i2c_dev->is_multimaster_mode = of_property_read_bool(np,
 747                         "multi-master");
 748 }
 749
 750 static const struct i2c_algorithm tegra_i2c_algo = {
 751         .master_xfer    = tegra_i2c_xfer,
 752         .functionality  = tegra_i2c_func,
 753 };
 754
 755 /* payload size is only 12 bit */
 756 static struct i2c_adapter_quirks tegra_i2c_quirks = {
 757         .max_read_len = 4096,
 758         .max_write_len = 4096,
 759 };
 760
 761 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 762         .has_continue_xfer_support = false,
 763         .has_per_pkt_xfer_complete_irq = false,
 764         .has_single_clk_source = false,
 765         .clk_divisor_hs_mode = 3,
 766         .clk_divisor_std_fast_mode = 0,
 767         .clk_divisor_fast_plus_mode = 0,
 768         .has_config_load_reg = false,
 769         .has_multi_master_mode = false,
 770         .has_slcg_override_reg = false,
 771 };
 772
 773 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 774         .has_continue_xfer_support = true,
 775         .has_per_pkt_xfer_complete_irq = false,
 776         .has_single_clk_source = false,
 777         .clk_divisor_hs_mode = 3,
 778         .clk_divisor_std_fast_mode = 0,
 779         .clk_divisor_fast_plus_mode = 0,
 780         .has_config_load_reg = false,
 781         .has_multi_master_mode = false,
 782         .has_slcg_override_reg = false,
 783 };
 784
 785 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 786         .has_continue_xfer_support = true,
 787         .has_per_pkt_xfer_complete_irq = true,
 788         .has_single_clk_source = true,
 789         .clk_divisor_hs_mode = 1,
 790         .clk_divisor_std_fast_mode = 0x19,
 791         .clk_divisor_fast_plus_mode = 0x10,
 792         .has_config_load_reg = false,
 793         .has_multi_master_mode = false,
 794         .has_slcg_override_reg = false,
 795 };
 796
 797 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 798         .has_continue_xfer_support = true,
 799         .has_per_pkt_xfer_complete_irq = true,
 800         .has_single_clk_source = true,
 801         .clk_divisor_hs_mode = 1,
 802         .clk_divisor_std_fast_mode = 0x19,
 803         .clk_divisor_fast_plus_mode = 0x10,
 804         .has_config_load_reg = true,
 805         .has_multi_master_mode = false,
 806         .has_slcg_override_reg = true,
 807 };
 808
 809 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
 810         .has_continue_xfer_support = true,
 811         .has_per_pkt_xfer_complete_irq = true,
 812         .has_single_clk_source = true,
 813         .clk_divisor_hs_mode = 1,
 814         .clk_divisor_std_fast_mode = 0x19,
 815         .clk_divisor_fast_plus_mode = 0x10,
 816         .has_config_load_reg = true,
 817         .has_multi_master_mode = true,
 818         .has_slcg_override_reg = true,
 819 };
 820
 821 /* Match table for of_platform binding */
 822 static const struct of_device_id tegra_i2c_of_match[] = {
 823         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
 824         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 825         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 826         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 827         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 828         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 829         {},
 830 };
 831 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 832
 833 static int tegra_i2c_probe(struct platform_device *pdev)
 834 {
 835         struct tegra_i2c_dev *i2c_dev;
 836         struct resource *res;
 837         struct clk *div_clk;
 838         struct clk *fast_clk;
 839         void __iomem *base;
 840         int irq;
 841         int ret = 0;
 842         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 843
 844         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 845         base = devm_ioremap_resource(&pdev->dev, res);
 846         if (IS_ERR(base))
 847                 return PTR_ERR(base);
 848
 849         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 850         if (!res) {
 851                 dev_err(&pdev->dev, "no irq resource\n");
 852                 return -EINVAL;
 853         }
 854         irq = res->start;
 855
 856         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 857         if (IS_ERR(div_clk)) {
 858                 dev_err(&pdev->dev, "missing controller clock\n");
 859                 return PTR_ERR(div_clk);
 860         }
 861
 862         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 863         if (!i2c_dev)
 864                 return -ENOMEM;
 865
 866         i2c_dev->base = base;
 867         i2c_dev->div_clk = div_clk;
 868         i2c_dev->adapter.algo = &tegra_i2c_algo;
 869         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 870         i2c_dev->irq = irq;
 871         i2c_dev->cont_id = pdev->id;
 872         i2c_dev->dev = &pdev->dev;
 873
 874         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 875         if (IS_ERR(i2c_dev->rst)) {
 876                 dev_err(&pdev->dev, "missing controller reset\n");
 877                 return PTR_ERR(i2c_dev->rst);
 878         }
 879
 880         tegra_i2c_parse_dt(i2c_dev);
 881
 882         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
 883         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 884                                                   "nvidia,tegra20-i2c-dvc");
 885         init_completion(&i2c_dev->msg_complete);
 886
 887         if (!i2c_dev->hw->has_single_clk_source) {
 888                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 889                 if (IS_ERR(fast_clk)) {
 890                         dev_err(&pdev->dev, "missing fast clock\n");
 891                         return PTR_ERR(fast_clk);
 892                 }
 893                 i2c_dev->fast_clk = fast_clk;
 894         }
 895
 896         platform_set_drvdata(pdev, i2c_dev);
 897
 898         if (!i2c_dev->hw->has_single_clk_source) {
 899                 ret = clk_prepare(i2c_dev->fast_clk);
 900                 if (ret < 0) {
 901                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 902                         return ret;
 903                 }
 904         }
 905
 906         i2c_dev->clk_divisor_non_hs_mode =
 907                         i2c_dev->hw->clk_divisor_std_fast_mode;
 908         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
 909                 (i2c_dev->bus_clk_rate == 1000000))
 910                 i2c_dev->clk_divisor_non_hs_mode =
 911                         i2c_dev->hw->clk_divisor_fast_plus_mode;
 912
 913         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 914         ret = clk_set_rate(i2c_dev->div_clk,
 915                            i2c_dev->bus_clk_rate * clk_multiplier);
 916         if (ret) {
 917                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 918                 goto unprepare_fast_clk;
 919         }
 920
 921         ret = clk_prepare(i2c_dev->div_clk);
 922         if (ret < 0) {
 923                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 924                 goto unprepare_fast_clk;
 925         }
 926
 927         pm_runtime_enable(&pdev->dev);
 928         if (!pm_runtime_enabled(&pdev->dev)) {
 929                 ret = tegra_i2c_runtime_resume(&pdev->dev);
 930                 if (ret < 0) {
 931                         dev_err(&pdev->dev, "runtime resume failed\n");
 932                         goto unprepare_div_clk;
 933                 }
 934         }
 935
 936         if (i2c_dev->is_multimaster_mode) {
 937                 ret = clk_enable(i2c_dev->div_clk);
 938                 if (ret < 0) {
 939                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
 940                                 ret);
 941                         goto disable_rpm;
 942                 }
 943         }
 944
 945         ret = tegra_i2c_init(i2c_dev);
 946         if (ret) {
 947                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
 948                 goto disable_div_clk;
 949         }
 950
 951         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 952                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 953         if (ret) {
 954                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 955                 goto disable_div_clk;
 956         }
 957
 958         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 959         i2c_dev->adapter.owner = THIS_MODULE;
 960         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 961         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
 962                 sizeof(i2c_dev->adapter.name));
 963         i2c_dev->adapter.dev.parent = &pdev->dev;
 964         i2c_dev->adapter.nr = pdev->id;
 965         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 966
 967         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 968         if (ret)
 969                 goto disable_div_clk;
 970
 971         return 0;
 972
 973 disable_div_clk:
 974         if (i2c_dev->is_multimaster_mode)
 975                 clk_disable(i2c_dev->div_clk);
 976
 977 disable_rpm:
 978         pm_runtime_disable(&pdev->dev);
 979         if (!pm_runtime_status_suspended(&pdev->dev))
 980                 tegra_i2c_runtime_suspend(&pdev->dev);
 981
 982 unprepare_div_clk:
 983         clk_unprepare(i2c_dev->div_clk);
 984
 985 unprepare_fast_clk:
 986         if (!i2c_dev->hw->has_single_clk_source)
 987                 clk_unprepare(i2c_dev->fast_clk);
 988
 989         return ret;
 990 }
 991
 992 static int tegra_i2c_remove(struct platform_device *pdev)
 993 {
 994         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 995
 996         i2c_del_adapter(&i2c_dev->adapter);
 997
 998         if (i2c_dev->is_multimaster_mode)
 999                 clk_disable(i2c_dev->div_clk);
1000
1001         pm_runtime_disable(&pdev->dev);
1002         if (!pm_runtime_status_suspended(&pdev->dev))
1003                 tegra_i2c_runtime_suspend(&pdev->dev);
1004
1005         clk_unprepare(i2c_dev->div_clk);
1006         if (!i2c_dev->hw->has_single_clk_source)
1007                 clk_unprepare(i2c_dev->fast_clk);
1008
1009         return 0;
1010 }
1011
1012 #ifdef CONFIG_PM_SLEEP
1013 static int tegra_i2c_suspend(struct device *dev)
1014 {
1015         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1016
1017         i2c_lock_adapter(&i2c_dev->adapter);
1018         i2c_dev->is_suspended = true;
1019         i2c_unlock_adapter(&i2c_dev->adapter);
1020
1021         return 0;
1022 }
1023
1024 static int tegra_i2c_resume(struct device *dev)
1025 {
1026         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1027         int ret;
1028
1029         i2c_lock_adapter(&i2c_dev->adapter);
1030
1031         ret = tegra_i2c_init(i2c_dev);
1032         if (!ret)
1033                 i2c_dev->is_suspended = false;
1034
1035         i2c_unlock_adapter(&i2c_dev->adapter);
1036
1037         return ret;
1038 }
1039
1040 static const struct dev_pm_ops tegra_i2c_pm = {
1041         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1042                            NULL)
1043         SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1044 };
1045 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1046 #else
1047 #define TEGRA_I2C_PM    NULL
1048 #endif
1049
1050 static struct platform_driver tegra_i2c_driver = {
1051         .probe   = tegra_i2c_probe,
1052         .remove  = tegra_i2c_remove,
1053         .driver  = {
1054                 .name  = "tegra-i2c",
1055                 .of_match_table = tegra_i2c_of_match,
1056                 .pm    = TEGRA_I2C_PM,
1057         },
1058 };
1059
1060 static int __init tegra_i2c_init_driver(void)
1061 {
1062         return platform_driver_register(&tegra_i2c_driver);
1063 }
1064
1065 static void __exit tegra_i2c_exit_driver(void)
1066 {
1067         platform_driver_unregister(&tegra_i2c_driver);
1068 }
1069
1070 subsys_initcall(tegra_i2c_init_driver);
1071 module_exit(tegra_i2c_exit_driver);
1072
1073 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1074 MODULE_AUTHOR("Colin Cross");
1075 MODULE_LICENSE("GPL v2");