drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/reset.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/iopoll.h>
  34
  35 #include <asm/unaligned.h>
  36
  37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  38 #define BYTES_PER_FIFO_WORD 4
  39
  40 #define I2C_CNFG                                0x000
  41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  42 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  43 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  44 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  45 #define I2C_STATUS                              0x01C
  46 #define I2C_SL_CNFG                             0x020
  47 #define I2C_SL_CNFG_NACK                        BIT(1)
  48 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  49 #define I2C_SL_ADDR1                            0x02c
  50 #define I2C_SL_ADDR2                            0x030
  51 #define I2C_TX_FIFO                             0x050
  52 #define I2C_RX_FIFO                             0x054
  53 #define I2C_PACKET_TRANSFER_STATUS              0x058
  54 #define I2C_FIFO_CONTROL                        0x05c
  55 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  56 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  59 #define I2C_FIFO_STATUS                         0x060
  60 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  61 #define I2C_FIFO_STATUS_TX_SHIFT                4
  62 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  63 #define I2C_FIFO_STATUS_RX_SHIFT                0
  64 #define I2C_INT_MASK                            0x064
  65 #define I2C_INT_STATUS                          0x068
  66 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       BIT(6)
  68 #define I2C_INT_TX_FIFO_OVERFLOW                BIT(5)
  69 #define I2C_INT_RX_FIFO_UNDERFLOW               BIT(4)
  70 #define I2C_INT_NO_ACK                          BIT(3)
  71 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  72 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  73 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  74 #define I2C_CLK_DIVISOR                         0x06c
  75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  77
  78 #define DVC_CTRL_REG1                           0x000
  79 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  80 #define DVC_CTRL_REG2                           0x004
  81 #define DVC_CTRL_REG3                           0x008
  82 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  84 #define DVC_STATUS                              0x00c
  85 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  86
  87 #define I2C_ERR_NONE                            0x00
  88 #define I2C_ERR_NO_ACK                          0x01
  89 #define I2C_ERR_ARBITRATION_LOST                0x02
  90 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  91
  92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  93 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  94 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  95 #define PACKET_HEADER0_PROTOCOL_I2C             BIT(4)
  96
  97 #define I2C_HEADER_HIGHSPEED_MODE               BIT(22)
  98 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  99 #define I2C_HEADER_SEND_START_BYTE              BIT(20)
 100 #define I2C_HEADER_READ                         BIT(19)
 101 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
 102 #define I2C_HEADER_IE_ENABLE                    BIT(17)
 103 #define I2C_HEADER_REPEAT_START                 BIT(16)
 104 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
 105 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 106 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 107
 108 #define I2C_CONFIG_LOAD                         0x08C
 109 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 110 #define I2C_SLV_CONFIG_LOAD                     BIT(1)
 111 #define I2C_TIMEOUT_CONFIG_LOAD                 BIT(2)
 112
 113 #define I2C_CLKEN_OVERRIDE                      0x090
 114 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 115
 116 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 117
 118 /*
 119  * msg_end_type: The bus control which need to be send at end of transfer.
 120  * @MSG_END_STOP: Send stop pulse at end of transfer.
 121  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 122  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 123  *              stop or repeat start.
 124  */
 125 enum msg_end_type {
 126         MSG_END_STOP,
 127         MSG_END_REPEAT_START,
 128         MSG_END_CONTINUE,
 129 };
 130
 131 /**
 132  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 133  * @has_continue_xfer_support: Continue transfer supports.
 134  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 135  *              complete interrupt per packet basis.
 136  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 137  *              and earlier Socs has two clock sources i.e. div-clk and
 138  *              fast-clk.
 139  * @has_config_load_reg: Has the config load register to load the new
 140  *              configuration.
 141  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 142  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 143  *              applicable if there is no fast clock source i.e. single clock
 144  *              source.
 145  */
 146
 147 struct tegra_i2c_hw_feature {
 148         bool has_continue_xfer_support;
 149         bool has_per_pkt_xfer_complete_irq;
 150         bool has_single_clk_source;
 151         bool has_config_load_reg;
 152         int clk_divisor_hs_mode;
 153         int clk_divisor_std_fast_mode;
 154         u16 clk_divisor_fast_plus_mode;
 155         bool has_multi_master_mode;
 156         bool has_slcg_override_reg;
 157 };
 158
 159 /**
 160  * struct tegra_i2c_dev - per device i2c context
 161  * @dev: device reference for power management
 162  * @hw: Tegra i2c hw feature.
 163  * @adapter: core i2c layer adapter information
 164  * @div_clk: clock reference for div clock of i2c controller.
 165  * @fast_clk: clock reference for fast clock of i2c controller.
 166  * @base: ioremapped registers cookie
 167  * @cont_id: i2c controller id, used for for packet header
 168  * @irq: irq number of transfer complete interrupt
 169  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 170  * @msg_complete: transfer completion notifier
 171  * @msg_err: error code for completed message
 172  * @msg_buf: pointer to current message data
 173  * @msg_buf_remaining: size of unsent data in the message buffer
 174  * @msg_read: identifies read transfers
 175  * @bus_clk_rate: current i2c bus clock rate
 176  * @is_suspended: prevents i2c controller accesses after suspend is called
 177  */
 178 struct tegra_i2c_dev {
 179         struct device *dev;
 180         const struct tegra_i2c_hw_feature *hw;
 181         struct i2c_adapter adapter;
 182         struct clk *div_clk;
 183         struct clk *fast_clk;
 184         struct reset_control *rst;
 185         void __iomem *base;
 186         int cont_id;
 187         int irq;
 188         bool irq_disabled;
 189         int is_dvc;
 190         struct completion msg_complete;
 191         int msg_err;
 192         u8 *msg_buf;
 193         size_t msg_buf_remaining;
 194         int msg_read;
 195         u32 bus_clk_rate;
 196         u16 clk_divisor_non_hs_mode;
 197         bool is_suspended;
 198         bool is_multimaster_mode;
 199 };
 200
 201 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 202                        unsigned long reg)
 203 {
 204         writel(val, i2c_dev->base + reg);
 205 }
 206
 207 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 208 {
 209         return readl(i2c_dev->base + reg);
 210 }
 211
 212 /*
 213  * i2c_writel and i2c_readl will offset the register if necessary to talk
 214  * to the I2C block inside the DVC block
 215  */
 216 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 217         unsigned long reg)
 218 {
 219         if (i2c_dev->is_dvc)
 220                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 221         return reg;
 222 }
 223
 224 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 225         unsigned long reg)
 226 {
 227         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 228
 229         /* Read back register to make sure that register writes completed */
 230         if (reg != I2C_TX_FIFO)
 231                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 232 }
 233
 234 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 235 {
 236         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 237 }
 238
 239 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 240         unsigned long reg, int len)
 241 {
 242         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 243 }
 244
 245 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 246         unsigned long reg, int len)
 247 {
 248         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 249 }
 250
 251 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 252 {
 253         u32 int_mask;
 254
 255         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 256         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 257 }
 258
 259 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 260 {
 261         u32 int_mask;
 262
 263         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 264         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 265 }
 266
 267 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 268 {
 269         unsigned long timeout = jiffies + HZ;
 270         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 271
 272         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 273         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 274
 275         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 276                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 277                 if (time_after(jiffies, timeout)) {
 278                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 279                         return -ETIMEDOUT;
 280                 }
 281                 msleep(1);
 282         }
 283         return 0;
 284 }
 285
 286 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 287 {
 288         u32 val;
 289         int rx_fifo_avail;
 290         u8 *buf = i2c_dev->msg_buf;
 291         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 292         int words_to_transfer;
 293
 294         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 295         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 296                 I2C_FIFO_STATUS_RX_SHIFT;
 297
 298         /* Rounds down to not include partial word at the end of buf */
 299         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 300         if (words_to_transfer > rx_fifo_avail)
 301                 words_to_transfer = rx_fifo_avail;
 302
 303         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 304
 305         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 306         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 307         rx_fifo_avail -= words_to_transfer;
 308
 309         /*
 310          * If there is a partial word at the end of buf, handle it manually to
 311          * prevent overwriting past the end of buf
 312          */
 313         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 314                 BUG_ON(buf_remaining > 3);
 315                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 316                 val = cpu_to_le32(val);
 317                 memcpy(buf, &val, buf_remaining);
 318                 buf_remaining = 0;
 319                 rx_fifo_avail--;
 320         }
 321
 322         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 323         i2c_dev->msg_buf_remaining = buf_remaining;
 324         i2c_dev->msg_buf = buf;
 325         return 0;
 326 }
 327
 328 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 329 {
 330         u32 val;
 331         int tx_fifo_avail;
 332         u8 *buf = i2c_dev->msg_buf;
 333         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 334         int words_to_transfer;
 335
 336         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 337         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 338                 I2C_FIFO_STATUS_TX_SHIFT;
 339
 340         /* Rounds down to not include partial word at the end of buf */
 341         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 342
 343         /* It's very common to have < 4 bytes, so optimize that case. */
 344         if (words_to_transfer) {
 345                 if (words_to_transfer > tx_fifo_avail)
 346                         words_to_transfer = tx_fifo_avail;
 347
 348                 /*
 349                  * Update state before writing to FIFO.  If this casues us
 350                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 351                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 352                  * not maskable).  We need to make sure that the isr sees
 353                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 354                  */
 355                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 356                 tx_fifo_avail -= words_to_transfer;
 357                 i2c_dev->msg_buf_remaining = buf_remaining;
 358                 i2c_dev->msg_buf = buf +
 359                         words_to_transfer * BYTES_PER_FIFO_WORD;
 360                 barrier();
 361
 362                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 363
 364                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 365         }
 366
 367         /*
 368          * If there is a partial word at the end of buf, handle it manually to
 369          * prevent reading past the end of buf, which could cross a page
 370          * boundary and fault.
 371          */
 372         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 373                 BUG_ON(buf_remaining > 3);
 374                 memcpy(&val, buf, buf_remaining);
 375                 val = le32_to_cpu(val);
 376
 377                 /* Again update before writing to FIFO to make sure isr sees. */
 378                 i2c_dev->msg_buf_remaining = 0;
 379                 i2c_dev->msg_buf = NULL;
 380                 barrier();
 381
 382                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 383         }
 384
 385         return 0;
 386 }
 387
 388 /*
 389  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 390  * block.  This block is identical to the rest of the I2C blocks, except that
 391  * it only supports master mode, it has registers moved around, and it needs
 392  * some extra init to get it into I2C mode.  The register moves are handled
 393  * by i2c_readl and i2c_writel
 394  */
 395 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 396 {
 397         u32 val;
 398
 399         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 400         val |= DVC_CTRL_REG3_SW_PROG;
 401         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 402         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 403
 404         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 405         val |= DVC_CTRL_REG1_INTR_EN;
 406         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 407 }
 408
 409 static int tegra_i2c_runtime_resume(struct device *dev)
 410 {
 411         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 412         int ret;
 413
 414         ret = pinctrl_pm_select_default_state(i2c_dev->dev);
 415         if (ret)
 416                 return ret;
 417
 418         if (!i2c_dev->hw->has_single_clk_source) {
 419                 ret = clk_enable(i2c_dev->fast_clk);
 420                 if (ret < 0) {
 421                         dev_err(i2c_dev->dev,
 422                                 "Enabling fast clk failed, err %d\n", ret);
 423                         return ret;
 424                 }
 425         }
 426
 427         ret = clk_enable(i2c_dev->div_clk);
 428         if (ret < 0) {
 429                 dev_err(i2c_dev->dev,
 430                         "Enabling div clk failed, err %d\n", ret);
 431                 clk_disable(i2c_dev->fast_clk);
 432                 return ret;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int tegra_i2c_runtime_suspend(struct device *dev)
 439 {
 440         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 441
 442         clk_disable(i2c_dev->div_clk);
 443         if (!i2c_dev->hw->has_single_clk_source)
 444                 clk_disable(i2c_dev->fast_clk);
 445
 446         return pinctrl_pm_select_idle_state(i2c_dev->dev);
 447 }
 448
 449 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 450 {
 451         unsigned long reg_offset;
 452         void __iomem *addr;
 453         u32 val;
 454         int err;
 455
 456         if (i2c_dev->hw->has_config_load_reg) {
 457                 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
 458                 addr = i2c_dev->base + reg_offset;
 459                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 460                 if (in_interrupt())
 461                         err = readl_poll_timeout_atomic(addr, val, val == 0,
 462                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
 463                 else
 464                         err = readl_poll_timeout(addr, val, val == 0,
 465                                         1000, I2C_CONFIG_LOAD_TIMEOUT);
 466
 467                 if (err) {
 468                         dev_warn(i2c_dev->dev,
 469                                  "timeout waiting for config load\n");
 470                         return err;
 471                 }
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 478 {
 479         u32 val;
 480         int err;
 481         u32 clk_divisor;
 482
 483         err = pm_runtime_get_sync(i2c_dev->dev);
 484         if (err < 0) {
 485                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
 486                 return err;
 487         }
 488
 489         reset_control_assert(i2c_dev->rst);
 490         udelay(2);
 491         reset_control_deassert(i2c_dev->rst);
 492
 493         if (i2c_dev->is_dvc)
 494                 tegra_dvc_init(i2c_dev);
 495
 496         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 497                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 498
 499         if (i2c_dev->hw->has_multi_master_mode)
 500                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 501
 502         i2c_writel(i2c_dev, val, I2C_CNFG);
 503         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 504
 505         /* Make sure clock divisor programmed correctly */
 506         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 507         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 508                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 509         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 510
 511         if (!i2c_dev->is_dvc) {
 512                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 513
 514                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 515                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 516                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 517                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 518         }
 519
 520         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 521                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 522         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 523
 524         err = tegra_i2c_flush_fifos(i2c_dev);
 525         if (err)
 526                 goto err;
 527
 528         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 529                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 530
 531         err = tegra_i2c_wait_for_config_load(i2c_dev);
 532         if (err)
 533                 goto err;
 534
 535         if (i2c_dev->irq_disabled) {
 536                 i2c_dev->irq_disabled = 0;
 537                 enable_irq(i2c_dev->irq);
 538         }
 539
 540 err:
 541         pm_runtime_put(i2c_dev->dev);
 542         return err;
 543 }
 544
 545 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 546 {
 547         u32 status;
 548         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 549         struct tegra_i2c_dev *i2c_dev = dev_id;
 550
 551         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 552
 553         if (status == 0) {
 554                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 555                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 556                          i2c_readl(i2c_dev, I2C_STATUS),
 557                          i2c_readl(i2c_dev, I2C_CNFG));
 558                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 559
 560                 if (!i2c_dev->irq_disabled) {
 561                         disable_irq_nosync(i2c_dev->irq);
 562                         i2c_dev->irq_disabled = 1;
 563                 }
 564                 goto err;
 565         }
 566
 567         if (unlikely(status & status_err)) {
 568                 if (status & I2C_INT_NO_ACK)
 569                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 570                 if (status & I2C_INT_ARBITRATION_LOST)
 571                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 572                 goto err;
 573         }
 574
 575         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 576                 if (i2c_dev->msg_buf_remaining)
 577                         tegra_i2c_empty_rx_fifo(i2c_dev);
 578                 else
 579                         BUG();
 580         }
 581
 582         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 583                 if (i2c_dev->msg_buf_remaining)
 584                         tegra_i2c_fill_tx_fifo(i2c_dev);
 585                 else
 586                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 587         }
 588
 589         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 590         if (i2c_dev->is_dvc)
 591                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 592
 593         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 594                 BUG_ON(i2c_dev->msg_buf_remaining);
 595                 complete(&i2c_dev->msg_complete);
 596         }
 597         return IRQ_HANDLED;
 598 err:
 599         /* An error occurred, mask all interrupts */
 600         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 601                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 602                 I2C_INT_RX_FIFO_DATA_REQ);
 603         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 604         if (i2c_dev->is_dvc)
 605                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 606
 607         complete(&i2c_dev->msg_complete);
 608         return IRQ_HANDLED;
 609 }
 610
 611 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 612         struct i2c_msg *msg, enum msg_end_type end_state)
 613 {
 614         u32 packet_header;
 615         u32 int_mask;
 616         unsigned long time_left;
 617
 618         tegra_i2c_flush_fifos(i2c_dev);
 619
 620         if (msg->len == 0)
 621                 return -EINVAL;
 622
 623         i2c_dev->msg_buf = msg->buf;
 624         i2c_dev->msg_buf_remaining = msg->len;
 625         i2c_dev->msg_err = I2C_ERR_NONE;
 626         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 627         reinit_completion(&i2c_dev->msg_complete);
 628
 629         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 630                         PACKET_HEADER0_PROTOCOL_I2C |
 631                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 632                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 633         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 634
 635         packet_header = msg->len - 1;
 636         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 637
 638         packet_header = I2C_HEADER_IE_ENABLE;
 639         if (end_state == MSG_END_CONTINUE)
 640                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 641         else if (end_state == MSG_END_REPEAT_START)
 642                 packet_header |= I2C_HEADER_REPEAT_START;
 643         if (msg->flags & I2C_M_TEN) {
 644                 packet_header |= msg->addr;
 645                 packet_header |= I2C_HEADER_10BIT_ADDR;
 646         } else {
 647                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 648         }
 649         if (msg->flags & I2C_M_IGNORE_NAK)
 650                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 651         if (msg->flags & I2C_M_RD)
 652                 packet_header |= I2C_HEADER_READ;
 653         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 654
 655         if (!(msg->flags & I2C_M_RD))
 656                 tegra_i2c_fill_tx_fifo(i2c_dev);
 657
 658         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 659         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 660                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 661         if (msg->flags & I2C_M_RD)
 662                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 663         else if (i2c_dev->msg_buf_remaining)
 664                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 665         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 666         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 667                 i2c_readl(i2c_dev, I2C_INT_MASK));
 668
 669         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 670                                                 TEGRA_I2C_TIMEOUT);
 671         tegra_i2c_mask_irq(i2c_dev, int_mask);
 672
 673         if (time_left == 0) {
 674                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 675
 676                 tegra_i2c_init(i2c_dev);
 677                 return -ETIMEDOUT;
 678         }
 679
 680         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 681                 time_left, completion_done(&i2c_dev->msg_complete),
 682                 i2c_dev->msg_err);
 683
 684         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 685                 return 0;
 686
 687         /*
 688          * NACK interrupt is generated before the I2C controller generates
 689          * the STOP condition on the bus. So wait for 2 clock periods
 690          * before resetting the controller so that the STOP condition has
 691          * been delivered properly.
 692          */
 693         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 694                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 695
 696         tegra_i2c_init(i2c_dev);
 697         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 698                 if (msg->flags & I2C_M_IGNORE_NAK)
 699                         return 0;
 700                 return -EREMOTEIO;
 701         }
 702
 703         return -EIO;
 704 }
 705
 706 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 707         int num)
 708 {
 709         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 710         int i;
 711         int ret = 0;
 712
 713         if (i2c_dev->is_suspended)
 714                 return -EBUSY;
 715
 716         ret = pm_runtime_get_sync(i2c_dev->dev);
 717         if (ret < 0) {
 718                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
 719                 return ret;
 720         }
 721
 722         for (i = 0; i < num; i++) {
 723                 enum msg_end_type end_type = MSG_END_STOP;
 724
 725                 if (i < (num - 1)) {
 726                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 727                                 end_type = MSG_END_CONTINUE;
 728                         else
 729                                 end_type = MSG_END_REPEAT_START;
 730                 }
 731                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 732                 if (ret)
 733                         break;
 734         }
 735
 736         pm_runtime_put(i2c_dev->dev);
 737
 738         return ret ?: i;
 739 }
 740
 741 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 742 {
 743         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 744         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 745                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 746
 747         if (i2c_dev->hw->has_continue_xfer_support)
 748                 ret |= I2C_FUNC_NOSTART;
 749         return ret;
 750 }
 751
 752 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 753 {
 754         struct device_node *np = i2c_dev->dev->of_node;
 755         int ret;
 756
 757         ret = of_property_read_u32(np, "clock-frequency",
 758                         &i2c_dev->bus_clk_rate);
 759         if (ret)
 760                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 761
 762         i2c_dev->is_multimaster_mode = of_property_read_bool(np,
 763                         "multi-master");
 764 }
 765
 766 static const struct i2c_algorithm tegra_i2c_algo = {
 767         .master_xfer    = tegra_i2c_xfer,
 768         .functionality  = tegra_i2c_func,
 769 };
 770
 771 /* payload size is only 12 bit */
 772 static struct i2c_adapter_quirks tegra_i2c_quirks = {
 773         .max_read_len = 4096,
 774         .max_write_len = 4096,
 775 };
 776
 777 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 778         .has_continue_xfer_support = false,
 779         .has_per_pkt_xfer_complete_irq = false,
 780         .has_single_clk_source = false,
 781         .clk_divisor_hs_mode = 3,
 782         .clk_divisor_std_fast_mode = 0,
 783         .clk_divisor_fast_plus_mode = 0,
 784         .has_config_load_reg = false,
 785         .has_multi_master_mode = false,
 786         .has_slcg_override_reg = false,
 787 };
 788
 789 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 790         .has_continue_xfer_support = true,
 791         .has_per_pkt_xfer_complete_irq = false,
 792         .has_single_clk_source = false,
 793         .clk_divisor_hs_mode = 3,
 794         .clk_divisor_std_fast_mode = 0,
 795         .clk_divisor_fast_plus_mode = 0,
 796         .has_config_load_reg = false,
 797         .has_multi_master_mode = false,
 798         .has_slcg_override_reg = false,
 799 };
 800
 801 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 802         .has_continue_xfer_support = true,
 803         .has_per_pkt_xfer_complete_irq = true,
 804         .has_single_clk_source = true,
 805         .clk_divisor_hs_mode = 1,
 806         .clk_divisor_std_fast_mode = 0x19,
 807         .clk_divisor_fast_plus_mode = 0x10,
 808         .has_config_load_reg = false,
 809         .has_multi_master_mode = false,
 810         .has_slcg_override_reg = false,
 811 };
 812
 813 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 814         .has_continue_xfer_support = true,
 815         .has_per_pkt_xfer_complete_irq = true,
 816         .has_single_clk_source = true,
 817         .clk_divisor_hs_mode = 1,
 818         .clk_divisor_std_fast_mode = 0x19,
 819         .clk_divisor_fast_plus_mode = 0x10,
 820         .has_config_load_reg = true,
 821         .has_multi_master_mode = false,
 822         .has_slcg_override_reg = true,
 823 };
 824
 825 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
 826         .has_continue_xfer_support = true,
 827         .has_per_pkt_xfer_complete_irq = true,
 828         .has_single_clk_source = true,
 829         .clk_divisor_hs_mode = 1,
 830         .clk_divisor_std_fast_mode = 0x19,
 831         .clk_divisor_fast_plus_mode = 0x10,
 832         .has_config_load_reg = true,
 833         .has_multi_master_mode = true,
 834         .has_slcg_override_reg = true,
 835 };
 836
 837 /* Match table for of_platform binding */
 838 static const struct of_device_id tegra_i2c_of_match[] = {
 839         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
 840         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 841         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 842         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 843         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 844         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 845         {},
 846 };
 847 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 848
 849 static int tegra_i2c_probe(struct platform_device *pdev)
 850 {
 851         struct tegra_i2c_dev *i2c_dev;
 852         struct resource *res;
 853         struct clk *div_clk;
 854         struct clk *fast_clk;
 855         void __iomem *base;
 856         int irq;
 857         int ret = 0;
 858         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 859
 860         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 861         base = devm_ioremap_resource(&pdev->dev, res);
 862         if (IS_ERR(base))
 863                 return PTR_ERR(base);
 864
 865         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 866         if (!res) {
 867                 dev_err(&pdev->dev, "no irq resource\n");
 868                 return -EINVAL;
 869         }
 870         irq = res->start;
 871
 872         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 873         if (IS_ERR(div_clk)) {
 874                 dev_err(&pdev->dev, "missing controller clock\n");
 875                 return PTR_ERR(div_clk);
 876         }
 877
 878         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 879         if (!i2c_dev)
 880                 return -ENOMEM;
 881
 882         i2c_dev->base = base;
 883         i2c_dev->div_clk = div_clk;
 884         i2c_dev->adapter.algo = &tegra_i2c_algo;
 885         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 886         i2c_dev->irq = irq;
 887         i2c_dev->cont_id = pdev->id;
 888         i2c_dev->dev = &pdev->dev;
 889
 890         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 891         if (IS_ERR(i2c_dev->rst)) {
 892                 dev_err(&pdev->dev, "missing controller reset\n");
 893                 return PTR_ERR(i2c_dev->rst);
 894         }
 895
 896         tegra_i2c_parse_dt(i2c_dev);
 897
 898         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
 899         i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 900                                                   "nvidia,tegra20-i2c-dvc");
 901         init_completion(&i2c_dev->msg_complete);
 902
 903         if (!i2c_dev->hw->has_single_clk_source) {
 904                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 905                 if (IS_ERR(fast_clk)) {
 906                         dev_err(&pdev->dev, "missing fast clock\n");
 907                         return PTR_ERR(fast_clk);
 908                 }
 909                 i2c_dev->fast_clk = fast_clk;
 910         }
 911
 912         platform_set_drvdata(pdev, i2c_dev);
 913
 914         if (!i2c_dev->hw->has_single_clk_source) {
 915                 ret = clk_prepare(i2c_dev->fast_clk);
 916                 if (ret < 0) {
 917                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 918                         return ret;
 919                 }
 920         }
 921
 922         i2c_dev->clk_divisor_non_hs_mode =
 923                         i2c_dev->hw->clk_divisor_std_fast_mode;
 924         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
 925                 (i2c_dev->bus_clk_rate == 1000000))
 926                 i2c_dev->clk_divisor_non_hs_mode =
 927                         i2c_dev->hw->clk_divisor_fast_plus_mode;
 928
 929         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 930         ret = clk_set_rate(i2c_dev->div_clk,
 931                            i2c_dev->bus_clk_rate * clk_multiplier);
 932         if (ret) {
 933                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 934                 goto unprepare_fast_clk;
 935         }
 936
 937         ret = clk_prepare(i2c_dev->div_clk);
 938         if (ret < 0) {
 939                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 940                 goto unprepare_fast_clk;
 941         }
 942
 943         pm_runtime_enable(&pdev->dev);
 944         if (!pm_runtime_enabled(&pdev->dev)) {
 945                 ret = tegra_i2c_runtime_resume(&pdev->dev);
 946                 if (ret < 0) {
 947                         dev_err(&pdev->dev, "runtime resume failed\n");
 948                         goto unprepare_div_clk;
 949                 }
 950         }
 951
 952         if (i2c_dev->is_multimaster_mode) {
 953                 ret = clk_enable(i2c_dev->div_clk);
 954                 if (ret < 0) {
 955                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
 956                                 ret);
 957                         goto disable_rpm;
 958                 }
 959         }
 960
 961         ret = tegra_i2c_init(i2c_dev);
 962         if (ret) {
 963                 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
 964                 goto disable_div_clk;
 965         }
 966
 967         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 968                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 969         if (ret) {
 970                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 971                 goto disable_div_clk;
 972         }
 973
 974         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 975         i2c_dev->adapter.owner = THIS_MODULE;
 976         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 977         strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
 978                 sizeof(i2c_dev->adapter.name));
 979         i2c_dev->adapter.dev.parent = &pdev->dev;
 980         i2c_dev->adapter.nr = pdev->id;
 981         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 982
 983         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 984         if (ret)
 985                 goto disable_div_clk;
 986
 987         return 0;
 988
 989 disable_div_clk:
 990         if (i2c_dev->is_multimaster_mode)
 991                 clk_disable(i2c_dev->div_clk);
 992
 993 disable_rpm:
 994         pm_runtime_disable(&pdev->dev);
 995         if (!pm_runtime_status_suspended(&pdev->dev))
 996                 tegra_i2c_runtime_suspend(&pdev->dev);
 997
 998 unprepare_div_clk:
 999         clk_unprepare(i2c_dev->div_clk);
1000
1001 unprepare_fast_clk:
1002         if (!i2c_dev->hw->has_single_clk_source)
1003                 clk_unprepare(i2c_dev->fast_clk);
1004
1005         return ret;
1006 }
1007
1008 static int tegra_i2c_remove(struct platform_device *pdev)
1009 {
1010         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1011
1012         i2c_del_adapter(&i2c_dev->adapter);
1013
1014         if (i2c_dev->is_multimaster_mode)
1015                 clk_disable(i2c_dev->div_clk);
1016
1017         pm_runtime_disable(&pdev->dev);
1018         if (!pm_runtime_status_suspended(&pdev->dev))
1019                 tegra_i2c_runtime_suspend(&pdev->dev);
1020
1021         clk_unprepare(i2c_dev->div_clk);
1022         if (!i2c_dev->hw->has_single_clk_source)
1023                 clk_unprepare(i2c_dev->fast_clk);
1024
1025         return 0;
1026 }
1027
1028 #ifdef CONFIG_PM_SLEEP
1029 static int tegra_i2c_suspend(struct device *dev)
1030 {
1031         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1032
1033         i2c_lock_adapter(&i2c_dev->adapter);
1034         i2c_dev->is_suspended = true;
1035         i2c_unlock_adapter(&i2c_dev->adapter);
1036
1037         return 0;
1038 }
1039
1040 static int tegra_i2c_resume(struct device *dev)
1041 {
1042         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1043         int ret;
1044
1045         i2c_lock_adapter(&i2c_dev->adapter);
1046
1047         ret = tegra_i2c_init(i2c_dev);
1048         if (!ret)
1049                 i2c_dev->is_suspended = false;
1050
1051         i2c_unlock_adapter(&i2c_dev->adapter);
1052
1053         return ret;
1054 }
1055
1056 static const struct dev_pm_ops tegra_i2c_pm = {
1057         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1058                            NULL)
1059         SET_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1060 };
1061 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1062 #else
1063 #define TEGRA_I2C_PM    NULL
1064 #endif
1065
1066 static struct platform_driver tegra_i2c_driver = {
1067         .probe   = tegra_i2c_probe,
1068         .remove  = tegra_i2c_remove,
1069         .driver  = {
1070                 .name  = "tegra-i2c",
1071                 .of_match_table = tegra_i2c_of_match,
1072                 .pm    = TEGRA_I2C_PM,
1073         },
1074 };
1075
1076 static int __init tegra_i2c_init_driver(void)
1077 {
1078         return platform_driver_register(&tegra_i2c_driver);
1079 }
1080
1081 static void __exit tegra_i2c_exit_driver(void)
1082 {
1083         platform_driver_unregister(&tegra_i2c_driver);
1084 }
1085
1086 subsys_initcall(tegra_i2c_init_driver);
1087 module_exit(tegra_i2c_exit_driver);
1088
1089 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1090 MODULE_AUTHOR("Colin Cross");
1091 MODULE_LICENSE("GPL v2");