2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/module.h>
30 #include <linux/reset.h>
32 #include <asm/unaligned.h>
34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
35 #define BYTES_PER_FIFO_WORD 4
37 #define I2C_CNFG 0x000
38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
39 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
40 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
41 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
42 #define I2C_STATUS 0x01C
43 #define I2C_SL_CNFG 0x020
44 #define I2C_SL_CNFG_NACK BIT(1)
45 #define I2C_SL_CNFG_NEWSL BIT(2)
46 #define I2C_SL_ADDR1 0x02c
47 #define I2C_SL_ADDR2 0x030
48 #define I2C_TX_FIFO 0x050
49 #define I2C_RX_FIFO 0x054
50 #define I2C_PACKET_TRANSFER_STATUS 0x058
51 #define I2C_FIFO_CONTROL 0x05c
52 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
53 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
54 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
55 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
56 #define I2C_FIFO_STATUS 0x060
57 #define I2C_FIFO_STATUS_TX_MASK 0xF0
58 #define I2C_FIFO_STATUS_TX_SHIFT 4
59 #define I2C_FIFO_STATUS_RX_MASK 0x0F
60 #define I2C_FIFO_STATUS_RX_SHIFT 0
61 #define I2C_INT_MASK 0x064
62 #define I2C_INT_STATUS 0x068
63 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
64 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6)
65 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5)
66 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4)
67 #define I2C_INT_NO_ACK BIT(3)
68 #define I2C_INT_ARBITRATION_LOST BIT(2)
69 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
70 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
71 #define I2C_CLK_DIVISOR 0x06c
72 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
73 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
75 #define DVC_CTRL_REG1 0x000
76 #define DVC_CTRL_REG1_INTR_EN BIT(10)
77 #define DVC_CTRL_REG2 0x004
78 #define DVC_CTRL_REG3 0x008
79 #define DVC_CTRL_REG3_SW_PROG BIT(26)
80 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
81 #define DVC_STATUS 0x00c
82 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
84 #define I2C_ERR_NONE 0x00
85 #define I2C_ERR_NO_ACK 0x01
86 #define I2C_ERR_ARBITRATION_LOST 0x02
87 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
89 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
90 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
91 #define PACKET_HEADER0_CONT_ID_SHIFT 12
92 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
94 #define I2C_HEADER_HIGHSPEED_MODE BIT(22)
95 #define I2C_HEADER_CONT_ON_NAK BIT(21)
96 #define I2C_HEADER_SEND_START_BYTE BIT(20)
97 #define I2C_HEADER_READ BIT(19)
98 #define I2C_HEADER_10BIT_ADDR BIT(18)
99 #define I2C_HEADER_IE_ENABLE BIT(17)
100 #define I2C_HEADER_REPEAT_START BIT(16)
101 #define I2C_HEADER_CONTINUE_XFER BIT(15)
102 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
103 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
105 #define I2C_CONFIG_LOAD 0x08C
106 #define I2C_MSTR_CONFIG_LOAD BIT(0)
107 #define I2C_SLV_CONFIG_LOAD BIT(1)
108 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2)
110 #define I2C_CLKEN_OVERRIDE 0x090
111 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
114 * msg_end_type: The bus control which need to be send at end of transfer.
115 * @MSG_END_STOP: Send stop pulse at end of transfer.
116 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
117 * @MSG_END_CONTINUE: The following on message is coming and so do not send
118 * stop or repeat start.
122 MSG_END_REPEAT_START,
127 * struct tegra_i2c_hw_feature : Different HW support on Tegra
128 * @has_continue_xfer_support: Continue transfer supports.
129 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
130 * complete interrupt per packet basis.
131 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
132 * and earlier Socs has two clock sources i.e. div-clk and
134 * @has_config_load_reg: Has the config load register to load the new
136 * @clk_divisor_hs_mode: Clock divisor in HS mode.
137 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
138 * applicable if there is no fast clock source i.e. single clock
142 struct tegra_i2c_hw_feature {
143 bool has_continue_xfer_support;
144 bool has_per_pkt_xfer_complete_irq;
145 bool has_single_clk_source;
146 bool has_config_load_reg;
147 int clk_divisor_hs_mode;
148 int clk_divisor_std_fast_mode;
149 u16 clk_divisor_fast_plus_mode;
150 bool has_multi_master_mode;
151 bool has_slcg_override_reg;
155 * struct tegra_i2c_dev - per device i2c context
156 * @dev: device reference for power management
157 * @hw: Tegra i2c hw feature.
158 * @adapter: core i2c layer adapter information
159 * @div_clk: clock reference for div clock of i2c controller.
160 * @fast_clk: clock reference for fast clock of i2c controller.
161 * @base: ioremapped registers cookie
162 * @cont_id: i2c controller id, used for for packet header
163 * @irq: irq number of transfer complete interrupt
164 * @is_dvc: identifies the DVC i2c controller, has a different register layout
165 * @msg_complete: transfer completion notifier
166 * @msg_err: error code for completed message
167 * @msg_buf: pointer to current message data
168 * @msg_buf_remaining: size of unsent data in the message buffer
169 * @msg_read: identifies read transfers
170 * @bus_clk_rate: current i2c bus clock rate
171 * @is_suspended: prevents i2c controller accesses after suspend is called
173 struct tegra_i2c_dev {
175 const struct tegra_i2c_hw_feature *hw;
176 struct i2c_adapter adapter;
178 struct clk *fast_clk;
179 struct reset_control *rst;
185 struct completion msg_complete;
188 size_t msg_buf_remaining;
191 u16 clk_divisor_non_hs_mode;
193 bool is_multimaster_mode;
196 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
199 writel(val, i2c_dev->base + reg);
202 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
204 return readl(i2c_dev->base + reg);
208 * i2c_writel and i2c_readl will offset the register if necessary to talk
209 * to the I2C block inside the DVC block
211 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
215 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
219 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
222 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
224 /* Read back register to make sure that register writes completed */
225 if (reg != I2C_TX_FIFO)
226 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
229 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
231 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
234 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
235 unsigned long reg, int len)
237 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
240 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
241 unsigned long reg, int len)
243 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
246 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
250 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
251 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
254 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
258 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
259 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
262 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
264 unsigned long timeout = jiffies + HZ;
265 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
267 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
268 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
270 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
271 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
272 if (time_after(jiffies, timeout)) {
273 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
281 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
285 u8 *buf = i2c_dev->msg_buf;
286 size_t buf_remaining = i2c_dev->msg_buf_remaining;
287 int words_to_transfer;
289 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
290 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
291 I2C_FIFO_STATUS_RX_SHIFT;
293 /* Rounds down to not include partial word at the end of buf */
294 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
295 if (words_to_transfer > rx_fifo_avail)
296 words_to_transfer = rx_fifo_avail;
298 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
300 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
301 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
302 rx_fifo_avail -= words_to_transfer;
305 * If there is a partial word at the end of buf, handle it manually to
306 * prevent overwriting past the end of buf
308 if (rx_fifo_avail > 0 && buf_remaining > 0) {
309 BUG_ON(buf_remaining > 3);
310 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
311 val = cpu_to_le32(val);
312 memcpy(buf, &val, buf_remaining);
317 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
318 i2c_dev->msg_buf_remaining = buf_remaining;
319 i2c_dev->msg_buf = buf;
323 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
327 u8 *buf = i2c_dev->msg_buf;
328 size_t buf_remaining = i2c_dev->msg_buf_remaining;
329 int words_to_transfer;
331 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
332 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
333 I2C_FIFO_STATUS_TX_SHIFT;
335 /* Rounds down to not include partial word at the end of buf */
336 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
338 /* It's very common to have < 4 bytes, so optimize that case. */
339 if (words_to_transfer) {
340 if (words_to_transfer > tx_fifo_avail)
341 words_to_transfer = tx_fifo_avail;
344 * Update state before writing to FIFO. If this casues us
345 * to finish writing all bytes (AKA buf_remaining goes to 0) we
346 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
347 * not maskable). We need to make sure that the isr sees
348 * buf_remaining as 0 and doesn't call us back re-entrantly.
350 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
351 tx_fifo_avail -= words_to_transfer;
352 i2c_dev->msg_buf_remaining = buf_remaining;
353 i2c_dev->msg_buf = buf +
354 words_to_transfer * BYTES_PER_FIFO_WORD;
357 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
359 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
363 * If there is a partial word at the end of buf, handle it manually to
364 * prevent reading past the end of buf, which could cross a page
365 * boundary and fault.
367 if (tx_fifo_avail > 0 && buf_remaining > 0) {
368 BUG_ON(buf_remaining > 3);
369 memcpy(&val, buf, buf_remaining);
370 val = le32_to_cpu(val);
372 /* Again update before writing to FIFO to make sure isr sees. */
373 i2c_dev->msg_buf_remaining = 0;
374 i2c_dev->msg_buf = NULL;
377 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
384 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
385 * block. This block is identical to the rest of the I2C blocks, except that
386 * it only supports master mode, it has registers moved around, and it needs
387 * some extra init to get it into I2C mode. The register moves are handled
388 * by i2c_readl and i2c_writel
390 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
394 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
395 val |= DVC_CTRL_REG3_SW_PROG;
396 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
397 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
399 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
400 val |= DVC_CTRL_REG1_INTR_EN;
401 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
404 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
408 if (!i2c_dev->hw->has_single_clk_source) {
409 ret = clk_enable(i2c_dev->fast_clk);
411 dev_err(i2c_dev->dev,
412 "Enabling fast clk failed, err %d\n", ret);
416 ret = clk_enable(i2c_dev->div_clk);
418 dev_err(i2c_dev->dev,
419 "Enabling div clk failed, err %d\n", ret);
420 clk_disable(i2c_dev->fast_clk);
425 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
427 clk_disable(i2c_dev->div_clk);
428 if (!i2c_dev->hw->has_single_clk_source)
429 clk_disable(i2c_dev->fast_clk);
432 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
437 unsigned long timeout = jiffies + HZ;
439 err = tegra_i2c_clock_enable(i2c_dev);
441 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
445 reset_control_assert(i2c_dev->rst);
447 reset_control_deassert(i2c_dev->rst);
450 tegra_dvc_init(i2c_dev);
452 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
453 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
455 if (i2c_dev->hw->has_multi_master_mode)
456 val |= I2C_CNFG_MULTI_MASTER_MODE;
458 i2c_writel(i2c_dev, val, I2C_CNFG);
459 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
461 /* Make sure clock divisor programmed correctly */
462 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
463 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
464 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
465 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
467 if (!i2c_dev->is_dvc) {
468 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
470 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
471 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
472 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
473 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
476 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
477 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
478 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
480 if (tegra_i2c_flush_fifos(i2c_dev))
483 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
484 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
486 if (i2c_dev->hw->has_config_load_reg) {
487 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
488 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
489 if (time_after(jiffies, timeout)) {
490 dev_warn(i2c_dev->dev,
491 "timeout waiting for config load\n");
499 if (i2c_dev->irq_disabled) {
500 i2c_dev->irq_disabled = 0;
501 enable_irq(i2c_dev->irq);
505 tegra_i2c_clock_disable(i2c_dev);
509 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
512 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
513 struct tegra_i2c_dev *i2c_dev = dev_id;
515 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
518 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
519 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
520 i2c_readl(i2c_dev, I2C_STATUS),
521 i2c_readl(i2c_dev, I2C_CNFG));
522 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
524 if (!i2c_dev->irq_disabled) {
525 disable_irq_nosync(i2c_dev->irq);
526 i2c_dev->irq_disabled = 1;
531 if (unlikely(status & status_err)) {
532 if (status & I2C_INT_NO_ACK)
533 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
534 if (status & I2C_INT_ARBITRATION_LOST)
535 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
539 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
540 if (i2c_dev->msg_buf_remaining)
541 tegra_i2c_empty_rx_fifo(i2c_dev);
546 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
547 if (i2c_dev->msg_buf_remaining)
548 tegra_i2c_fill_tx_fifo(i2c_dev);
550 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
553 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
555 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
557 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
558 BUG_ON(i2c_dev->msg_buf_remaining);
559 complete(&i2c_dev->msg_complete);
563 /* An error occurred, mask all interrupts */
564 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
565 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
566 I2C_INT_RX_FIFO_DATA_REQ);
567 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
569 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
571 complete(&i2c_dev->msg_complete);
575 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
576 struct i2c_msg *msg, enum msg_end_type end_state)
580 unsigned long time_left;
582 tegra_i2c_flush_fifos(i2c_dev);
587 i2c_dev->msg_buf = msg->buf;
588 i2c_dev->msg_buf_remaining = msg->len;
589 i2c_dev->msg_err = I2C_ERR_NONE;
590 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
591 reinit_completion(&i2c_dev->msg_complete);
593 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
594 PACKET_HEADER0_PROTOCOL_I2C |
595 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
596 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
597 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
599 packet_header = msg->len - 1;
600 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
602 packet_header = I2C_HEADER_IE_ENABLE;
603 if (end_state == MSG_END_CONTINUE)
604 packet_header |= I2C_HEADER_CONTINUE_XFER;
605 else if (end_state == MSG_END_REPEAT_START)
606 packet_header |= I2C_HEADER_REPEAT_START;
607 if (msg->flags & I2C_M_TEN) {
608 packet_header |= msg->addr;
609 packet_header |= I2C_HEADER_10BIT_ADDR;
611 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
613 if (msg->flags & I2C_M_IGNORE_NAK)
614 packet_header |= I2C_HEADER_CONT_ON_NAK;
615 if (msg->flags & I2C_M_RD)
616 packet_header |= I2C_HEADER_READ;
617 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
619 if (!(msg->flags & I2C_M_RD))
620 tegra_i2c_fill_tx_fifo(i2c_dev);
622 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
623 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
624 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
625 if (msg->flags & I2C_M_RD)
626 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
627 else if (i2c_dev->msg_buf_remaining)
628 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
629 tegra_i2c_unmask_irq(i2c_dev, int_mask);
630 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
631 i2c_readl(i2c_dev, I2C_INT_MASK));
633 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
635 tegra_i2c_mask_irq(i2c_dev, int_mask);
637 if (time_left == 0) {
638 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
640 tegra_i2c_init(i2c_dev);
644 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
645 time_left, completion_done(&i2c_dev->msg_complete),
648 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
652 * NACK interrupt is generated before the I2C controller generates
653 * the STOP condition on the bus. So wait for 2 clock periods
654 * before resetting the controller so that the STOP condition has
655 * been delivered properly.
657 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
658 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
660 tegra_i2c_init(i2c_dev);
661 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
662 if (msg->flags & I2C_M_IGNORE_NAK)
670 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
673 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
677 if (i2c_dev->is_suspended)
680 ret = tegra_i2c_clock_enable(i2c_dev);
682 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
686 for (i = 0; i < num; i++) {
687 enum msg_end_type end_type = MSG_END_STOP;
690 if (msgs[i + 1].flags & I2C_M_NOSTART)
691 end_type = MSG_END_CONTINUE;
693 end_type = MSG_END_REPEAT_START;
695 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
699 tegra_i2c_clock_disable(i2c_dev);
703 static u32 tegra_i2c_func(struct i2c_adapter *adap)
705 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
706 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
707 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
709 if (i2c_dev->hw->has_continue_xfer_support)
710 ret |= I2C_FUNC_NOSTART;
714 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
716 struct device_node *np = i2c_dev->dev->of_node;
719 ret = of_property_read_u32(np, "clock-frequency",
720 &i2c_dev->bus_clk_rate);
722 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
724 i2c_dev->is_multimaster_mode = of_property_read_bool(np,
728 static const struct i2c_algorithm tegra_i2c_algo = {
729 .master_xfer = tegra_i2c_xfer,
730 .functionality = tegra_i2c_func,
733 /* payload size is only 12 bit */
734 static struct i2c_adapter_quirks tegra_i2c_quirks = {
735 .max_read_len = 4096,
736 .max_write_len = 4096,
739 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
740 .has_continue_xfer_support = false,
741 .has_per_pkt_xfer_complete_irq = false,
742 .has_single_clk_source = false,
743 .clk_divisor_hs_mode = 3,
744 .clk_divisor_std_fast_mode = 0,
745 .clk_divisor_fast_plus_mode = 0,
746 .has_config_load_reg = false,
747 .has_multi_master_mode = false,
748 .has_slcg_override_reg = false,
751 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
752 .has_continue_xfer_support = true,
753 .has_per_pkt_xfer_complete_irq = false,
754 .has_single_clk_source = false,
755 .clk_divisor_hs_mode = 3,
756 .clk_divisor_std_fast_mode = 0,
757 .clk_divisor_fast_plus_mode = 0,
758 .has_config_load_reg = false,
759 .has_multi_master_mode = false,
760 .has_slcg_override_reg = false,
763 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
764 .has_continue_xfer_support = true,
765 .has_per_pkt_xfer_complete_irq = true,
766 .has_single_clk_source = true,
767 .clk_divisor_hs_mode = 1,
768 .clk_divisor_std_fast_mode = 0x19,
769 .clk_divisor_fast_plus_mode = 0x10,
770 .has_config_load_reg = false,
771 .has_multi_master_mode = false,
772 .has_slcg_override_reg = false,
775 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
776 .has_continue_xfer_support = true,
777 .has_per_pkt_xfer_complete_irq = true,
778 .has_single_clk_source = true,
779 .clk_divisor_hs_mode = 1,
780 .clk_divisor_std_fast_mode = 0x19,
781 .clk_divisor_fast_plus_mode = 0x10,
782 .has_config_load_reg = true,
783 .has_multi_master_mode = false,
784 .has_slcg_override_reg = true,
787 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
788 .has_continue_xfer_support = true,
789 .has_per_pkt_xfer_complete_irq = true,
790 .has_single_clk_source = true,
791 .clk_divisor_hs_mode = 1,
792 .clk_divisor_std_fast_mode = 0x19,
793 .clk_divisor_fast_plus_mode = 0x10,
794 .has_config_load_reg = true,
795 .has_multi_master_mode = true,
796 .has_slcg_override_reg = true,
799 /* Match table for of_platform binding */
800 static const struct of_device_id tegra_i2c_of_match[] = {
801 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
802 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
803 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
804 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
805 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
806 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
809 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
811 static int tegra_i2c_probe(struct platform_device *pdev)
813 struct tegra_i2c_dev *i2c_dev;
814 struct resource *res;
816 struct clk *fast_clk;
820 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
822 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
823 base = devm_ioremap_resource(&pdev->dev, res);
825 return PTR_ERR(base);
827 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
829 dev_err(&pdev->dev, "no irq resource\n");
834 div_clk = devm_clk_get(&pdev->dev, "div-clk");
835 if (IS_ERR(div_clk)) {
836 dev_err(&pdev->dev, "missing controller clock");
837 return PTR_ERR(div_clk);
840 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
844 i2c_dev->base = base;
845 i2c_dev->div_clk = div_clk;
846 i2c_dev->adapter.algo = &tegra_i2c_algo;
847 i2c_dev->adapter.quirks = &tegra_i2c_quirks;
849 i2c_dev->cont_id = pdev->id;
850 i2c_dev->dev = &pdev->dev;
852 i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
853 if (IS_ERR(i2c_dev->rst)) {
854 dev_err(&pdev->dev, "missing controller reset");
855 return PTR_ERR(i2c_dev->rst);
858 tegra_i2c_parse_dt(i2c_dev);
860 i2c_dev->hw = &tegra20_i2c_hw;
862 if (pdev->dev.of_node) {
863 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
864 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
865 "nvidia,tegra20-i2c-dvc");
866 } else if (pdev->id == 3) {
869 init_completion(&i2c_dev->msg_complete);
871 if (!i2c_dev->hw->has_single_clk_source) {
872 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
873 if (IS_ERR(fast_clk)) {
874 dev_err(&pdev->dev, "missing fast clock");
875 return PTR_ERR(fast_clk);
877 i2c_dev->fast_clk = fast_clk;
880 platform_set_drvdata(pdev, i2c_dev);
882 if (!i2c_dev->hw->has_single_clk_source) {
883 ret = clk_prepare(i2c_dev->fast_clk);
885 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
890 i2c_dev->clk_divisor_non_hs_mode =
891 i2c_dev->hw->clk_divisor_std_fast_mode;
892 if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
893 (i2c_dev->bus_clk_rate == 1000000))
894 i2c_dev->clk_divisor_non_hs_mode =
895 i2c_dev->hw->clk_divisor_fast_plus_mode;
897 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
898 ret = clk_set_rate(i2c_dev->div_clk,
899 i2c_dev->bus_clk_rate * clk_multiplier);
901 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
902 goto unprepare_fast_clk;
905 ret = clk_prepare(i2c_dev->div_clk);
907 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
908 goto unprepare_fast_clk;
911 if (i2c_dev->is_multimaster_mode) {
912 ret = clk_enable(i2c_dev->div_clk);
914 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
916 goto unprepare_div_clk;
920 ret = tegra_i2c_init(i2c_dev);
922 dev_err(&pdev->dev, "Failed to initialize i2c controller");
923 goto disable_div_clk;
926 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
927 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
929 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
930 goto disable_div_clk;
933 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
934 i2c_dev->adapter.owner = THIS_MODULE;
935 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
936 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
937 sizeof(i2c_dev->adapter.name));
938 i2c_dev->adapter.dev.parent = &pdev->dev;
939 i2c_dev->adapter.nr = pdev->id;
940 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
942 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
944 goto disable_div_clk;
949 if (i2c_dev->is_multimaster_mode)
950 clk_disable(i2c_dev->div_clk);
953 clk_unprepare(i2c_dev->div_clk);
956 if (!i2c_dev->hw->has_single_clk_source)
957 clk_unprepare(i2c_dev->fast_clk);
962 static int tegra_i2c_remove(struct platform_device *pdev)
964 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
966 i2c_del_adapter(&i2c_dev->adapter);
968 if (i2c_dev->is_multimaster_mode)
969 clk_disable(i2c_dev->div_clk);
971 clk_unprepare(i2c_dev->div_clk);
972 if (!i2c_dev->hw->has_single_clk_source)
973 clk_unprepare(i2c_dev->fast_clk);
978 #ifdef CONFIG_PM_SLEEP
979 static int tegra_i2c_suspend(struct device *dev)
981 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
983 i2c_lock_adapter(&i2c_dev->adapter);
984 i2c_dev->is_suspended = true;
985 i2c_unlock_adapter(&i2c_dev->adapter);
990 static int tegra_i2c_resume(struct device *dev)
992 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
995 i2c_lock_adapter(&i2c_dev->adapter);
997 ret = tegra_i2c_init(i2c_dev);
1000 i2c_unlock_adapter(&i2c_dev->adapter);
1004 i2c_dev->is_suspended = false;
1006 i2c_unlock_adapter(&i2c_dev->adapter);
1011 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
1012 #define TEGRA_I2C_PM (&tegra_i2c_pm)
1014 #define TEGRA_I2C_PM NULL
1017 static struct platform_driver tegra_i2c_driver = {
1018 .probe = tegra_i2c_probe,
1019 .remove = tegra_i2c_remove,
1021 .name = "tegra-i2c",
1022 .of_match_table = tegra_i2c_of_match,
1027 static int __init tegra_i2c_init_driver(void)
1029 return platform_driver_register(&tegra_i2c_driver);
1032 static void __exit tegra_i2c_exit_driver(void)
1034 platform_driver_unregister(&tegra_i2c_driver);
1037 subsys_initcall(tegra_i2c_init_driver);
1038 module_exit(tegra_i2c_exit_driver);
1040 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1041 MODULE_AUTHOR("Colin Cross");
1042 MODULE_LICENSE("GPL v2");