drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/reset.h>
  31
  32 #include <asm/unaligned.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_CNFG_MULTI_MASTER_MODE              (1<<17)
  42 #define I2C_STATUS                              0x01C
  43 #define I2C_SL_CNFG                             0x020
  44 #define I2C_SL_CNFG_NACK                        (1<<1)
  45 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  46 #define I2C_SL_ADDR1                            0x02c
  47 #define I2C_SL_ADDR2                            0x030
  48 #define I2C_TX_FIFO                             0x050
  49 #define I2C_RX_FIFO                             0x054
  50 #define I2C_PACKET_TRANSFER_STATUS              0x058
  51 #define I2C_FIFO_CONTROL                        0x05c
  52 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  53 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  54 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  55 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  56 #define I2C_FIFO_STATUS                         0x060
  57 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  58 #define I2C_FIFO_STATUS_TX_SHIFT                4
  59 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  60 #define I2C_FIFO_STATUS_RX_SHIFT                0
  61 #define I2C_INT_MASK                            0x064
  62 #define I2C_INT_STATUS                          0x068
  63 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  64 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  65 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  66 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  67 #define I2C_INT_NO_ACK                          (1<<3)
  68 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  69 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  70 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  71 #define I2C_CLK_DIVISOR                         0x06c
  72 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  73 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  74
  75 #define DVC_CTRL_REG1                           0x000
  76 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  77 #define DVC_CTRL_REG2                           0x004
  78 #define DVC_CTRL_REG3                           0x008
  79 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  80 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  81 #define DVC_STATUS                              0x00c
  82 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  83
  84 #define I2C_ERR_NONE                            0x00
  85 #define I2C_ERR_NO_ACK                          0x01
  86 #define I2C_ERR_ARBITRATION_LOST                0x02
  87 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  88
  89 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  90 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  91 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  92 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  93
  94 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  95 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  96 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  97 #define I2C_HEADER_READ                         (1<<19)
  98 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  99 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 100 #define I2C_HEADER_REPEAT_START                 (1<<16)
 101 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 102 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 103 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 104
 105 #define I2C_CONFIG_LOAD                         0x08C
 106 #define I2C_MSTR_CONFIG_LOAD                    (1 << 0)
 107 #define I2C_SLV_CONFIG_LOAD                     (1 << 1)
 108 #define I2C_TIMEOUT_CONFIG_LOAD                 (1 << 2)
 109
 110 #define I2C_CLKEN_OVERRIDE                      0x090
 111 #define I2C_MST_CORE_CLKEN_OVR                  (1 << 0)
 112
 113 /*
 114  * msg_end_type: The bus control which need to be send at end of transfer.
 115  * @MSG_END_STOP: Send stop pulse at end of transfer.
 116  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 117  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 118  *              stop or repeat start.
 119  */
 120 enum msg_end_type {
 121         MSG_END_STOP,
 122         MSG_END_REPEAT_START,
 123         MSG_END_CONTINUE,
 124 };
 125
 126 /**
 127  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 128  * @has_continue_xfer_support: Continue transfer supports.
 129  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 130  *              complete interrupt per packet basis.
 131  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 132  *              and earlier Socs has two clock sources i.e. div-clk and
 133  *              fast-clk.
 134  * @has_config_load_reg: Has the config load register to load the new
 135  *              configuration.
 136  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 137  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 138  *              applicable if there is no fast clock source i.e. single clock
 139  *              source.
 140  */
 141
 142 struct tegra_i2c_hw_feature {
 143         bool has_continue_xfer_support;
 144         bool has_per_pkt_xfer_complete_irq;
 145         bool has_single_clk_source;
 146         bool has_config_load_reg;
 147         int clk_divisor_hs_mode;
 148         int clk_divisor_std_fast_mode;
 149         u16 clk_divisor_fast_plus_mode;
 150         bool has_multi_master_mode;
 151         bool has_slcg_override_reg;
 152 };
 153
 154 /**
 155  * struct tegra_i2c_dev - per device i2c context
 156  * @dev: device reference for power management
 157  * @hw: Tegra i2c hw feature.
 158  * @adapter: core i2c layer adapter information
 159  * @div_clk: clock reference for div clock of i2c controller.
 160  * @fast_clk: clock reference for fast clock of i2c controller.
 161  * @base: ioremapped registers cookie
 162  * @cont_id: i2c controller id, used for for packet header
 163  * @irq: irq number of transfer complete interrupt
 164  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 165  * @msg_complete: transfer completion notifier
 166  * @msg_err: error code for completed message
 167  * @msg_buf: pointer to current message data
 168  * @msg_buf_remaining: size of unsent data in the message buffer
 169  * @msg_read: identifies read transfers
 170  * @bus_clk_rate: current i2c bus clock rate
 171  * @is_suspended: prevents i2c controller accesses after suspend is called
 172  */
 173 struct tegra_i2c_dev {
 174         struct device *dev;
 175         const struct tegra_i2c_hw_feature *hw;
 176         struct i2c_adapter adapter;
 177         struct clk *div_clk;
 178         struct clk *fast_clk;
 179         struct reset_control *rst;
 180         void __iomem *base;
 181         int cont_id;
 182         int irq;
 183         bool irq_disabled;
 184         int is_dvc;
 185         struct completion msg_complete;
 186         int msg_err;
 187         u8 *msg_buf;
 188         size_t msg_buf_remaining;
 189         int msg_read;
 190         u32 bus_clk_rate;
 191         u16 clk_divisor_non_hs_mode;
 192         bool is_suspended;
 193         bool is_multimaster_mode;
 194 };
 195
 196 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 197                        unsigned long reg)
 198 {
 199         writel(val, i2c_dev->base + reg);
 200 }
 201
 202 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 203 {
 204         return readl(i2c_dev->base + reg);
 205 }
 206
 207 /*
 208  * i2c_writel and i2c_readl will offset the register if necessary to talk
 209  * to the I2C block inside the DVC block
 210  */
 211 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 212         unsigned long reg)
 213 {
 214         if (i2c_dev->is_dvc)
 215                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 216         return reg;
 217 }
 218
 219 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 220         unsigned long reg)
 221 {
 222         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 223
 224         /* Read back register to make sure that register writes completed */
 225         if (reg != I2C_TX_FIFO)
 226                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 227 }
 228
 229 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 230 {
 231         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 232 }
 233
 234 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 235         unsigned long reg, int len)
 236 {
 237         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 238 }
 239
 240 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 241         unsigned long reg, int len)
 242 {
 243         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 244 }
 245
 246 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 247 {
 248         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 249         int_mask &= ~mask;
 250         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 251 }
 252
 253 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 254 {
 255         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 256         int_mask |= mask;
 257         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 258 }
 259
 260 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 261 {
 262         unsigned long timeout = jiffies + HZ;
 263         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 264         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 265         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 266
 267         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 268                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 269                 if (time_after(jiffies, timeout)) {
 270                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 271                         return -ETIMEDOUT;
 272                 }
 273                 msleep(1);
 274         }
 275         return 0;
 276 }
 277
 278 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 279 {
 280         u32 val;
 281         int rx_fifo_avail;
 282         u8 *buf = i2c_dev->msg_buf;
 283         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 284         int words_to_transfer;
 285
 286         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 287         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 288                 I2C_FIFO_STATUS_RX_SHIFT;
 289
 290         /* Rounds down to not include partial word at the end of buf */
 291         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 292         if (words_to_transfer > rx_fifo_avail)
 293                 words_to_transfer = rx_fifo_avail;
 294
 295         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 296
 297         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 298         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 299         rx_fifo_avail -= words_to_transfer;
 300
 301         /*
 302          * If there is a partial word at the end of buf, handle it manually to
 303          * prevent overwriting past the end of buf
 304          */
 305         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 306                 BUG_ON(buf_remaining > 3);
 307                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 308                 val = cpu_to_le32(val);
 309                 memcpy(buf, &val, buf_remaining);
 310                 buf_remaining = 0;
 311                 rx_fifo_avail--;
 312         }
 313
 314         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 315         i2c_dev->msg_buf_remaining = buf_remaining;
 316         i2c_dev->msg_buf = buf;
 317         return 0;
 318 }
 319
 320 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 321 {
 322         u32 val;
 323         int tx_fifo_avail;
 324         u8 *buf = i2c_dev->msg_buf;
 325         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 326         int words_to_transfer;
 327
 328         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 329         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 330                 I2C_FIFO_STATUS_TX_SHIFT;
 331
 332         /* Rounds down to not include partial word at the end of buf */
 333         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 334
 335         /* It's very common to have < 4 bytes, so optimize that case. */
 336         if (words_to_transfer) {
 337                 if (words_to_transfer > tx_fifo_avail)
 338                         words_to_transfer = tx_fifo_avail;
 339
 340                 /*
 341                  * Update state before writing to FIFO.  If this casues us
 342                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 343                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 344                  * not maskable).  We need to make sure that the isr sees
 345                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 346                  */
 347                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 348                 tx_fifo_avail -= words_to_transfer;
 349                 i2c_dev->msg_buf_remaining = buf_remaining;
 350                 i2c_dev->msg_buf = buf +
 351                         words_to_transfer * BYTES_PER_FIFO_WORD;
 352                 barrier();
 353
 354                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 355
 356                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 357         }
 358
 359         /*
 360          * If there is a partial word at the end of buf, handle it manually to
 361          * prevent reading past the end of buf, which could cross a page
 362          * boundary and fault.
 363          */
 364         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 365                 BUG_ON(buf_remaining > 3);
 366                 memcpy(&val, buf, buf_remaining);
 367                 val = le32_to_cpu(val);
 368
 369                 /* Again update before writing to FIFO to make sure isr sees. */
 370                 i2c_dev->msg_buf_remaining = 0;
 371                 i2c_dev->msg_buf = NULL;
 372                 barrier();
 373
 374                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 375         }
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 382  * block.  This block is identical to the rest of the I2C blocks, except that
 383  * it only supports master mode, it has registers moved around, and it needs
 384  * some extra init to get it into I2C mode.  The register moves are handled
 385  * by i2c_readl and i2c_writel
 386  */
 387 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 388 {
 389         u32 val = 0;
 390         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 391         val |= DVC_CTRL_REG3_SW_PROG;
 392         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 393         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 394
 395         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 396         val |= DVC_CTRL_REG1_INTR_EN;
 397         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 398 }
 399
 400 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 401 {
 402         int ret;
 403         if (!i2c_dev->hw->has_single_clk_source) {
 404                 ret = clk_enable(i2c_dev->fast_clk);
 405                 if (ret < 0) {
 406                         dev_err(i2c_dev->dev,
 407                                 "Enabling fast clk failed, err %d\n", ret);
 408                         return ret;
 409                 }
 410         }
 411         ret = clk_enable(i2c_dev->div_clk);
 412         if (ret < 0) {
 413                 dev_err(i2c_dev->dev,
 414                         "Enabling div clk failed, err %d\n", ret);
 415                 clk_disable(i2c_dev->fast_clk);
 416         }
 417         return ret;
 418 }
 419
 420 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 421 {
 422         clk_disable(i2c_dev->div_clk);
 423         if (!i2c_dev->hw->has_single_clk_source)
 424                 clk_disable(i2c_dev->fast_clk);
 425 }
 426
 427 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 428 {
 429         u32 val;
 430         int err = 0;
 431         u32 clk_divisor;
 432         unsigned long timeout = jiffies + HZ;
 433
 434         err = tegra_i2c_clock_enable(i2c_dev);
 435         if (err < 0) {
 436                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 437                 return err;
 438         }
 439
 440         reset_control_assert(i2c_dev->rst);
 441         udelay(2);
 442         reset_control_deassert(i2c_dev->rst);
 443
 444         if (i2c_dev->is_dvc)
 445                 tegra_dvc_init(i2c_dev);
 446
 447         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 448                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 449
 450         if (i2c_dev->hw->has_multi_master_mode)
 451                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 452
 453         i2c_writel(i2c_dev, val, I2C_CNFG);
 454         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 455
 456         /* Make sure clock divisor programmed correctly */
 457         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 458         clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
 459                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 460         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 461
 462         if (!i2c_dev->is_dvc) {
 463                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 464                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 465                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 466                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 467                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 468
 469         }
 470
 471         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 472                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 473         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 474
 475         if (tegra_i2c_flush_fifos(i2c_dev))
 476                 err = -ETIMEDOUT;
 477
 478         if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 479                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 480
 481         if (i2c_dev->hw->has_config_load_reg) {
 482                 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 483                 while (i2c_readl(i2c_dev, I2C_CONFIG_LOAD) != 0) {
 484                         if (time_after(jiffies, timeout)) {
 485                                 dev_warn(i2c_dev->dev,
 486                                         "timeout waiting for config load\n");
 487                                 err = -ETIMEDOUT;
 488                                 goto err;
 489                         }
 490                         msleep(1);
 491                 }
 492         }
 493
 494         if (i2c_dev->irq_disabled) {
 495                 i2c_dev->irq_disabled = 0;
 496                 enable_irq(i2c_dev->irq);
 497         }
 498
 499 err:
 500         tegra_i2c_clock_disable(i2c_dev);
 501         return err;
 502 }
 503
 504 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 505 {
 506         u32 status;
 507         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 508         struct tegra_i2c_dev *i2c_dev = dev_id;
 509
 510         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 511
 512         if (status == 0) {
 513                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 514                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 515                          i2c_readl(i2c_dev, I2C_STATUS),
 516                          i2c_readl(i2c_dev, I2C_CNFG));
 517                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 518
 519                 if (!i2c_dev->irq_disabled) {
 520                         disable_irq_nosync(i2c_dev->irq);
 521                         i2c_dev->irq_disabled = 1;
 522                 }
 523                 goto err;
 524         }
 525
 526         if (unlikely(status & status_err)) {
 527                 if (status & I2C_INT_NO_ACK)
 528                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 529                 if (status & I2C_INT_ARBITRATION_LOST)
 530                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 531                 goto err;
 532         }
 533
 534         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 535                 if (i2c_dev->msg_buf_remaining)
 536                         tegra_i2c_empty_rx_fifo(i2c_dev);
 537                 else
 538                         BUG();
 539         }
 540
 541         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 542                 if (i2c_dev->msg_buf_remaining)
 543                         tegra_i2c_fill_tx_fifo(i2c_dev);
 544                 else
 545                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 546         }
 547
 548         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 549         if (i2c_dev->is_dvc)
 550                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 551
 552         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 553                 BUG_ON(i2c_dev->msg_buf_remaining);
 554                 complete(&i2c_dev->msg_complete);
 555         }
 556         return IRQ_HANDLED;
 557 err:
 558         /* An error occurred, mask all interrupts */
 559         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 560                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 561                 I2C_INT_RX_FIFO_DATA_REQ);
 562         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 563         if (i2c_dev->is_dvc)
 564                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 565
 566         complete(&i2c_dev->msg_complete);
 567         return IRQ_HANDLED;
 568 }
 569
 570 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 571         struct i2c_msg *msg, enum msg_end_type end_state)
 572 {
 573         u32 packet_header;
 574         u32 int_mask;
 575         unsigned long time_left;
 576
 577         tegra_i2c_flush_fifos(i2c_dev);
 578
 579         if (msg->len == 0)
 580                 return -EINVAL;
 581
 582         i2c_dev->msg_buf = msg->buf;
 583         i2c_dev->msg_buf_remaining = msg->len;
 584         i2c_dev->msg_err = I2C_ERR_NONE;
 585         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 586         reinit_completion(&i2c_dev->msg_complete);
 587
 588         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 589                         PACKET_HEADER0_PROTOCOL_I2C |
 590                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 591                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 592         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 593
 594         packet_header = msg->len - 1;
 595         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 596
 597         packet_header = I2C_HEADER_IE_ENABLE;
 598         if (end_state == MSG_END_CONTINUE)
 599                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 600         else if (end_state == MSG_END_REPEAT_START)
 601                 packet_header |= I2C_HEADER_REPEAT_START;
 602         if (msg->flags & I2C_M_TEN) {
 603                 packet_header |= msg->addr;
 604                 packet_header |= I2C_HEADER_10BIT_ADDR;
 605         } else {
 606                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 607         }
 608         if (msg->flags & I2C_M_IGNORE_NAK)
 609                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 610         if (msg->flags & I2C_M_RD)
 611                 packet_header |= I2C_HEADER_READ;
 612         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 613
 614         if (!(msg->flags & I2C_M_RD))
 615                 tegra_i2c_fill_tx_fifo(i2c_dev);
 616
 617         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 618         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 619                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 620         if (msg->flags & I2C_M_RD)
 621                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 622         else if (i2c_dev->msg_buf_remaining)
 623                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 624         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 625         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 626                 i2c_readl(i2c_dev, I2C_INT_MASK));
 627
 628         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 629                                                 TEGRA_I2C_TIMEOUT);
 630         tegra_i2c_mask_irq(i2c_dev, int_mask);
 631
 632         if (time_left == 0) {
 633                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 634
 635                 tegra_i2c_init(i2c_dev);
 636                 return -ETIMEDOUT;
 637         }
 638
 639         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
 640                 time_left, completion_done(&i2c_dev->msg_complete),
 641                 i2c_dev->msg_err);
 642
 643         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 644                 return 0;
 645
 646         /*
 647          * NACK interrupt is generated before the I2C controller generates
 648          * the STOP condition on the bus. So wait for 2 clock periods
 649          * before resetting the controller so that the STOP condition has
 650          * been delivered properly.
 651          */
 652         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 653                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 654
 655         tegra_i2c_init(i2c_dev);
 656         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 657                 if (msg->flags & I2C_M_IGNORE_NAK)
 658                         return 0;
 659                 return -EREMOTEIO;
 660         }
 661
 662         return -EIO;
 663 }
 664
 665 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 666         int num)
 667 {
 668         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 669         int i;
 670         int ret = 0;
 671
 672         if (i2c_dev->is_suspended)
 673                 return -EBUSY;
 674
 675         ret = tegra_i2c_clock_enable(i2c_dev);
 676         if (ret < 0) {
 677                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
 678                 return ret;
 679         }
 680
 681         for (i = 0; i < num; i++) {
 682                 enum msg_end_type end_type = MSG_END_STOP;
 683                 if (i < (num - 1)) {
 684                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 685                                 end_type = MSG_END_CONTINUE;
 686                         else
 687                                 end_type = MSG_END_REPEAT_START;
 688                 }
 689                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 690                 if (ret)
 691                         break;
 692         }
 693         tegra_i2c_clock_disable(i2c_dev);
 694         return ret ?: i;
 695 }
 696
 697 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 698 {
 699         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 700         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 701                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
 702
 703         if (i2c_dev->hw->has_continue_xfer_support)
 704                 ret |= I2C_FUNC_NOSTART;
 705         return ret;
 706 }
 707
 708 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 709 {
 710         struct device_node *np = i2c_dev->dev->of_node;
 711         int ret;
 712
 713         ret = of_property_read_u32(np, "clock-frequency",
 714                         &i2c_dev->bus_clk_rate);
 715         if (ret)
 716                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 717
 718         i2c_dev->is_multimaster_mode = of_property_read_bool(np,
 719                         "multi-master");
 720 }
 721
 722 static const struct i2c_algorithm tegra_i2c_algo = {
 723         .master_xfer    = tegra_i2c_xfer,
 724         .functionality  = tegra_i2c_func,
 725 };
 726
 727 /* payload size is only 12 bit */
 728 static struct i2c_adapter_quirks tegra_i2c_quirks = {
 729         .max_read_len = 4096,
 730         .max_write_len = 4096,
 731 };
 732
 733 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 734         .has_continue_xfer_support = false,
 735         .has_per_pkt_xfer_complete_irq = false,
 736         .has_single_clk_source = false,
 737         .clk_divisor_hs_mode = 3,
 738         .clk_divisor_std_fast_mode = 0,
 739         .clk_divisor_fast_plus_mode = 0,
 740         .has_config_load_reg = false,
 741         .has_multi_master_mode = false,
 742         .has_slcg_override_reg = false,
 743 };
 744
 745 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 746         .has_continue_xfer_support = true,
 747         .has_per_pkt_xfer_complete_irq = false,
 748         .has_single_clk_source = false,
 749         .clk_divisor_hs_mode = 3,
 750         .clk_divisor_std_fast_mode = 0,
 751         .clk_divisor_fast_plus_mode = 0,
 752         .has_config_load_reg = false,
 753         .has_multi_master_mode = false,
 754         .has_slcg_override_reg = false,
 755 };
 756
 757 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 758         .has_continue_xfer_support = true,
 759         .has_per_pkt_xfer_complete_irq = true,
 760         .has_single_clk_source = true,
 761         .clk_divisor_hs_mode = 1,
 762         .clk_divisor_std_fast_mode = 0x19,
 763         .clk_divisor_fast_plus_mode = 0x10,
 764         .has_config_load_reg = false,
 765         .has_multi_master_mode = false,
 766         .has_slcg_override_reg = false,
 767 };
 768
 769 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
 770         .has_continue_xfer_support = true,
 771         .has_per_pkt_xfer_complete_irq = true,
 772         .has_single_clk_source = true,
 773         .clk_divisor_hs_mode = 1,
 774         .clk_divisor_std_fast_mode = 0x19,
 775         .clk_divisor_fast_plus_mode = 0x10,
 776         .has_config_load_reg = true,
 777         .has_multi_master_mode = false,
 778         .has_slcg_override_reg = true,
 779 };
 780
 781 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
 782         .has_continue_xfer_support = true,
 783         .has_per_pkt_xfer_complete_irq = true,
 784         .has_single_clk_source = true,
 785         .clk_divisor_hs_mode = 1,
 786         .clk_divisor_std_fast_mode = 0x19,
 787         .clk_divisor_fast_plus_mode = 0x10,
 788         .has_config_load_reg = true,
 789         .has_multi_master_mode = true,
 790         .has_slcg_override_reg = true,
 791 };
 792
 793 /* Match table for of_platform binding */
 794 static const struct of_device_id tegra_i2c_of_match[] = {
 795         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
 796         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
 797         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 798         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 799         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 800         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 801         {},
 802 };
 803 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 804
 805 static int tegra_i2c_probe(struct platform_device *pdev)
 806 {
 807         struct tegra_i2c_dev *i2c_dev;
 808         struct resource *res;
 809         struct clk *div_clk;
 810         struct clk *fast_clk;
 811         void __iomem *base;
 812         int irq;
 813         int ret = 0;
 814         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 815
 816         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 817         base = devm_ioremap_resource(&pdev->dev, res);
 818         if (IS_ERR(base))
 819                 return PTR_ERR(base);
 820
 821         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 822         if (!res) {
 823                 dev_err(&pdev->dev, "no irq resource\n");
 824                 return -EINVAL;
 825         }
 826         irq = res->start;
 827
 828         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 829         if (IS_ERR(div_clk)) {
 830                 dev_err(&pdev->dev, "missing controller clock");
 831                 return PTR_ERR(div_clk);
 832         }
 833
 834         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 835         if (!i2c_dev)
 836                 return -ENOMEM;
 837
 838         i2c_dev->base = base;
 839         i2c_dev->div_clk = div_clk;
 840         i2c_dev->adapter.algo = &tegra_i2c_algo;
 841         i2c_dev->adapter.quirks = &tegra_i2c_quirks;
 842         i2c_dev->irq = irq;
 843         i2c_dev->cont_id = pdev->id;
 844         i2c_dev->dev = &pdev->dev;
 845
 846         i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
 847         if (IS_ERR(i2c_dev->rst)) {
 848                 dev_err(&pdev->dev, "missing controller reset");
 849                 return PTR_ERR(i2c_dev->rst);
 850         }
 851
 852         tegra_i2c_parse_dt(i2c_dev);
 853
 854         i2c_dev->hw = &tegra20_i2c_hw;
 855
 856         if (pdev->dev.of_node) {
 857                 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
 858                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 859                                                 "nvidia,tegra20-i2c-dvc");
 860         } else if (pdev->id == 3) {
 861                 i2c_dev->is_dvc = 1;
 862         }
 863         init_completion(&i2c_dev->msg_complete);
 864
 865         if (!i2c_dev->hw->has_single_clk_source) {
 866                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 867                 if (IS_ERR(fast_clk)) {
 868                         dev_err(&pdev->dev, "missing fast clock");
 869                         return PTR_ERR(fast_clk);
 870                 }
 871                 i2c_dev->fast_clk = fast_clk;
 872         }
 873
 874         platform_set_drvdata(pdev, i2c_dev);
 875
 876         if (!i2c_dev->hw->has_single_clk_source) {
 877                 ret = clk_prepare(i2c_dev->fast_clk);
 878                 if (ret < 0) {
 879                         dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 880                         return ret;
 881                 }
 882         }
 883
 884         i2c_dev->clk_divisor_non_hs_mode =
 885                         i2c_dev->hw->clk_divisor_std_fast_mode;
 886         if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
 887                 (i2c_dev->bus_clk_rate == 1000000))
 888                 i2c_dev->clk_divisor_non_hs_mode =
 889                         i2c_dev->hw->clk_divisor_fast_plus_mode;
 890
 891         clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
 892         ret = clk_set_rate(i2c_dev->div_clk,
 893                            i2c_dev->bus_clk_rate * clk_multiplier);
 894         if (ret) {
 895                 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
 896                 goto unprepare_fast_clk;
 897         }
 898
 899         ret = clk_prepare(i2c_dev->div_clk);
 900         if (ret < 0) {
 901                 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
 902                 goto unprepare_fast_clk;
 903         }
 904
 905         if (i2c_dev->is_multimaster_mode) {
 906                 ret = clk_enable(i2c_dev->div_clk);
 907                 if (ret < 0) {
 908                         dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
 909                                 ret);
 910                         goto unprepare_div_clk;
 911                 }
 912         }
 913
 914         ret = tegra_i2c_init(i2c_dev);
 915         if (ret) {
 916                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 917                 goto disable_div_clk;
 918         }
 919
 920         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 921                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 922         if (ret) {
 923                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 924                 goto disable_div_clk;
 925         }
 926
 927         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 928         i2c_dev->adapter.owner = THIS_MODULE;
 929         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
 930         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 931                 sizeof(i2c_dev->adapter.name));
 932         i2c_dev->adapter.dev.parent = &pdev->dev;
 933         i2c_dev->adapter.nr = pdev->id;
 934         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 935
 936         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 937         if (ret)
 938                 goto disable_div_clk;
 939
 940         return 0;
 941
 942 disable_div_clk:
 943         if (i2c_dev->is_multimaster_mode)
 944                 clk_disable(i2c_dev->div_clk);
 945
 946 unprepare_div_clk:
 947         clk_unprepare(i2c_dev->div_clk);
 948
 949 unprepare_fast_clk:
 950         if (!i2c_dev->hw->has_single_clk_source)
 951                 clk_unprepare(i2c_dev->fast_clk);
 952
 953         return ret;
 954 }
 955
 956 static int tegra_i2c_remove(struct platform_device *pdev)
 957 {
 958         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 959         i2c_del_adapter(&i2c_dev->adapter);
 960
 961         if (i2c_dev->is_multimaster_mode)
 962                 clk_disable(i2c_dev->div_clk);
 963
 964         clk_unprepare(i2c_dev->div_clk);
 965         if (!i2c_dev->hw->has_single_clk_source)
 966                 clk_unprepare(i2c_dev->fast_clk);
 967
 968         return 0;
 969 }
 970
 971 #ifdef CONFIG_PM_SLEEP
 972 static int tegra_i2c_suspend(struct device *dev)
 973 {
 974         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 975
 976         i2c_lock_adapter(&i2c_dev->adapter);
 977         i2c_dev->is_suspended = true;
 978         i2c_unlock_adapter(&i2c_dev->adapter);
 979
 980         return 0;
 981 }
 982
 983 static int tegra_i2c_resume(struct device *dev)
 984 {
 985         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 986         int ret;
 987
 988         i2c_lock_adapter(&i2c_dev->adapter);
 989
 990         ret = tegra_i2c_init(i2c_dev);
 991
 992         if (ret) {
 993                 i2c_unlock_adapter(&i2c_dev->adapter);
 994                 return ret;
 995         }
 996
 997         i2c_dev->is_suspended = false;
 998
 999         i2c_unlock_adapter(&i2c_dev->adapter);
1000
1001         return 0;
1002 }
1003
1004 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
1005 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
1006 #else
1007 #define TEGRA_I2C_PM    NULL
1008 #endif
1009
1010 static struct platform_driver tegra_i2c_driver = {
1011         .probe   = tegra_i2c_probe,
1012         .remove  = tegra_i2c_remove,
1013         .driver  = {
1014                 .name  = "tegra-i2c",
1015                 .of_match_table = tegra_i2c_of_match,
1016                 .pm    = TEGRA_I2C_PM,
1017         },
1018 };
1019
1020 static int __init tegra_i2c_init_driver(void)
1021 {
1022         return platform_driver_register(&tegra_i2c_driver);
1023 }
1024
1025 static void __exit tegra_i2c_exit_driver(void)
1026 {
1027         platform_driver_unregister(&tegra_i2c_driver);
1028 }
1029
1030 subsys_initcall(tegra_i2c_init_driver);
1031 module_exit(tegra_i2c_exit_driver);
1032
1033 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1034 MODULE_AUTHOR("Colin Cross");
1035 MODULE_LICENSE("GPL v2");