drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.11    March 27, 2002
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  *
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 struct chipset_bus_clock_list_entry {
  20         u8 xfer_speed;
  21         u8 chipset_settings;
  22         u8 ultra_settings;
  23 };
  24
  25 static struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  26         {       XFER_UDMA_6,    0x31,   0x07    },
  27         {       XFER_UDMA_5,    0x31,   0x06    },
  28         {       XFER_UDMA_4,    0x31,   0x05    },
  29         {       XFER_UDMA_3,    0x31,   0x04    },
  30         {       XFER_UDMA_2,    0x31,   0x03    },
  31         {       XFER_UDMA_1,    0x31,   0x02    },
  32         {       XFER_UDMA_0,    0x31,   0x01    },
  33
  34         {       XFER_MW_DMA_2,  0x31,   0x00    },
  35         {       XFER_MW_DMA_1,  0x31,   0x00    },
  36         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  37         {       XFER_PIO_4,     0x31,   0x00    },
  38         {       XFER_PIO_3,     0x33,   0x00    },
  39         {       XFER_PIO_2,     0x08,   0x00    },
  40         {       XFER_PIO_1,     0x0a,   0x00    },
  41         {       XFER_PIO_0,     0x00,   0x00    },
  42         {       0,              0x00,   0x00    }
  43 };
  44
  45 static struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  46         {       XFER_UDMA_6,    0x41,   0x06    },
  47         {       XFER_UDMA_5,    0x41,   0x05    },
  48         {       XFER_UDMA_4,    0x41,   0x04    },
  49         {       XFER_UDMA_3,    0x41,   0x03    },
  50         {       XFER_UDMA_2,    0x41,   0x02    },
  51         {       XFER_UDMA_1,    0x41,   0x01    },
  52         {       XFER_UDMA_0,    0x41,   0x01    },
  53
  54         {       XFER_MW_DMA_2,  0x41,   0x00    },
  55         {       XFER_MW_DMA_1,  0x42,   0x00    },
  56         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  57         {       XFER_PIO_4,     0x41,   0x00    },
  58         {       XFER_PIO_3,     0x43,   0x00    },
  59         {       XFER_PIO_2,     0x78,   0x00    },
  60         {       XFER_PIO_1,     0x7a,   0x00    },
  61         {       XFER_PIO_0,     0x70,   0x00    },
  62         {       0,              0x00,   0x00    }
  63 };
  64
  65 #define BUSCLOCK(D)     \
  66         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  67
  68 #if 0
  69                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
  70                         (void) pci_read_config_byte(dev, 0x54, &art);
  71                         p += sprintf(p, "DMA Mode:       %s(%s)",
  72                                 (c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
  73                                 (art&0x02)?"2":(art&0x01)?"1":"0");
  74                         p += sprintf(p, "          %s(%s)",
  75                                 (c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
  76                                 (art&0x08)?"2":(art&0x04)?"1":"0");
  77                         p += sprintf(p, "         %s(%s)",
  78                                 (c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
  79                                 (art&0x20)?"2":(art&0x10)?"1":"0");
  80                         p += sprintf(p, "           %s(%s)\n",
  81                                 (c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
  82                                 (art&0x80)?"2":(art&0x40)?"1":"0");
  83                 } else {
  84 #endif
  85
  86 /*
  87  * TO DO: active tuning and correction of cards without a bios.
  88  */
  89 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  90 {
  91         for ( ; chipset_table->xfer_speed ; chipset_table++)
  92                 if (chipset_table->xfer_speed == speed) {
  93                         return chipset_table->chipset_settings;
  94                 }
  95         return chipset_table->chipset_settings;
  96 }
  97
  98 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  99 {
 100         for ( ; chipset_table->xfer_speed ; chipset_table++)
 101                 if (chipset_table->xfer_speed == speed) {
 102                         return chipset_table->ultra_settings;
 103                 }
 104         return chipset_table->ultra_settings;
 105 }
 106
 107 static u8 aec62xx_ratemask (ide_drive_t *drive)
 108 {
 109         ide_hwif_t *hwif        = HWIF(drive);
 110         u8 mode;
 111
 112         switch(hwif->pci_dev->device) {
 113                 case PCI_DEVICE_ID_ARTOP_ATP865:
 114                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 115 #if 0
 116                         mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
 117 #else
 118                         mode = (hwif->INB(((hwif->channel) ?
 119                                         hwif->mate->dma_status :
 120                                         hwif->dma_status)) & 0x10) ? 4 : 3;
 121 #endif
 122                         break;
 123                 case PCI_DEVICE_ID_ARTOP_ATP860:
 124                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 125                         mode = 2;
 126                         break;
 127                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 128                 default:
 129                         return 1;
 130         }
 131
 132         if (!eighty_ninty_three(drive))
 133                 mode = min(mode, (u8)1);
 134         return mode;
 135 }
 136
 137 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 138 {
 139         ide_hwif_t *hwif        = HWIF(drive);
 140         struct pci_dev *dev     = hwif->pci_dev;
 141         u16 d_conf              = 0;
 142         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 143         u8 ultra = 0, ultra_conf = 0;
 144         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
 145         unsigned long flags;
 146
 147         local_irq_save(flags);
 148         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 149         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 150         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 151         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 152         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 153
 154         tmp1 = 0x00;
 155         tmp2 = 0x00;
 156         pci_read_config_byte(dev, 0x54, &ultra);
 157         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 158         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 159         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 160         pci_write_config_byte(dev, 0x54, tmp2);
 161         local_irq_restore(flags);
 162         return(ide_config_drive_speed(drive, speed));
 163 }
 164
 165 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 166 {
 167         ide_hwif_t *hwif        = HWIF(drive);
 168         struct pci_dev *dev     = hwif->pci_dev;
 169         u8 speed        = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
 170         u8 unit         = (drive->select.b.unit & 0x01);
 171         u8 tmp1 = 0, tmp2 = 0;
 172         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176         /* high 4-bits: Active, low 4-bits: Recovery */
 177         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 178         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 179         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 180
 181         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 182         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 183         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 184         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 185         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 186         local_irq_restore(flags);
 187         return(ide_config_drive_speed(drive, speed));
 188 }
 189
 190 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
 191 {
 192         switch (HWIF(drive)->pci_dev->device) {
 193                 case PCI_DEVICE_ID_ARTOP_ATP865:
 194                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 195                 case PCI_DEVICE_ID_ARTOP_ATP860:
 196                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 197                         return ((int) aec6260_tune_chipset(drive, speed));
 198                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 199                         return ((int) aec6210_tune_chipset(drive, speed));
 200                 default:
 201                         return -1;
 202         }
 203 }
 204
 205 static int config_chipset_for_dma (ide_drive_t *drive)
 206 {
 207         u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
 208
 209         if (!(speed))
 210                 return 0;
 211
 212         (void) aec62xx_tune_chipset(drive, speed);
 213         return ide_dma_enable(drive);
 214 }
 215
 216 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
 217 {
 218         u8 speed = 0;
 219         u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 220
 221         switch(pio) {
 222                 case 5:         speed = new_pio; break;
 223                 case 4:         speed = XFER_PIO_4; break;
 224                 case 3:         speed = XFER_PIO_3; break;
 225                 case 2:         speed = XFER_PIO_2; break;
 226                 case 1:         speed = XFER_PIO_1; break;
 227                 default:        speed = XFER_PIO_0; break;
 228         }
 229         (void) aec62xx_tune_chipset(drive, speed);
 230 }
 231
 232 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
 233 {
 234         ide_hwif_t *hwif        = HWIF(drive);
 235         struct hd_driveid *id   = drive->id;
 236
 237         if ((id->capability & 1) && drive->autodma) {
 238
 239                 if (ide_use_dma(drive)) {
 240                         if (config_chipset_for_dma(drive))
 241                                 return hwif->ide_dma_on(drive);
 242                 }
 243
 244                 goto fast_ata_pio;
 245
 246         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 247 fast_ata_pio:
 248                 aec62xx_tune_drive(drive, 5);
 249                 return hwif->ide_dma_off_quietly(drive);
 250         }
 251         /* IORDY not supported */
 252         return 0;
 253 }
 254
 255 static int aec62xx_irq_timeout (ide_drive_t *drive)
 256 {
 257         ide_hwif_t *hwif        = HWIF(drive);
 258         struct pci_dev *dev     = hwif->pci_dev;
 259
 260         switch(dev->device) {
 261                 case PCI_DEVICE_ID_ARTOP_ATP860:
 262                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 263                 case PCI_DEVICE_ID_ARTOP_ATP865:
 264                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 265                         printk(" AEC62XX time out ");
 266 #if 0
 267                         {
 268                                 int i = 0;
 269                                 u8 reg49h = 0;
 270                                 pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, &reg49h);
 271                                 for (i=0;i<256;i++)
 272                                         pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
 273                                 pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
 274                         }
 275                         return 0;
 276 #endif
 277                 default:
 278                         break;
 279         }
 280 #if 0
 281         {
 282                 ide_hwif_t *hwif        = HWIF(drive);
 283                 struct pci_dev *dev     = hwif->pci_dev;
 284                 u8 tmp1 = 0, tmp2 = 0, mode6 = 0;
 285
 286                 pci_read_config_byte(dev, 0x44, &tmp1);
 287                 pci_read_config_byte(dev, 0x45, &tmp2);
 288                 printk(" AEC6280 r44=%x r45=%x ",tmp1,tmp2);
 289                 mode6 = HWIF(drive)->INB(((hwif->channel) ?
 290                                            hwif->mate->dma_status :
 291                                            hwif->dma_status));
 292                 printk(" AEC6280 133=%x ", (mode6 & 0x10));
 293         }
 294 #endif
 295         return 0;
 296 }
 297
 298 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 299 {
 300         int bus_speed = system_bus_clock();
 301
 302         if (dev->resource[PCI_ROM_RESOURCE].start) {
 303                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 304                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
 305         }
 306
 307         if (bus_speed <= 33)
 308                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 309         else
 310                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 311
 312         return dev->irq;
 313 }
 314
 315 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
 316 {
 317         hwif->autodma = 0;
 318         hwif->tuneproc = &aec62xx_tune_drive;
 319         hwif->speedproc = &aec62xx_tune_chipset;
 320
 321         if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 322                 hwif->serialized = hwif->channel;
 323                 hwif->no_dsc = 1;
 324         }
 325
 326         if (hwif->mate)
 327                 hwif->mate->serialized = hwif->serialized;
 328
 329         if (!hwif->dma_base) {
 330                 hwif->drives[0].autotune = 1;
 331                 hwif->drives[1].autotune = 1;
 332                 return;
 333         }
 334
 335         hwif->ultra_mask = 0x7f;
 336         hwif->mwdma_mask = 0x07;
 337         hwif->swdma_mask = 0x07;
 338
 339         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
 340         hwif->ide_dma_lostirq   = &aec62xx_irq_timeout;
 341         hwif->ide_dma_timeout   = &aec62xx_irq_timeout;
 342         if (!noautodma)
 343                 hwif->autodma = 1;
 344         hwif->drives[0].autodma = hwif->autodma;
 345         hwif->drives[1].autodma = hwif->autodma;
 346 }
 347
 348 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
 349 {
 350         struct pci_dev *dev     = hwif->pci_dev;
 351
 352         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 353                 u8 reg54h = 0;
 354                 unsigned long flags;
 355
 356                 spin_lock_irqsave(&ide_lock, flags);
 357                 pci_read_config_byte(dev, 0x54, &reg54h);
 358                 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
 359                 spin_unlock_irqrestore(&ide_lock, flags);
 360         } else {
 361                 u8 ata66        = 0;
 362                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 363                 if (!(hwif->udma_four))
 364                         hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
 365         }
 366
 367         ide_setup_dma(hwif, dmabase, 8);
 368 }
 369
 370 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
 371 {
 372         return ide_setup_pci_device(dev, d);
 373 }
 374
 375 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
 376 {
 377         unsigned long bar4reg = pci_resource_start(dev, 4);
 378
 379         if (inb(bar4reg+2) & 0x10) {
 380                 strcpy(d->name, "AEC6880");
 381                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 382                         strcpy(d->name, "AEC6880R");
 383         } else {
 384                 strcpy(d->name, "AEC6280");
 385                 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
 386                         strcpy(d->name, "AEC6280R");
 387         }
 388
 389         return ide_setup_pci_device(dev, d);
 390 }
 391
 392 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
 393         {       /* 0 */
 394                 .name           = "AEC6210",
 395                 .init_setup     = init_setup_aec62xx,
 396                 .init_chipset   = init_chipset_aec62xx,
 397                 .init_hwif      = init_hwif_aec62xx,
 398                 .init_dma       = init_dma_aec62xx,
 399                 .channels       = 2,
 400                 .autodma        = AUTODMA,
 401                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 402                 .bootable       = OFF_BOARD,
 403         },{     /* 1 */
 404                 .name           = "AEC6260",
 405                 .init_setup     = init_setup_aec62xx,
 406                 .init_chipset   = init_chipset_aec62xx,
 407                 .init_hwif      = init_hwif_aec62xx,
 408                 .init_dma       = init_dma_aec62xx,
 409                 .channels       = 2,
 410                 .autodma        = NOAUTODMA,
 411                 .bootable       = OFF_BOARD,
 412         },{     /* 2 */
 413                 .name           = "AEC6260R",
 414                 .init_setup     = init_setup_aec62xx,
 415                 .init_chipset   = init_chipset_aec62xx,
 416                 .init_hwif      = init_hwif_aec62xx,
 417                 .init_dma       = init_dma_aec62xx,
 418                 .channels       = 2,
 419                 .autodma        = AUTODMA,
 420                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 421                 .bootable       = NEVER_BOARD,
 422         },{     /* 3 */
 423                 .name           = "AEC6X80",
 424                 .init_setup     = init_setup_aec6x80,
 425                 .init_chipset   = init_chipset_aec62xx,
 426                 .init_hwif      = init_hwif_aec62xx,
 427                 .init_dma       = init_dma_aec62xx,
 428                 .channels       = 2,
 429                 .autodma        = AUTODMA,
 430                 .bootable       = OFF_BOARD,
 431         },{     /* 4 */
 432                 .name           = "AEC6X80R",
 433                 .init_setup     = init_setup_aec6x80,
 434                 .init_chipset   = init_chipset_aec62xx,
 435                 .init_hwif      = init_hwif_aec62xx,
 436                 .init_dma       = init_dma_aec62xx,
 437                 .channels       = 2,
 438                 .autodma        = AUTODMA,
 439                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 440                 .bootable       = OFF_BOARD,
 441         }
 442 };
 443
 444 /**
 445  *      aec62xx_init_one        -       called when a AEC is found
 446  *      @dev: the aec62xx device
 447  *      @id: the matching pci id
 448  *
 449  *      Called when the PCI registration layer (or the IDE initialization)
 450  *      finds a device matching our IDE device tables.
 451  */
 452
 453 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 454 {
 455         ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
 456
 457         return d->init_setup(dev, d);
 458 }
 459
 460 static struct pci_device_id aec62xx_pci_tbl[] = {
 461         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 462         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
 463         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
 464         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
 465         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
 466         { 0, },
 467 };
 468 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 469
 470 static struct pci_driver driver = {
 471         .name           = "AEC62xx_IDE",
 472         .id_table       = aec62xx_pci_tbl,
 473         .probe          = aec62xx_init_one,
 474 };
 475
 476 static int aec62xx_ide_init(void)
 477 {
 478         return ide_pci_register_driver(&driver);
 479 }
 480
 481 module_init(aec62xx_ide_init);
 482
 483 MODULE_AUTHOR("Andre Hedrick");
 484 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 485 MODULE_LICENSE("GPL");