drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/tick.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/intel-family.h>
  66 #include <asm/mwait.h>
  67 #include <asm/msr.h>
  68
  69 #define INTEL_IDLE_VERSION "0.4.1"
  70 #define PREFIX "intel_idle: "
  71
  72 static struct cpuidle_driver intel_idle_driver = {
  73         .name = "intel_idle",
  74         .owner = THIS_MODULE,
  75 };
  76 /* intel_idle.max_cstate=0 disables driver */
  77 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  78
  79 static unsigned int mwait_substates;
  80
  81 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  82 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  83 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  84
  85 struct idle_cpu {
  86         struct cpuidle_state *state_table;
  87
  88         /*
  89          * Hardware C-state auto-demotion may not always be optimal.
  90          * Indicate which enable bits to clear here.
  91          */
  92         unsigned long auto_demotion_disable_flags;
  93         bool byt_auto_demotion_disable_flag;
  94         bool disable_promotion_to_c1e;
  95 };
  96
  97 static const struct idle_cpu *icpu;
  98 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  99 static int intel_idle(struct cpuidle_device *dev,
 100                         struct cpuidle_driver *drv, int index);
 101 static void intel_idle_freeze(struct cpuidle_device *dev,
 102                               struct cpuidle_driver *drv, int index);
 103 static int intel_idle_cpu_init(int cpu);
 104
 105 static struct cpuidle_state *cpuidle_state_table;
 106
 107 /*
 108  * Set this flag for states where the HW flushes the TLB for us
 109  * and so we don't need cross-calls to keep it consistent.
 110  * If this flag is set, SW flushes the TLB, so even if the
 111  * HW doesn't do the flushing, this flag is safe to use.
 112  */
 113 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 114
 115 /*
 116  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 117  * the C-state (top nibble) and sub-state (bottom nibble)
 118  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 119  *
 120  * We store the hint at the top of our "flags" for each state.
 121  */
 122 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 123 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 124
 125 /*
 126  * States are indexed by the cstate number,
 127  * which is also the index into the MWAIT hint array.
 128  * Thus C0 is a dummy.
 129  */
 130 static struct cpuidle_state nehalem_cstates[] = {
 131         {
 132                 .name = "C1-NHM",
 133                 .desc = "MWAIT 0x00",
 134                 .flags = MWAIT2flg(0x00),
 135                 .exit_latency = 3,
 136                 .target_residency = 6,
 137                 .enter = &intel_idle,
 138                 .enter_freeze = intel_idle_freeze, },
 139         {
 140                 .name = "C1E-NHM",
 141                 .desc = "MWAIT 0x01",
 142                 .flags = MWAIT2flg(0x01),
 143                 .exit_latency = 10,
 144                 .target_residency = 20,
 145                 .enter = &intel_idle,
 146                 .enter_freeze = intel_idle_freeze, },
 147         {
 148                 .name = "C3-NHM",
 149                 .desc = "MWAIT 0x10",
 150                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 151                 .exit_latency = 20,
 152                 .target_residency = 80,
 153                 .enter = &intel_idle,
 154                 .enter_freeze = intel_idle_freeze, },
 155         {
 156                 .name = "C6-NHM",
 157                 .desc = "MWAIT 0x20",
 158                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 159                 .exit_latency = 200,
 160                 .target_residency = 800,
 161                 .enter = &intel_idle,
 162                 .enter_freeze = intel_idle_freeze, },
 163         {
 164                 .enter = NULL }
 165 };
 166
 167 static struct cpuidle_state snb_cstates[] = {
 168         {
 169                 .name = "C1-SNB",
 170                 .desc = "MWAIT 0x00",
 171                 .flags = MWAIT2flg(0x00),
 172                 .exit_latency = 2,
 173                 .target_residency = 2,
 174                 .enter = &intel_idle,
 175                 .enter_freeze = intel_idle_freeze, },
 176         {
 177                 .name = "C1E-SNB",
 178                 .desc = "MWAIT 0x01",
 179                 .flags = MWAIT2flg(0x01),
 180                 .exit_latency = 10,
 181                 .target_residency = 20,
 182                 .enter = &intel_idle,
 183                 .enter_freeze = intel_idle_freeze, },
 184         {
 185                 .name = "C3-SNB",
 186                 .desc = "MWAIT 0x10",
 187                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 188                 .exit_latency = 80,
 189                 .target_residency = 211,
 190                 .enter = &intel_idle,
 191                 .enter_freeze = intel_idle_freeze, },
 192         {
 193                 .name = "C6-SNB",
 194                 .desc = "MWAIT 0x20",
 195                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 196                 .exit_latency = 104,
 197                 .target_residency = 345,
 198                 .enter = &intel_idle,
 199                 .enter_freeze = intel_idle_freeze, },
 200         {
 201                 .name = "C7-SNB",
 202                 .desc = "MWAIT 0x30",
 203                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 204                 .exit_latency = 109,
 205                 .target_residency = 345,
 206                 .enter = &intel_idle,
 207                 .enter_freeze = intel_idle_freeze, },
 208         {
 209                 .enter = NULL }
 210 };
 211
 212 static struct cpuidle_state byt_cstates[] = {
 213         {
 214                 .name = "C1-BYT",
 215                 .desc = "MWAIT 0x00",
 216                 .flags = MWAIT2flg(0x00),
 217                 .exit_latency = 1,
 218                 .target_residency = 1,
 219                 .enter = &intel_idle,
 220                 .enter_freeze = intel_idle_freeze, },
 221         {
 222                 .name = "C6N-BYT",
 223                 .desc = "MWAIT 0x58",
 224                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 225                 .exit_latency = 300,
 226                 .target_residency = 275,
 227                 .enter = &intel_idle,
 228                 .enter_freeze = intel_idle_freeze, },
 229         {
 230                 .name = "C6S-BYT",
 231                 .desc = "MWAIT 0x52",
 232                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 233                 .exit_latency = 500,
 234                 .target_residency = 560,
 235                 .enter = &intel_idle,
 236                 .enter_freeze = intel_idle_freeze, },
 237         {
 238                 .name = "C7-BYT",
 239                 .desc = "MWAIT 0x60",
 240                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 241                 .exit_latency = 1200,
 242                 .target_residency = 4000,
 243                 .enter = &intel_idle,
 244                 .enter_freeze = intel_idle_freeze, },
 245         {
 246                 .name = "C7S-BYT",
 247                 .desc = "MWAIT 0x64",
 248                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 249                 .exit_latency = 10000,
 250                 .target_residency = 20000,
 251                 .enter = &intel_idle,
 252                 .enter_freeze = intel_idle_freeze, },
 253         {
 254                 .enter = NULL }
 255 };
 256
 257 static struct cpuidle_state cht_cstates[] = {
 258         {
 259                 .name = "C1-CHT",
 260                 .desc = "MWAIT 0x00",
 261                 .flags = MWAIT2flg(0x00),
 262                 .exit_latency = 1,
 263                 .target_residency = 1,
 264                 .enter = &intel_idle,
 265                 .enter_freeze = intel_idle_freeze, },
 266         {
 267                 .name = "C6N-CHT",
 268                 .desc = "MWAIT 0x58",
 269                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
 270                 .exit_latency = 80,
 271                 .target_residency = 275,
 272                 .enter = &intel_idle,
 273                 .enter_freeze = intel_idle_freeze, },
 274         {
 275                 .name = "C6S-CHT",
 276                 .desc = "MWAIT 0x52",
 277                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 278                 .exit_latency = 200,
 279                 .target_residency = 560,
 280                 .enter = &intel_idle,
 281                 .enter_freeze = intel_idle_freeze, },
 282         {
 283                 .name = "C7-CHT",
 284                 .desc = "MWAIT 0x60",
 285                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 286                 .exit_latency = 1200,
 287                 .target_residency = 4000,
 288                 .enter = &intel_idle,
 289                 .enter_freeze = intel_idle_freeze, },
 290         {
 291                 .name = "C7S-CHT",
 292                 .desc = "MWAIT 0x64",
 293                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
 294                 .exit_latency = 10000,
 295                 .target_residency = 20000,
 296                 .enter = &intel_idle,
 297                 .enter_freeze = intel_idle_freeze, },
 298         {
 299                 .enter = NULL }
 300 };
 301
 302 static struct cpuidle_state ivb_cstates[] = {
 303         {
 304                 .name = "C1-IVB",
 305                 .desc = "MWAIT 0x00",
 306                 .flags = MWAIT2flg(0x00),
 307                 .exit_latency = 1,
 308                 .target_residency = 1,
 309                 .enter = &intel_idle,
 310                 .enter_freeze = intel_idle_freeze, },
 311         {
 312                 .name = "C1E-IVB",
 313                 .desc = "MWAIT 0x01",
 314                 .flags = MWAIT2flg(0x01),
 315                 .exit_latency = 10,
 316                 .target_residency = 20,
 317                 .enter = &intel_idle,
 318                 .enter_freeze = intel_idle_freeze, },
 319         {
 320                 .name = "C3-IVB",
 321                 .desc = "MWAIT 0x10",
 322                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 323                 .exit_latency = 59,
 324                 .target_residency = 156,
 325                 .enter = &intel_idle,
 326                 .enter_freeze = intel_idle_freeze, },
 327         {
 328                 .name = "C6-IVB",
 329                 .desc = "MWAIT 0x20",
 330                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 331                 .exit_latency = 80,
 332                 .target_residency = 300,
 333                 .enter = &intel_idle,
 334                 .enter_freeze = intel_idle_freeze, },
 335         {
 336                 .name = "C7-IVB",
 337                 .desc = "MWAIT 0x30",
 338                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 339                 .exit_latency = 87,
 340                 .target_residency = 300,
 341                 .enter = &intel_idle,
 342                 .enter_freeze = intel_idle_freeze, },
 343         {
 344                 .enter = NULL }
 345 };
 346
 347 static struct cpuidle_state ivt_cstates[] = {
 348         {
 349                 .name = "C1-IVT",
 350                 .desc = "MWAIT 0x00",
 351                 .flags = MWAIT2flg(0x00),
 352                 .exit_latency = 1,
 353                 .target_residency = 1,
 354                 .enter = &intel_idle,
 355                 .enter_freeze = intel_idle_freeze, },
 356         {
 357                 .name = "C1E-IVT",
 358                 .desc = "MWAIT 0x01",
 359                 .flags = MWAIT2flg(0x01),
 360                 .exit_latency = 10,
 361                 .target_residency = 80,
 362                 .enter = &intel_idle,
 363                 .enter_freeze = intel_idle_freeze, },
 364         {
 365                 .name = "C3-IVT",
 366                 .desc = "MWAIT 0x10",
 367                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 368                 .exit_latency = 59,
 369                 .target_residency = 156,
 370                 .enter = &intel_idle,
 371                 .enter_freeze = intel_idle_freeze, },
 372         {
 373                 .name = "C6-IVT",
 374                 .desc = "MWAIT 0x20",
 375                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 376                 .exit_latency = 82,
 377                 .target_residency = 300,
 378                 .enter = &intel_idle,
 379                 .enter_freeze = intel_idle_freeze, },
 380         {
 381                 .enter = NULL }
 382 };
 383
 384 static struct cpuidle_state ivt_cstates_4s[] = {
 385         {
 386                 .name = "C1-IVT-4S",
 387                 .desc = "MWAIT 0x00",
 388                 .flags = MWAIT2flg(0x00),
 389                 .exit_latency = 1,
 390                 .target_residency = 1,
 391                 .enter = &intel_idle,
 392                 .enter_freeze = intel_idle_freeze, },
 393         {
 394                 .name = "C1E-IVT-4S",
 395                 .desc = "MWAIT 0x01",
 396                 .flags = MWAIT2flg(0x01),
 397                 .exit_latency = 10,
 398                 .target_residency = 250,
 399                 .enter = &intel_idle,
 400                 .enter_freeze = intel_idle_freeze, },
 401         {
 402                 .name = "C3-IVT-4S",
 403                 .desc = "MWAIT 0x10",
 404                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 405                 .exit_latency = 59,
 406                 .target_residency = 300,
 407                 .enter = &intel_idle,
 408                 .enter_freeze = intel_idle_freeze, },
 409         {
 410                 .name = "C6-IVT-4S",
 411                 .desc = "MWAIT 0x20",
 412                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 413                 .exit_latency = 84,
 414                 .target_residency = 400,
 415                 .enter = &intel_idle,
 416                 .enter_freeze = intel_idle_freeze, },
 417         {
 418                 .enter = NULL }
 419 };
 420
 421 static struct cpuidle_state ivt_cstates_8s[] = {
 422         {
 423                 .name = "C1-IVT-8S",
 424                 .desc = "MWAIT 0x00",
 425                 .flags = MWAIT2flg(0x00),
 426                 .exit_latency = 1,
 427                 .target_residency = 1,
 428                 .enter = &intel_idle,
 429                 .enter_freeze = intel_idle_freeze, },
 430         {
 431                 .name = "C1E-IVT-8S",
 432                 .desc = "MWAIT 0x01",
 433                 .flags = MWAIT2flg(0x01),
 434                 .exit_latency = 10,
 435                 .target_residency = 500,
 436                 .enter = &intel_idle,
 437                 .enter_freeze = intel_idle_freeze, },
 438         {
 439                 .name = "C3-IVT-8S",
 440                 .desc = "MWAIT 0x10",
 441                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 442                 .exit_latency = 59,
 443                 .target_residency = 600,
 444                 .enter = &intel_idle,
 445                 .enter_freeze = intel_idle_freeze, },
 446         {
 447                 .name = "C6-IVT-8S",
 448                 .desc = "MWAIT 0x20",
 449                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 450                 .exit_latency = 88,
 451                 .target_residency = 700,
 452                 .enter = &intel_idle,
 453                 .enter_freeze = intel_idle_freeze, },
 454         {
 455                 .enter = NULL }
 456 };
 457
 458 static struct cpuidle_state hsw_cstates[] = {
 459         {
 460                 .name = "C1-HSW",
 461                 .desc = "MWAIT 0x00",
 462                 .flags = MWAIT2flg(0x00),
 463                 .exit_latency = 2,
 464                 .target_residency = 2,
 465                 .enter = &intel_idle,
 466                 .enter_freeze = intel_idle_freeze, },
 467         {
 468                 .name = "C1E-HSW",
 469                 .desc = "MWAIT 0x01",
 470                 .flags = MWAIT2flg(0x01),
 471                 .exit_latency = 10,
 472                 .target_residency = 20,
 473                 .enter = &intel_idle,
 474                 .enter_freeze = intel_idle_freeze, },
 475         {
 476                 .name = "C3-HSW",
 477                 .desc = "MWAIT 0x10",
 478                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 479                 .exit_latency = 33,
 480                 .target_residency = 100,
 481                 .enter = &intel_idle,
 482                 .enter_freeze = intel_idle_freeze, },
 483         {
 484                 .name = "C6-HSW",
 485                 .desc = "MWAIT 0x20",
 486                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 487                 .exit_latency = 133,
 488                 .target_residency = 400,
 489                 .enter = &intel_idle,
 490                 .enter_freeze = intel_idle_freeze, },
 491         {
 492                 .name = "C7s-HSW",
 493                 .desc = "MWAIT 0x32",
 494                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 495                 .exit_latency = 166,
 496                 .target_residency = 500,
 497                 .enter = &intel_idle,
 498                 .enter_freeze = intel_idle_freeze, },
 499         {
 500                 .name = "C8-HSW",
 501                 .desc = "MWAIT 0x40",
 502                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 503                 .exit_latency = 300,
 504                 .target_residency = 900,
 505                 .enter = &intel_idle,
 506                 .enter_freeze = intel_idle_freeze, },
 507         {
 508                 .name = "C9-HSW",
 509                 .desc = "MWAIT 0x50",
 510                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 511                 .exit_latency = 600,
 512                 .target_residency = 1800,
 513                 .enter = &intel_idle,
 514                 .enter_freeze = intel_idle_freeze, },
 515         {
 516                 .name = "C10-HSW",
 517                 .desc = "MWAIT 0x60",
 518                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 519                 .exit_latency = 2600,
 520                 .target_residency = 7700,
 521                 .enter = &intel_idle,
 522                 .enter_freeze = intel_idle_freeze, },
 523         {
 524                 .enter = NULL }
 525 };
 526 static struct cpuidle_state bdw_cstates[] = {
 527         {
 528                 .name = "C1-BDW",
 529                 .desc = "MWAIT 0x00",
 530                 .flags = MWAIT2flg(0x00),
 531                 .exit_latency = 2,
 532                 .target_residency = 2,
 533                 .enter = &intel_idle,
 534                 .enter_freeze = intel_idle_freeze, },
 535         {
 536                 .name = "C1E-BDW",
 537                 .desc = "MWAIT 0x01",
 538                 .flags = MWAIT2flg(0x01),
 539                 .exit_latency = 10,
 540                 .target_residency = 20,
 541                 .enter = &intel_idle,
 542                 .enter_freeze = intel_idle_freeze, },
 543         {
 544                 .name = "C3-BDW",
 545                 .desc = "MWAIT 0x10",
 546                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 547                 .exit_latency = 40,
 548                 .target_residency = 100,
 549                 .enter = &intel_idle,
 550                 .enter_freeze = intel_idle_freeze, },
 551         {
 552                 .name = "C6-BDW",
 553                 .desc = "MWAIT 0x20",
 554                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 555                 .exit_latency = 133,
 556                 .target_residency = 400,
 557                 .enter = &intel_idle,
 558                 .enter_freeze = intel_idle_freeze, },
 559         {
 560                 .name = "C7s-BDW",
 561                 .desc = "MWAIT 0x32",
 562                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
 563                 .exit_latency = 166,
 564                 .target_residency = 500,
 565                 .enter = &intel_idle,
 566                 .enter_freeze = intel_idle_freeze, },
 567         {
 568                 .name = "C8-BDW",
 569                 .desc = "MWAIT 0x40",
 570                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 571                 .exit_latency = 300,
 572                 .target_residency = 900,
 573                 .enter = &intel_idle,
 574                 .enter_freeze = intel_idle_freeze, },
 575         {
 576                 .name = "C9-BDW",
 577                 .desc = "MWAIT 0x50",
 578                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 579                 .exit_latency = 600,
 580                 .target_residency = 1800,
 581                 .enter = &intel_idle,
 582                 .enter_freeze = intel_idle_freeze, },
 583         {
 584                 .name = "C10-BDW",
 585                 .desc = "MWAIT 0x60",
 586                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 587                 .exit_latency = 2600,
 588                 .target_residency = 7700,
 589                 .enter = &intel_idle,
 590                 .enter_freeze = intel_idle_freeze, },
 591         {
 592                 .enter = NULL }
 593 };
 594
 595 static struct cpuidle_state skl_cstates[] = {
 596         {
 597                 .name = "C1-SKL",
 598                 .desc = "MWAIT 0x00",
 599                 .flags = MWAIT2flg(0x00),
 600                 .exit_latency = 2,
 601                 .target_residency = 2,
 602                 .enter = &intel_idle,
 603                 .enter_freeze = intel_idle_freeze, },
 604         {
 605                 .name = "C1E-SKL",
 606                 .desc = "MWAIT 0x01",
 607                 .flags = MWAIT2flg(0x01),
 608                 .exit_latency = 10,
 609                 .target_residency = 20,
 610                 .enter = &intel_idle,
 611                 .enter_freeze = intel_idle_freeze, },
 612         {
 613                 .name = "C3-SKL",
 614                 .desc = "MWAIT 0x10",
 615                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 616                 .exit_latency = 70,
 617                 .target_residency = 100,
 618                 .enter = &intel_idle,
 619                 .enter_freeze = intel_idle_freeze, },
 620         {
 621                 .name = "C6-SKL",
 622                 .desc = "MWAIT 0x20",
 623                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 624                 .exit_latency = 85,
 625                 .target_residency = 200,
 626                 .enter = &intel_idle,
 627                 .enter_freeze = intel_idle_freeze, },
 628         {
 629                 .name = "C7s-SKL",
 630                 .desc = "MWAIT 0x33",
 631                 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
 632                 .exit_latency = 124,
 633                 .target_residency = 800,
 634                 .enter = &intel_idle,
 635                 .enter_freeze = intel_idle_freeze, },
 636         {
 637                 .name = "C8-SKL",
 638                 .desc = "MWAIT 0x40",
 639                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 640                 .exit_latency = 200,
 641                 .target_residency = 800,
 642                 .enter = &intel_idle,
 643                 .enter_freeze = intel_idle_freeze, },
 644         {
 645                 .name = "C9-SKL",
 646                 .desc = "MWAIT 0x50",
 647                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 648                 .exit_latency = 480,
 649                 .target_residency = 5000,
 650                 .enter = &intel_idle,
 651                 .enter_freeze = intel_idle_freeze, },
 652         {
 653                 .name = "C10-SKL",
 654                 .desc = "MWAIT 0x60",
 655                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 656                 .exit_latency = 890,
 657                 .target_residency = 5000,
 658                 .enter = &intel_idle,
 659                 .enter_freeze = intel_idle_freeze, },
 660         {
 661                 .enter = NULL }
 662 };
 663
 664 static struct cpuidle_state skx_cstates[] = {
 665         {
 666                 .name = "C1-SKX",
 667                 .desc = "MWAIT 0x00",
 668                 .flags = MWAIT2flg(0x00),
 669                 .exit_latency = 2,
 670                 .target_residency = 2,
 671                 .enter = &intel_idle,
 672                 .enter_freeze = intel_idle_freeze, },
 673         {
 674                 .name = "C1E-SKX",
 675                 .desc = "MWAIT 0x01",
 676                 .flags = MWAIT2flg(0x01),
 677                 .exit_latency = 10,
 678                 .target_residency = 20,
 679                 .enter = &intel_idle,
 680                 .enter_freeze = intel_idle_freeze, },
 681         {
 682                 .name = "C6-SKX",
 683                 .desc = "MWAIT 0x20",
 684                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 685                 .exit_latency = 133,
 686                 .target_residency = 600,
 687                 .enter = &intel_idle,
 688                 .enter_freeze = intel_idle_freeze, },
 689         {
 690                 .enter = NULL }
 691 };
 692
 693 static struct cpuidle_state atom_cstates[] = {
 694         {
 695                 .name = "C1E-ATM",
 696                 .desc = "MWAIT 0x00",
 697                 .flags = MWAIT2flg(0x00),
 698                 .exit_latency = 10,
 699                 .target_residency = 20,
 700                 .enter = &intel_idle,
 701                 .enter_freeze = intel_idle_freeze, },
 702         {
 703                 .name = "C2-ATM",
 704                 .desc = "MWAIT 0x10",
 705                 .flags = MWAIT2flg(0x10),
 706                 .exit_latency = 20,
 707                 .target_residency = 80,
 708                 .enter = &intel_idle,
 709                 .enter_freeze = intel_idle_freeze, },
 710         {
 711                 .name = "C4-ATM",
 712                 .desc = "MWAIT 0x30",
 713                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
 714                 .exit_latency = 100,
 715                 .target_residency = 400,
 716                 .enter = &intel_idle,
 717                 .enter_freeze = intel_idle_freeze, },
 718         {
 719                 .name = "C6-ATM",
 720                 .desc = "MWAIT 0x52",
 721                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
 722                 .exit_latency = 140,
 723                 .target_residency = 560,
 724                 .enter = &intel_idle,
 725                 .enter_freeze = intel_idle_freeze, },
 726         {
 727                 .enter = NULL }
 728 };
 729 static struct cpuidle_state avn_cstates[] = {
 730         {
 731                 .name = "C1-AVN",
 732                 .desc = "MWAIT 0x00",
 733                 .flags = MWAIT2flg(0x00),
 734                 .exit_latency = 2,
 735                 .target_residency = 2,
 736                 .enter = &intel_idle,
 737                 .enter_freeze = intel_idle_freeze, },
 738         {
 739                 .name = "C6-AVN",
 740                 .desc = "MWAIT 0x51",
 741                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
 742                 .exit_latency = 15,
 743                 .target_residency = 45,
 744                 .enter = &intel_idle,
 745                 .enter_freeze = intel_idle_freeze, },
 746         {
 747                 .enter = NULL }
 748 };
 749 static struct cpuidle_state knl_cstates[] = {
 750         {
 751                 .name = "C1-KNL",
 752                 .desc = "MWAIT 0x00",
 753                 .flags = MWAIT2flg(0x00),
 754                 .exit_latency = 1,
 755                 .target_residency = 2,
 756                 .enter = &intel_idle,
 757                 .enter_freeze = intel_idle_freeze },
 758         {
 759                 .name = "C6-KNL",
 760                 .desc = "MWAIT 0x10",
 761                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
 762                 .exit_latency = 120,
 763                 .target_residency = 500,
 764                 .enter = &intel_idle,
 765                 .enter_freeze = intel_idle_freeze },
 766         {
 767                 .enter = NULL }
 768 };
 769
 770 static struct cpuidle_state bxt_cstates[] = {
 771         {
 772                 .name = "C1-BXT",
 773                 .desc = "MWAIT 0x00",
 774                 .flags = MWAIT2flg(0x00),
 775                 .exit_latency = 2,
 776                 .target_residency = 2,
 777                 .enter = &intel_idle,
 778                 .enter_freeze = intel_idle_freeze, },
 779         {
 780                 .name = "C1E-BXT",
 781                 .desc = "MWAIT 0x01",
 782                 .flags = MWAIT2flg(0x01),
 783                 .exit_latency = 10,
 784                 .target_residency = 20,
 785                 .enter = &intel_idle,
 786                 .enter_freeze = intel_idle_freeze, },
 787         {
 788                 .name = "C6-BXT",
 789                 .desc = "MWAIT 0x20",
 790                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
 791                 .exit_latency = 133,
 792                 .target_residency = 133,
 793                 .enter = &intel_idle,
 794                 .enter_freeze = intel_idle_freeze, },
 795         {
 796                 .name = "C7s-BXT",
 797                 .desc = "MWAIT 0x31",
 798                 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
 799                 .exit_latency = 155,
 800                 .target_residency = 155,
 801                 .enter = &intel_idle,
 802                 .enter_freeze = intel_idle_freeze, },
 803         {
 804                 .name = "C8-BXT",
 805                 .desc = "MWAIT 0x40",
 806                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
 807                 .exit_latency = 1000,
 808                 .target_residency = 1000,
 809                 .enter = &intel_idle,
 810                 .enter_freeze = intel_idle_freeze, },
 811         {
 812                 .name = "C9-BXT",
 813                 .desc = "MWAIT 0x50",
 814                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
 815                 .exit_latency = 2000,
 816                 .target_residency = 2000,
 817                 .enter = &intel_idle,
 818                 .enter_freeze = intel_idle_freeze, },
 819         {
 820                 .name = "C10-BXT",
 821                 .desc = "MWAIT 0x60",
 822                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 823                 .exit_latency = 10000,
 824                 .target_residency = 10000,
 825                 .enter = &intel_idle,
 826                 .enter_freeze = intel_idle_freeze, },
 827         {
 828                 .enter = NULL }
 829 };
 830
 831 /**
 832  * intel_idle
 833  * @dev: cpuidle_device
 834  * @drv: cpuidle driver
 835  * @index: index of cpuidle state
 836  *
 837  * Must be called under local_irq_disable().
 838  */
 839 static int intel_idle(struct cpuidle_device *dev,
 840                 struct cpuidle_driver *drv, int index)
 841 {
 842         unsigned long ecx = 1; /* break on interrupt flag */
 843         struct cpuidle_state *state = &drv->states[index];
 844         unsigned long eax = flg2MWAIT(state->flags);
 845         unsigned int cstate;
 846         int cpu = smp_processor_id();
 847
 848         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 849
 850         /*
 851          * leave_mm() to avoid costly and often unnecessary wakeups
 852          * for flushing the user TLB's associated with the active mm.
 853          */
 854         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 855                 leave_mm(cpu);
 856
 857         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 858                 tick_broadcast_enter();
 859
 860         mwait_idle_with_hints(eax, ecx);
 861
 862         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 863                 tick_broadcast_exit();
 864
 865         return index;
 866 }
 867
 868 /**
 869  * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
 870  * @dev: cpuidle_device
 871  * @drv: cpuidle driver
 872  * @index: state index
 873  */
 874 static void intel_idle_freeze(struct cpuidle_device *dev,
 875                              struct cpuidle_driver *drv, int index)
 876 {
 877         unsigned long ecx = 1; /* break on interrupt flag */
 878         unsigned long eax = flg2MWAIT(drv->states[index].flags);
 879
 880         mwait_idle_with_hints(eax, ecx);
 881 }
 882
 883 static void __setup_broadcast_timer(void *arg)
 884 {
 885         unsigned long on = (unsigned long)arg;
 886
 887         if (on)
 888                 tick_broadcast_enable();
 889         else
 890                 tick_broadcast_disable();
 891 }
 892
 893 static int cpu_hotplug_notify(struct notifier_block *n,
 894                               unsigned long action, void *hcpu)
 895 {
 896         int hotcpu = (unsigned long)hcpu;
 897         struct cpuidle_device *dev;
 898
 899         switch (action & ~CPU_TASKS_FROZEN) {
 900         case CPU_ONLINE:
 901
 902                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 903                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 904                                                  (void *)true, 1);
 905
 906                 /*
 907                  * Some systems can hotplug a cpu at runtime after
 908                  * the kernel has booted, we have to initialize the
 909                  * driver in this case
 910                  */
 911                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 912                 if (dev->registered)
 913                         break;
 914
 915                 if (intel_idle_cpu_init(hotcpu))
 916                         return NOTIFY_BAD;
 917
 918                 break;
 919         }
 920         return NOTIFY_OK;
 921 }
 922
 923 static struct notifier_block cpu_hotplug_notifier = {
 924         .notifier_call = cpu_hotplug_notify,
 925 };
 926
 927 static void auto_demotion_disable(void *dummy)
 928 {
 929         unsigned long long msr_bits;
 930
 931         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 932         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 933         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 934 }
 935 static void c1e_promotion_disable(void *dummy)
 936 {
 937         unsigned long long msr_bits;
 938
 939         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 940         msr_bits &= ~0x2;
 941         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 942 }
 943
 944 static const struct idle_cpu idle_cpu_nehalem = {
 945         .state_table = nehalem_cstates,
 946         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 947         .disable_promotion_to_c1e = true,
 948 };
 949
 950 static const struct idle_cpu idle_cpu_atom = {
 951         .state_table = atom_cstates,
 952 };
 953
 954 static const struct idle_cpu idle_cpu_lincroft = {
 955         .state_table = atom_cstates,
 956         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 957 };
 958
 959 static const struct idle_cpu idle_cpu_snb = {
 960         .state_table = snb_cstates,
 961         .disable_promotion_to_c1e = true,
 962 };
 963
 964 static const struct idle_cpu idle_cpu_byt = {
 965         .state_table = byt_cstates,
 966         .disable_promotion_to_c1e = true,
 967         .byt_auto_demotion_disable_flag = true,
 968 };
 969
 970 static const struct idle_cpu idle_cpu_cht = {
 971         .state_table = cht_cstates,
 972         .disable_promotion_to_c1e = true,
 973         .byt_auto_demotion_disable_flag = true,
 974 };
 975
 976 static const struct idle_cpu idle_cpu_ivb = {
 977         .state_table = ivb_cstates,
 978         .disable_promotion_to_c1e = true,
 979 };
 980
 981 static const struct idle_cpu idle_cpu_ivt = {
 982         .state_table = ivt_cstates,
 983         .disable_promotion_to_c1e = true,
 984 };
 985
 986 static const struct idle_cpu idle_cpu_hsw = {
 987         .state_table = hsw_cstates,
 988         .disable_promotion_to_c1e = true,
 989 };
 990
 991 static const struct idle_cpu idle_cpu_bdw = {
 992         .state_table = bdw_cstates,
 993         .disable_promotion_to_c1e = true,
 994 };
 995
 996 static const struct idle_cpu idle_cpu_skl = {
 997         .state_table = skl_cstates,
 998         .disable_promotion_to_c1e = true,
 999 };
1000
1001 static const struct idle_cpu idle_cpu_skx = {
1002         .state_table = skx_cstates,
1003         .disable_promotion_to_c1e = true,
1004 };
1005
1006 static const struct idle_cpu idle_cpu_avn = {
1007         .state_table = avn_cstates,
1008         .disable_promotion_to_c1e = true,
1009 };
1010
1011 static const struct idle_cpu idle_cpu_knl = {
1012         .state_table = knl_cstates,
1013 };
1014
1015 static const struct idle_cpu idle_cpu_bxt = {
1016         .state_table = bxt_cstates,
1017         .disable_promotion_to_c1e = true,
1018 };
1019
1020 #define ICPU(model, cpu) \
1021         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
1022
1023 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1024         ICPU(INTEL_FAM6_NEHALEM_EP,             idle_cpu_nehalem),
1025         ICPU(INTEL_FAM6_NEHALEM,                idle_cpu_nehalem),
1026         ICPU(INTEL_FAM6_WESTMERE2,              idle_cpu_nehalem),
1027         ICPU(INTEL_FAM6_WESTMERE,               idle_cpu_nehalem),
1028         ICPU(INTEL_FAM6_WESTMERE_EP,            idle_cpu_nehalem),
1029         ICPU(INTEL_FAM6_NEHALEM_EX,             idle_cpu_nehalem),
1030         ICPU(INTEL_FAM6_ATOM_PINEVIEW,          idle_cpu_atom),
1031         ICPU(INTEL_FAM6_ATOM_LINCROFT,          idle_cpu_lincroft),
1032         ICPU(INTEL_FAM6_WESTMERE_EX,            idle_cpu_nehalem),
1033         ICPU(INTEL_FAM6_SANDYBRIDGE,            idle_cpu_snb),
1034         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          idle_cpu_snb),
1035         ICPU(INTEL_FAM6_ATOM_CEDARVIEW,         idle_cpu_atom),
1036         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       idle_cpu_byt),
1037         ICPU(INTEL_FAM6_ATOM_AIRMONT,           idle_cpu_cht),
1038         ICPU(INTEL_FAM6_IVYBRIDGE,              idle_cpu_ivb),
1039         ICPU(INTEL_FAM6_IVYBRIDGE_X,            idle_cpu_ivt),
1040         ICPU(INTEL_FAM6_HASWELL_CORE,           idle_cpu_hsw),
1041         ICPU(INTEL_FAM6_HASWELL_X,              idle_cpu_hsw),
1042         ICPU(INTEL_FAM6_HASWELL_ULT,            idle_cpu_hsw),
1043         ICPU(INTEL_FAM6_HASWELL_GT3E,           idle_cpu_hsw),
1044         ICPU(INTEL_FAM6_ATOM_SILVERMONT2,       idle_cpu_avn),
1045         ICPU(INTEL_FAM6_BROADWELL_CORE,         idle_cpu_bdw),
1046         ICPU(INTEL_FAM6_BROADWELL_GT3E,         idle_cpu_bdw),
1047         ICPU(INTEL_FAM6_BROADWELL_X,            idle_cpu_bdw),
1048         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       idle_cpu_bdw),
1049         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         idle_cpu_skl),
1050         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        idle_cpu_skl),
1051         ICPU(INTEL_FAM6_KABYLAKE_MOBILE,        idle_cpu_skl),
1052         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP,       idle_cpu_skl),
1053         ICPU(INTEL_FAM6_SKYLAKE_X,              idle_cpu_skx),
1054         ICPU(INTEL_FAM6_XEON_PHI_KNL,           idle_cpu_knl),
1055         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          idle_cpu_bxt),
1056         {}
1057 };
1058 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
1059
1060 /*
1061  * intel_idle_probe()
1062  */
1063 static int __init intel_idle_probe(void)
1064 {
1065         unsigned int eax, ebx, ecx;
1066         const struct x86_cpu_id *id;
1067
1068         if (max_cstate == 0) {
1069                 pr_debug(PREFIX "disabled\n");
1070                 return -EPERM;
1071         }
1072
1073         id = x86_match_cpu(intel_idle_ids);
1074         if (!id) {
1075                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
1076                     boot_cpu_data.x86 == 6)
1077                         pr_debug(PREFIX "does not run on family %d model %d\n",
1078                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
1079                 return -ENODEV;
1080         }
1081
1082         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1083                 return -ENODEV;
1084
1085         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1086
1087         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1088             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1089             !mwait_substates)
1090                         return -ENODEV;
1091
1092         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
1093
1094         icpu = (const struct idle_cpu *)id->driver_data;
1095         cpuidle_state_table = icpu->state_table;
1096
1097         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
1098                 " model 0x%X\n", boot_cpu_data.x86_model);
1099
1100         return 0;
1101 }
1102
1103 /*
1104  * intel_idle_cpuidle_devices_uninit()
1105  * Unregisters the cpuidle devices.
1106  */
1107 static void intel_idle_cpuidle_devices_uninit(void)
1108 {
1109         int i;
1110         struct cpuidle_device *dev;
1111
1112         for_each_online_cpu(i) {
1113                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1114                 cpuidle_unregister_device(dev);
1115         }
1116 }
1117
1118 /*
1119  * ivt_idle_state_table_update(void)
1120  *
1121  * Tune IVT multi-socket targets
1122  * Assumption: num_sockets == (max_package_num + 1)
1123  */
1124 static void ivt_idle_state_table_update(void)
1125 {
1126         /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1127         int cpu, package_num, num_sockets = 1;
1128
1129         for_each_online_cpu(cpu) {
1130                 package_num = topology_physical_package_id(cpu);
1131                 if (package_num + 1 > num_sockets) {
1132                         num_sockets = package_num + 1;
1133
1134                         if (num_sockets > 4) {
1135                                 cpuidle_state_table = ivt_cstates_8s;
1136                                 return;
1137                         }
1138                 }
1139         }
1140
1141         if (num_sockets > 2)
1142                 cpuidle_state_table = ivt_cstates_4s;
1143
1144         /* else, 1 and 2 socket systems use default ivt_cstates */
1145 }
1146
1147 /*
1148  * Translate IRTL (Interrupt Response Time Limit) MSR to usec
1149  */
1150
1151 static unsigned int irtl_ns_units[] = {
1152         1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1153
1154 static unsigned long long irtl_2_usec(unsigned long long irtl)
1155 {
1156         unsigned long long ns;
1157
1158         ns = irtl_ns_units[(irtl >> 10) & 0x3];
1159
1160         return div64_u64((irtl & 0x3FF) * ns, 1000);
1161 }
1162 /*
1163  * bxt_idle_state_table_update(void)
1164  *
1165  * On BXT, we trust the IRTL to show the definitive maximum latency
1166  * We use the same value for target_residency.
1167  */
1168 static void bxt_idle_state_table_update(void)
1169 {
1170         unsigned long long msr;
1171
1172         rdmsrl(MSR_PKGC6_IRTL, msr);
1173         if (msr) {
1174                 unsigned int usec = irtl_2_usec(msr);
1175
1176                 bxt_cstates[2].exit_latency = usec;
1177                 bxt_cstates[2].target_residency = usec;
1178         }
1179
1180         rdmsrl(MSR_PKGC7_IRTL, msr);
1181         if (msr) {
1182                 unsigned int usec = irtl_2_usec(msr);
1183
1184                 bxt_cstates[3].exit_latency = usec;
1185                 bxt_cstates[3].target_residency = usec;
1186         }
1187
1188         rdmsrl(MSR_PKGC8_IRTL, msr);
1189         if (msr) {
1190                 unsigned int usec = irtl_2_usec(msr);
1191
1192                 bxt_cstates[4].exit_latency = usec;
1193                 bxt_cstates[4].target_residency = usec;
1194         }
1195
1196         rdmsrl(MSR_PKGC9_IRTL, msr);
1197         if (msr) {
1198                 unsigned int usec = irtl_2_usec(msr);
1199
1200                 bxt_cstates[5].exit_latency = usec;
1201                 bxt_cstates[5].target_residency = usec;
1202         }
1203
1204         rdmsrl(MSR_PKGC10_IRTL, msr);
1205         if (msr) {
1206                 unsigned int usec = irtl_2_usec(msr);
1207
1208                 bxt_cstates[6].exit_latency = usec;
1209                 bxt_cstates[6].target_residency = usec;
1210         }
1211
1212 }
1213 /*
1214  * sklh_idle_state_table_update(void)
1215  *
1216  * On SKL-H (model 0x5e) disable C8 and C9 if:
1217  * C10 is enabled and SGX disabled
1218  */
1219 static void sklh_idle_state_table_update(void)
1220 {
1221         unsigned long long msr;
1222         unsigned int eax, ebx, ecx, edx;
1223
1224
1225         /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1226         if (max_cstate <= 7)
1227                 return;
1228
1229         /* if PC10 not present in CPUID.MWAIT.EDX */
1230         if ((mwait_substates & (0xF << 28)) == 0)
1231                 return;
1232
1233         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
1234
1235         /* PC10 is not enabled in PKG C-state limit */
1236         if ((msr & 0xF) != 8)
1237                 return;
1238
1239         ecx = 0;
1240         cpuid(7, &eax, &ebx, &ecx, &edx);
1241
1242         /* if SGX is present */
1243         if (ebx & (1 << 2)) {
1244
1245                 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1246
1247                 /* if SGX is enabled */
1248                 if (msr & (1 << 18))
1249                         return;
1250         }
1251
1252         skl_cstates[5].disabled = 1;    /* C8-SKL */
1253         skl_cstates[6].disabled = 1;    /* C9-SKL */
1254 }
1255 /*
1256  * intel_idle_state_table_update()
1257  *
1258  * Update the default state_table for this CPU-id
1259  */
1260
1261 static void intel_idle_state_table_update(void)
1262 {
1263         switch (boot_cpu_data.x86_model) {
1264
1265         case INTEL_FAM6_IVYBRIDGE_X:
1266                 ivt_idle_state_table_update();
1267                 break;
1268         case INTEL_FAM6_ATOM_GOLDMONT:
1269                 bxt_idle_state_table_update();
1270                 break;
1271         case INTEL_FAM6_SKYLAKE_DESKTOP:
1272                 sklh_idle_state_table_update();
1273                 break;
1274         }
1275 }
1276
1277 /*
1278  * intel_idle_cpuidle_driver_init()
1279  * allocate, initialize cpuidle_states
1280  */
1281 static void __init intel_idle_cpuidle_driver_init(void)
1282 {
1283         int cstate;
1284         struct cpuidle_driver *drv = &intel_idle_driver;
1285
1286         intel_idle_state_table_update();
1287
1288         drv->state_count = 1;
1289
1290         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1291                 int num_substates, mwait_hint, mwait_cstate;
1292
1293                 if ((cpuidle_state_table[cstate].enter == NULL) &&
1294                     (cpuidle_state_table[cstate].enter_freeze == NULL))
1295                         break;
1296
1297                 if (cstate + 1 > max_cstate) {
1298                         printk(PREFIX "max_cstate %d reached\n",
1299                                 max_cstate);
1300                         break;
1301                 }
1302
1303                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1304                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
1305
1306                 /* number of sub-states for this state in CPUID.MWAIT */
1307                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
1308                                         & MWAIT_SUBSTATE_MASK;
1309
1310                 /* if NO sub-states for this state in CPUID, skip it */
1311                 if (num_substates == 0)
1312                         continue;
1313
1314                 /* if state marked as disabled, skip it */
1315                 if (cpuidle_state_table[cstate].disabled != 0) {
1316                         pr_debug(PREFIX "state %s is disabled",
1317                                 cpuidle_state_table[cstate].name);
1318                         continue;
1319                 }
1320
1321
1322                 if (((mwait_cstate + 1) > 2) &&
1323                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1324                         mark_tsc_unstable("TSC halts in idle"
1325                                         " states deeper than C2");
1326
1327                 drv->states[drv->state_count] = /* structure copy */
1328                         cpuidle_state_table[cstate];
1329
1330                 drv->state_count += 1;
1331         }
1332
1333         if (icpu->byt_auto_demotion_disable_flag) {
1334                 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1335                 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1336         }
1337 }
1338
1339
1340 /*
1341  * intel_idle_cpu_init()
1342  * allocate, initialize, register cpuidle_devices
1343  * @cpu: cpu/core to initialize
1344  */
1345 static int intel_idle_cpu_init(int cpu)
1346 {
1347         struct cpuidle_device *dev;
1348
1349         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1350
1351         dev->cpu = cpu;
1352
1353         if (cpuidle_register_device(dev)) {
1354                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1355                 return -EIO;
1356         }
1357
1358         if (icpu->auto_demotion_disable_flags)
1359                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
1360
1361         if (icpu->disable_promotion_to_c1e)
1362                 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
1363
1364         return 0;
1365 }
1366
1367 static int __init intel_idle_init(void)
1368 {
1369         int retval, i;
1370
1371         /* Do not load intel_idle at all for now if idle= is passed */
1372         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1373                 return -ENODEV;
1374
1375         retval = intel_idle_probe();
1376         if (retval)
1377                 return retval;
1378
1379         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1380         if (intel_idle_cpuidle_devices == NULL)
1381                 return -ENOMEM;
1382
1383         intel_idle_cpuidle_driver_init();
1384         retval = cpuidle_register_driver(&intel_idle_driver);
1385         if (retval) {
1386                 struct cpuidle_driver *drv = cpuidle_get_driver();
1387                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1388                         drv ? drv->name : "none");
1389                 free_percpu(intel_idle_cpuidle_devices);
1390                 return retval;
1391         }
1392
1393         cpu_notifier_register_begin();
1394
1395         for_each_online_cpu(i) {
1396                 retval = intel_idle_cpu_init(i);
1397                 if (retval) {
1398                         intel_idle_cpuidle_devices_uninit();
1399                         cpu_notifier_register_done();
1400                         cpuidle_unregister_driver(&intel_idle_driver);
1401                         free_percpu(intel_idle_cpuidle_devices);
1402                         return retval;
1403                 }
1404         }
1405         __register_cpu_notifier(&cpu_hotplug_notifier);
1406
1407         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
1408                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
1409         else
1410                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
1411
1412         cpu_notifier_register_done();
1413
1414         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
1415                 lapic_timer_reliable_states);
1416
1417         return 0;
1418 }
1419
1420 static void __exit intel_idle_exit(void)
1421 {
1422         struct cpuidle_device *dev;
1423         int i;
1424
1425         cpu_notifier_register_begin();
1426
1427         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
1428                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
1429         __unregister_cpu_notifier(&cpu_hotplug_notifier);
1430
1431         for_each_possible_cpu(i) {
1432                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1433                 cpuidle_unregister_device(dev);
1434         }
1435
1436         cpu_notifier_register_done();
1437
1438         cpuidle_unregister_driver(&intel_idle_driver);
1439         free_percpu(intel_idle_cpuidle_devices);
1440 }
1441
1442 module_init(intel_idle_init);
1443 module_exit(intel_idle_exit);
1444
1445 module_param(max_cstate, int, 0444);
1446
1447 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
1448 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
1449 MODULE_LICENSE("GPL");