2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/events.h>
34 #include <linux/iio/trigger.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37 #include <linux/regmap.h>
39 #include "bmc150-accel.h"
41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
44 #define BMC150_ACCEL_REG_CHIP_ID 0x00
46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
53 #define BMC150_ACCEL_REG_PMU_LPW 0x11
54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
66 /* Default BW: 125Hz */
67 #define BMC150_ACCEL_REG_PMU_BW 0x10
68 #define BMC150_ACCEL_DEF_BW 125
70 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
71 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
73 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
74 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
75 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
76 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
78 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
79 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
80 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
81 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
83 #define BMC150_ACCEL_REG_INT_EN_0 0x16
84 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
85 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
86 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
88 #define BMC150_ACCEL_REG_INT_EN_1 0x17
89 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
90 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
91 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
93 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
94 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
96 #define BMC150_ACCEL_REG_INT_5 0x27
97 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
99 #define BMC150_ACCEL_REG_INT_6 0x28
100 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
102 /* Slope duration in terms of number of samples */
103 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
104 /* in terms of multiples of g's/LSB, based on range */
105 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
107 #define BMC150_ACCEL_REG_XOUT_L 0x02
109 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
111 /* Sleep Duration values */
112 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
113 #define BMC150_ACCEL_SLEEP_1_MS 0x06
114 #define BMC150_ACCEL_SLEEP_2_MS 0x07
115 #define BMC150_ACCEL_SLEEP_4_MS 0x08
116 #define BMC150_ACCEL_SLEEP_6_MS 0x09
117 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
118 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
119 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
120 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
121 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
122 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
124 #define BMC150_ACCEL_REG_TEMP 0x08
125 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
127 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
128 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
130 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
131 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
132 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
133 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
134 #define BMC150_ACCEL_FIFO_LENGTH 32
136 enum bmc150_accel_axis {
143 enum bmc150_power_modes {
144 BMC150_ACCEL_SLEEP_MODE_NORMAL,
145 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
146 BMC150_ACCEL_SLEEP_MODE_LPM,
147 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
150 struct bmc150_scale_info {
155 struct bmc150_accel_chip_info {
158 const struct iio_chan_spec *channels;
160 const struct bmc150_scale_info scale_table[4];
163 struct bmc150_accel_interrupt {
164 const struct bmc150_accel_interrupt_info *info;
168 struct bmc150_accel_trigger {
169 struct bmc150_accel_data *data;
170 struct iio_trigger *indio_trig;
171 int (*setup)(struct bmc150_accel_trigger *t, bool state);
176 enum bmc150_accel_interrupt_id {
177 BMC150_ACCEL_INT_DATA_READY,
178 BMC150_ACCEL_INT_ANY_MOTION,
179 BMC150_ACCEL_INT_WATERMARK,
180 BMC150_ACCEL_INTERRUPTS,
183 enum bmc150_accel_trigger_id {
184 BMC150_ACCEL_TRIGGER_DATA_READY,
185 BMC150_ACCEL_TRIGGER_ANY_MOTION,
186 BMC150_ACCEL_TRIGGERS,
189 struct bmc150_accel_data {
190 struct regmap *regmap;
192 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
193 atomic_t active_intr;
194 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
196 u8 fifo_mode, watermark;
203 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
204 const struct bmc150_accel_chip_info *chip_info;
207 static const struct {
211 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
220 static const struct {
223 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
232 static const struct {
235 } bmc150_accel_sleep_value_table[] = { {0, 0},
236 {500, BMC150_ACCEL_SLEEP_500_MICRO},
237 {1000, BMC150_ACCEL_SLEEP_1_MS},
238 {2000, BMC150_ACCEL_SLEEP_2_MS},
239 {4000, BMC150_ACCEL_SLEEP_4_MS},
240 {6000, BMC150_ACCEL_SLEEP_6_MS},
241 {10000, BMC150_ACCEL_SLEEP_10_MS},
242 {25000, BMC150_ACCEL_SLEEP_25_MS},
243 {50000, BMC150_ACCEL_SLEEP_50_MS},
244 {100000, BMC150_ACCEL_SLEEP_100_MS},
245 {500000, BMC150_ACCEL_SLEEP_500_MS},
246 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
248 const struct regmap_config bmc150_regmap_conf = {
251 .max_register = 0x3f,
253 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
255 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
256 enum bmc150_power_modes mode,
259 struct device *dev = regmap_get_device(data->regmap);
266 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
268 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
271 bmc150_accel_sleep_value_table[i].reg_value;
280 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
281 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
283 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
285 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
287 dev_err(dev, "Error writing reg_pmu_lpw\n");
294 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
300 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
301 if (bmc150_accel_samp_freq_table[i].val == val &&
302 bmc150_accel_samp_freq_table[i].val2 == val2) {
303 ret = regmap_write(data->regmap,
304 BMC150_ACCEL_REG_PMU_BW,
305 bmc150_accel_samp_freq_table[i].bw_bits);
310 bmc150_accel_samp_freq_table[i].bw_bits;
318 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
320 struct device *dev = regmap_get_device(data->regmap);
323 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
326 dev_err(dev, "Error writing reg_int_6\n");
330 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
331 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
333 dev_err(dev, "Error updating reg_int_5\n");
337 dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres,
343 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
347 return bmc150_accel_update_slope(t->data);
352 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
357 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
358 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
359 *val = bmc150_accel_samp_freq_table[i].val;
360 *val2 = bmc150_accel_samp_freq_table[i].val2;
361 return IIO_VAL_INT_PLUS_MICRO;
369 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
373 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
374 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
375 return bmc150_accel_sample_upd_time[i].msec;
378 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
381 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
383 struct device *dev = regmap_get_device(data->regmap);
387 ret = pm_runtime_get_sync(dev);
389 pm_runtime_mark_last_busy(dev);
390 ret = pm_runtime_put_autosuspend(dev);
395 "Failed: bmc150_accel_set_power_state for %d\n", on);
397 pm_runtime_put_noidle(dev);
405 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
411 static const struct bmc150_accel_interrupt_info {
416 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
417 { /* data ready interrupt */
418 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
419 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
420 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
421 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
423 { /* motion interrupt */
424 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
425 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
426 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
427 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
428 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
429 BMC150_ACCEL_INT_EN_BIT_SLP_Z
431 { /* fifo watermark interrupt */
432 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
433 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
434 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
435 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
439 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
440 struct bmc150_accel_data *data)
444 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
445 data->interrupts[i].info = &bmc150_accel_interrupts[i];
448 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
451 struct device *dev = regmap_get_device(data->regmap);
452 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
453 const struct bmc150_accel_interrupt_info *info = intr->info;
457 if (atomic_inc_return(&intr->users) > 1)
460 if (atomic_dec_return(&intr->users) > 0)
465 * We will expect the enable and disable to do operation in reverse
466 * order. This will happen here anyway, as our resume operation uses
467 * sync mode runtime pm calls. The suspend operation will be delayed
468 * by autosuspend delay.
469 * So the disable operation will still happen in reverse order of
470 * enable operation. When runtime pm is disabled the mode is always on,
471 * so sequence doesn't matter.
473 ret = bmc150_accel_set_power_state(data, state);
477 /* map the interrupt to the appropriate pins */
478 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
479 (state ? info->map_bitmask : 0));
481 dev_err(dev, "Error updating reg_int_map\n");
482 goto out_fix_power_state;
485 /* enable/disable the interrupt */
486 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
487 (state ? info->en_bitmask : 0));
489 dev_err(dev, "Error updating reg_int_en\n");
490 goto out_fix_power_state;
494 atomic_inc(&data->active_intr);
496 atomic_dec(&data->active_intr);
501 bmc150_accel_set_power_state(data, false);
505 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
507 struct device *dev = regmap_get_device(data->regmap);
510 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
511 if (data->chip_info->scale_table[i].scale == val) {
512 ret = regmap_write(data->regmap,
513 BMC150_ACCEL_REG_PMU_RANGE,
514 data->chip_info->scale_table[i].reg_range);
516 dev_err(dev, "Error writing pmu_range\n");
520 data->range = data->chip_info->scale_table[i].reg_range;
528 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
530 struct device *dev = regmap_get_device(data->regmap);
534 mutex_lock(&data->mutex);
536 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
538 dev_err(dev, "Error reading reg_temp\n");
539 mutex_unlock(&data->mutex);
542 *val = sign_extend32(value, 7);
544 mutex_unlock(&data->mutex);
549 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
550 struct iio_chan_spec const *chan,
553 struct device *dev = regmap_get_device(data->regmap);
555 int axis = chan->scan_index;
558 mutex_lock(&data->mutex);
559 ret = bmc150_accel_set_power_state(data, true);
561 mutex_unlock(&data->mutex);
565 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
566 &raw_val, sizeof(raw_val));
568 dev_err(dev, "Error reading axis %d\n", axis);
569 bmc150_accel_set_power_state(data, false);
570 mutex_unlock(&data->mutex);
573 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
574 chan->scan_type.realbits - 1);
575 ret = bmc150_accel_set_power_state(data, false);
576 mutex_unlock(&data->mutex);
583 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
584 struct iio_chan_spec const *chan,
585 int *val, int *val2, long mask)
587 struct bmc150_accel_data *data = iio_priv(indio_dev);
591 case IIO_CHAN_INFO_RAW:
592 switch (chan->type) {
594 return bmc150_accel_get_temp(data, val);
596 if (iio_buffer_enabled(indio_dev))
599 return bmc150_accel_get_axis(data, chan, val);
603 case IIO_CHAN_INFO_OFFSET:
604 if (chan->type == IIO_TEMP) {
605 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
610 case IIO_CHAN_INFO_SCALE:
612 switch (chan->type) {
615 return IIO_VAL_INT_PLUS_MICRO;
619 const struct bmc150_scale_info *si;
620 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
622 for (i = 0; i < st_size; ++i) {
623 si = &data->chip_info->scale_table[i];
624 if (si->reg_range == data->range) {
626 return IIO_VAL_INT_PLUS_MICRO;
634 case IIO_CHAN_INFO_SAMP_FREQ:
635 mutex_lock(&data->mutex);
636 ret = bmc150_accel_get_bw(data, val, val2);
637 mutex_unlock(&data->mutex);
644 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
645 struct iio_chan_spec const *chan,
646 int val, int val2, long mask)
648 struct bmc150_accel_data *data = iio_priv(indio_dev);
652 case IIO_CHAN_INFO_SAMP_FREQ:
653 mutex_lock(&data->mutex);
654 ret = bmc150_accel_set_bw(data, val, val2);
655 mutex_unlock(&data->mutex);
657 case IIO_CHAN_INFO_SCALE:
661 mutex_lock(&data->mutex);
662 ret = bmc150_accel_set_scale(data, val2);
663 mutex_unlock(&data->mutex);
672 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
673 const struct iio_chan_spec *chan,
674 enum iio_event_type type,
675 enum iio_event_direction dir,
676 enum iio_event_info info,
679 struct bmc150_accel_data *data = iio_priv(indio_dev);
683 case IIO_EV_INFO_VALUE:
684 *val = data->slope_thres;
686 case IIO_EV_INFO_PERIOD:
687 *val = data->slope_dur;
696 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
697 const struct iio_chan_spec *chan,
698 enum iio_event_type type,
699 enum iio_event_direction dir,
700 enum iio_event_info info,
703 struct bmc150_accel_data *data = iio_priv(indio_dev);
705 if (data->ev_enable_state)
709 case IIO_EV_INFO_VALUE:
710 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
712 case IIO_EV_INFO_PERIOD:
713 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
722 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
723 const struct iio_chan_spec *chan,
724 enum iio_event_type type,
725 enum iio_event_direction dir)
727 struct bmc150_accel_data *data = iio_priv(indio_dev);
729 return data->ev_enable_state;
732 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
733 const struct iio_chan_spec *chan,
734 enum iio_event_type type,
735 enum iio_event_direction dir,
738 struct bmc150_accel_data *data = iio_priv(indio_dev);
741 if (state == data->ev_enable_state)
744 mutex_lock(&data->mutex);
746 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
749 mutex_unlock(&data->mutex);
753 data->ev_enable_state = state;
754 mutex_unlock(&data->mutex);
759 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
760 struct iio_trigger *trig)
762 struct bmc150_accel_data *data = iio_priv(indio_dev);
765 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
766 if (data->triggers[i].indio_trig == trig)
773 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
774 struct device_attribute *attr,
777 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
778 struct bmc150_accel_data *data = iio_priv(indio_dev);
781 mutex_lock(&data->mutex);
782 wm = data->watermark;
783 mutex_unlock(&data->mutex);
785 return sprintf(buf, "%d\n", wm);
788 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
789 struct device_attribute *attr,
792 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
793 struct bmc150_accel_data *data = iio_priv(indio_dev);
796 mutex_lock(&data->mutex);
797 state = data->fifo_mode;
798 mutex_unlock(&data->mutex);
800 return sprintf(buf, "%d\n", state);
803 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
804 static IIO_CONST_ATTR(hwfifo_watermark_max,
805 __stringify(BMC150_ACCEL_FIFO_LENGTH));
806 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
807 bmc150_accel_get_fifo_state, NULL, 0);
808 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
809 bmc150_accel_get_fifo_watermark, NULL, 0);
811 static const struct attribute *bmc150_accel_fifo_attributes[] = {
812 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
813 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
814 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
815 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
819 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
821 struct bmc150_accel_data *data = iio_priv(indio_dev);
823 if (val > BMC150_ACCEL_FIFO_LENGTH)
824 val = BMC150_ACCEL_FIFO_LENGTH;
826 mutex_lock(&data->mutex);
827 data->watermark = val;
828 mutex_unlock(&data->mutex);
834 * We must read at least one full frame in one burst, otherwise the rest of the
835 * frame data is discarded.
837 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
838 char *buffer, int samples)
840 struct device *dev = regmap_get_device(data->regmap);
841 int sample_length = 3 * 2;
843 int total_length = samples * sample_length;
845 size_t step = regmap_get_raw_read_max(data->regmap);
847 if (!step || step > total_length)
849 else if (step < total_length)
850 step = sample_length;
853 * Seems we have a bus with size limitation so we have to execute
856 for (i = 0; i < total_length; i += step) {
857 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
865 "Error transferring data from fifo in single steps of %zu\n",
871 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
872 unsigned samples, bool irq)
874 struct bmc150_accel_data *data = iio_priv(indio_dev);
875 struct device *dev = regmap_get_device(data->regmap);
878 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
880 uint64_t sample_period;
883 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
885 dev_err(dev, "Error reading reg_fifo_status\n");
895 * If we getting called from IRQ handler we know the stored timestamp is
896 * fairly accurate for the last stored sample. Otherwise, if we are
897 * called as a result of a read operation from userspace and hence
898 * before the watermark interrupt was triggered, take a timestamp
899 * now. We can fall anywhere in between two samples so the error in this
900 * case is at most one sample period.
903 data->old_timestamp = data->timestamp;
904 data->timestamp = iio_get_time_ns(indio_dev);
908 * Approximate timestamps for each of the sample based on the sampling
909 * frequency, timestamp for last sample and number of samples.
911 * Note that we can't use the current bandwidth settings to compute the
912 * sample period because the sample rate varies with the device
913 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
914 * small variation adds when we store a large number of samples and
915 * creates significant jitter between the last and first samples in
916 * different batches (e.g. 32ms vs 21ms).
918 * To avoid this issue we compute the actual sample period ourselves
919 * based on the timestamp delta between the last two flush operations.
921 sample_period = (data->timestamp - data->old_timestamp);
922 do_div(sample_period, count);
923 tstamp = data->timestamp - (count - 1) * sample_period;
925 if (samples && count > samples)
928 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
933 * Ideally we want the IIO core to handle the demux when running in fifo
934 * mode but not when running in triggered buffer mode. Unfortunately
935 * this does not seem to be possible, so stick with driver demux for
938 for (i = 0; i < count; i++) {
943 for_each_set_bit(bit, indio_dev->active_scan_mask,
944 indio_dev->masklength)
945 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
947 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
949 tstamp += sample_period;
955 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
957 struct bmc150_accel_data *data = iio_priv(indio_dev);
960 mutex_lock(&data->mutex);
961 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
962 mutex_unlock(&data->mutex);
967 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
968 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
970 static struct attribute *bmc150_accel_attributes[] = {
971 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
975 static const struct attribute_group bmc150_accel_attrs_group = {
976 .attrs = bmc150_accel_attributes,
979 static const struct iio_event_spec bmc150_accel_event = {
980 .type = IIO_EV_TYPE_ROC,
981 .dir = IIO_EV_DIR_EITHER,
982 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
983 BIT(IIO_EV_INFO_ENABLE) |
984 BIT(IIO_EV_INFO_PERIOD)
987 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
990 .channel2 = IIO_MOD_##_axis, \
991 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
992 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
993 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
994 .scan_index = AXIS_##_axis, \
997 .realbits = (bits), \
999 .shift = 16 - (bits), \
1000 .endianness = IIO_LE, \
1002 .event_spec = &bmc150_accel_event, \
1003 .num_event_specs = 1 \
1006 #define BMC150_ACCEL_CHANNELS(bits) { \
1009 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1010 BIT(IIO_CHAN_INFO_SCALE) | \
1011 BIT(IIO_CHAN_INFO_OFFSET), \
1014 BMC150_ACCEL_CHANNEL(X, bits), \
1015 BMC150_ACCEL_CHANNEL(Y, bits), \
1016 BMC150_ACCEL_CHANNEL(Z, bits), \
1017 IIO_CHAN_SOFT_TIMESTAMP(3), \
1020 static const struct iio_chan_spec bma222e_accel_channels[] =
1021 BMC150_ACCEL_CHANNELS(8);
1022 static const struct iio_chan_spec bma250e_accel_channels[] =
1023 BMC150_ACCEL_CHANNELS(10);
1024 static const struct iio_chan_spec bmc150_accel_channels[] =
1025 BMC150_ACCEL_CHANNELS(12);
1026 static const struct iio_chan_spec bma280_accel_channels[] =
1027 BMC150_ACCEL_CHANNELS(14);
1029 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1033 .channels = bmc150_accel_channels,
1034 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1035 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1036 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1037 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1038 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1043 .channels = bmc150_accel_channels,
1044 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1045 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1046 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1047 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1048 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1053 .channels = bmc150_accel_channels,
1054 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1055 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1056 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1057 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1058 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1063 .channels = bma250e_accel_channels,
1064 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1065 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1066 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1067 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1068 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1073 .channels = bma222e_accel_channels,
1074 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1075 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1076 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1077 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1078 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1083 .channels = bma280_accel_channels,
1084 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1085 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1086 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1087 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1088 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1092 static const struct iio_info bmc150_accel_info = {
1093 .attrs = &bmc150_accel_attrs_group,
1094 .read_raw = bmc150_accel_read_raw,
1095 .write_raw = bmc150_accel_write_raw,
1096 .read_event_value = bmc150_accel_read_event,
1097 .write_event_value = bmc150_accel_write_event,
1098 .write_event_config = bmc150_accel_write_event_config,
1099 .read_event_config = bmc150_accel_read_event_config,
1100 .driver_module = THIS_MODULE,
1103 static const struct iio_info bmc150_accel_info_fifo = {
1104 .attrs = &bmc150_accel_attrs_group,
1105 .read_raw = bmc150_accel_read_raw,
1106 .write_raw = bmc150_accel_write_raw,
1107 .read_event_value = bmc150_accel_read_event,
1108 .write_event_value = bmc150_accel_write_event,
1109 .write_event_config = bmc150_accel_write_event_config,
1110 .read_event_config = bmc150_accel_read_event_config,
1111 .validate_trigger = bmc150_accel_validate_trigger,
1112 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1113 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1114 .driver_module = THIS_MODULE,
1117 static const unsigned long bmc150_accel_scan_masks[] = {
1118 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1121 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1123 struct iio_poll_func *pf = p;
1124 struct iio_dev *indio_dev = pf->indio_dev;
1125 struct bmc150_accel_data *data = iio_priv(indio_dev);
1128 mutex_lock(&data->mutex);
1129 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1130 data->buffer, AXIS_MAX * 2);
1131 mutex_unlock(&data->mutex);
1135 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1138 iio_trigger_notify_done(indio_dev->trig);
1143 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1145 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1146 struct bmc150_accel_data *data = t->data;
1147 struct device *dev = regmap_get_device(data->regmap);
1150 /* new data interrupts don't need ack */
1151 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1154 mutex_lock(&data->mutex);
1155 /* clear any latched interrupt */
1156 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1157 BMC150_ACCEL_INT_MODE_LATCH_INT |
1158 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1159 mutex_unlock(&data->mutex);
1161 dev_err(dev, "Error writing reg_int_rst_latch\n");
1168 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1171 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1172 struct bmc150_accel_data *data = t->data;
1175 mutex_lock(&data->mutex);
1177 if (t->enabled == state) {
1178 mutex_unlock(&data->mutex);
1183 ret = t->setup(t, state);
1185 mutex_unlock(&data->mutex);
1190 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1192 mutex_unlock(&data->mutex);
1198 mutex_unlock(&data->mutex);
1203 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1204 .set_trigger_state = bmc150_accel_trigger_set_state,
1205 .try_reenable = bmc150_accel_trig_try_reen,
1206 .owner = THIS_MODULE,
1209 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1211 struct bmc150_accel_data *data = iio_priv(indio_dev);
1212 struct device *dev = regmap_get_device(data->regmap);
1217 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1219 dev_err(dev, "Error reading reg_int_status_2\n");
1223 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1224 dir = IIO_EV_DIR_FALLING;
1226 dir = IIO_EV_DIR_RISING;
1228 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1229 iio_push_event(indio_dev,
1230 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1238 iio_push_event(indio_dev,
1239 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1247 iio_push_event(indio_dev,
1248 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1258 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1260 struct iio_dev *indio_dev = private;
1261 struct bmc150_accel_data *data = iio_priv(indio_dev);
1262 struct device *dev = regmap_get_device(data->regmap);
1266 mutex_lock(&data->mutex);
1268 if (data->fifo_mode) {
1269 ret = __bmc150_accel_fifo_flush(indio_dev,
1270 BMC150_ACCEL_FIFO_LENGTH, true);
1275 if (data->ev_enable_state) {
1276 ret = bmc150_accel_handle_roc_event(indio_dev);
1282 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1283 BMC150_ACCEL_INT_MODE_LATCH_INT |
1284 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1286 dev_err(dev, "Error writing reg_int_rst_latch\n");
1293 mutex_unlock(&data->mutex);
1298 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1300 struct iio_dev *indio_dev = private;
1301 struct bmc150_accel_data *data = iio_priv(indio_dev);
1305 data->old_timestamp = data->timestamp;
1306 data->timestamp = iio_get_time_ns(indio_dev);
1308 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1309 if (data->triggers[i].enabled) {
1310 iio_trigger_poll(data->triggers[i].indio_trig);
1316 if (data->ev_enable_state || data->fifo_mode)
1317 return IRQ_WAKE_THREAD;
1325 static const struct {
1328 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1329 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1336 .name = "%s-any-motion-dev%d",
1337 .setup = bmc150_accel_any_motion_setup,
1341 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1346 for (i = from; i >= 0; i--) {
1347 if (data->triggers[i].indio_trig) {
1348 iio_trigger_unregister(data->triggers[i].indio_trig);
1349 data->triggers[i].indio_trig = NULL;
1354 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1355 struct bmc150_accel_data *data)
1357 struct device *dev = regmap_get_device(data->regmap);
1360 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1361 struct bmc150_accel_trigger *t = &data->triggers[i];
1363 t->indio_trig = devm_iio_trigger_alloc(dev,
1364 bmc150_accel_triggers[i].name,
1367 if (!t->indio_trig) {
1372 t->indio_trig->dev.parent = dev;
1373 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1374 t->intr = bmc150_accel_triggers[i].intr;
1376 t->setup = bmc150_accel_triggers[i].setup;
1377 iio_trigger_set_drvdata(t->indio_trig, t);
1379 ret = iio_trigger_register(t->indio_trig);
1385 bmc150_accel_unregister_triggers(data, i - 1);
1390 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1391 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1392 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1394 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1396 struct device *dev = regmap_get_device(data->regmap);
1397 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1400 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1402 dev_err(dev, "Error writing reg_fifo_config1\n");
1406 if (!data->fifo_mode)
1409 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1412 dev_err(dev, "Error writing reg_fifo_config0\n");
1417 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1419 struct bmc150_accel_data *data = iio_priv(indio_dev);
1421 return bmc150_accel_set_power_state(data, true);
1424 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1426 struct bmc150_accel_data *data = iio_priv(indio_dev);
1429 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1430 return iio_triggered_buffer_postenable(indio_dev);
1432 mutex_lock(&data->mutex);
1434 if (!data->watermark)
1437 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1442 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1444 ret = bmc150_accel_fifo_set_mode(data);
1446 data->fifo_mode = 0;
1447 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1452 mutex_unlock(&data->mutex);
1457 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1459 struct bmc150_accel_data *data = iio_priv(indio_dev);
1461 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1462 return iio_triggered_buffer_predisable(indio_dev);
1464 mutex_lock(&data->mutex);
1466 if (!data->fifo_mode)
1469 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1470 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1471 data->fifo_mode = 0;
1472 bmc150_accel_fifo_set_mode(data);
1475 mutex_unlock(&data->mutex);
1480 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1482 struct bmc150_accel_data *data = iio_priv(indio_dev);
1484 return bmc150_accel_set_power_state(data, false);
1487 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1488 .preenable = bmc150_accel_buffer_preenable,
1489 .postenable = bmc150_accel_buffer_postenable,
1490 .predisable = bmc150_accel_buffer_predisable,
1491 .postdisable = bmc150_accel_buffer_postdisable,
1494 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1496 struct device *dev = regmap_get_device(data->regmap);
1500 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1502 dev_err(dev, "Error: Reading chip id\n");
1506 dev_dbg(dev, "Chip Id %x\n", val);
1507 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1508 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1509 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1514 if (!data->chip_info) {
1515 dev_err(dev, "Invalid chip %x\n", val);
1519 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1524 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1528 /* Set Default Range */
1529 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1530 BMC150_ACCEL_DEF_RANGE_4G);
1532 dev_err(dev, "Error writing reg_pmu_range\n");
1536 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1538 /* Set default slope duration and thresholds */
1539 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1540 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1541 ret = bmc150_accel_update_slope(data);
1545 /* Set default as latched interrupts */
1546 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1547 BMC150_ACCEL_INT_MODE_LATCH_INT |
1548 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1550 dev_err(dev, "Error writing reg_int_rst_latch\n");
1557 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1558 const char *name, bool block_supported)
1560 struct bmc150_accel_data *data;
1561 struct iio_dev *indio_dev;
1564 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1568 data = iio_priv(indio_dev);
1569 dev_set_drvdata(dev, indio_dev);
1572 data->regmap = regmap;
1574 ret = bmc150_accel_chip_init(data);
1578 mutex_init(&data->mutex);
1580 indio_dev->dev.parent = dev;
1581 indio_dev->channels = data->chip_info->channels;
1582 indio_dev->num_channels = data->chip_info->num_channels;
1583 indio_dev->name = name ? name : data->chip_info->name;
1584 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1585 indio_dev->modes = INDIO_DIRECT_MODE;
1586 indio_dev->info = &bmc150_accel_info;
1588 ret = iio_triggered_buffer_setup(indio_dev,
1589 &iio_pollfunc_store_time,
1590 bmc150_accel_trigger_handler,
1591 &bmc150_accel_buffer_ops);
1593 dev_err(dev, "Failed: iio triggered buffer setup\n");
1597 if (data->irq > 0) {
1598 ret = devm_request_threaded_irq(
1600 bmc150_accel_irq_handler,
1601 bmc150_accel_irq_thread_handler,
1602 IRQF_TRIGGER_RISING,
1603 BMC150_ACCEL_IRQ_NAME,
1606 goto err_buffer_cleanup;
1609 * Set latched mode interrupt. While certain interrupts are
1610 * non-latched regardless of this settings (e.g. new data) we
1611 * want to use latch mode when we can to prevent interrupt
1614 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1615 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1617 dev_err(dev, "Error writing reg_int_rst_latch\n");
1618 goto err_buffer_cleanup;
1621 bmc150_accel_interrupts_setup(indio_dev, data);
1623 ret = bmc150_accel_triggers_setup(indio_dev, data);
1625 goto err_buffer_cleanup;
1627 if (block_supported) {
1628 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1629 indio_dev->info = &bmc150_accel_info_fifo;
1630 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1634 ret = pm_runtime_set_active(dev);
1636 goto err_trigger_unregister;
1638 pm_runtime_enable(dev);
1639 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1640 pm_runtime_use_autosuspend(dev);
1642 ret = iio_device_register(indio_dev);
1644 dev_err(dev, "Unable to register iio device\n");
1645 goto err_trigger_unregister;
1650 err_trigger_unregister:
1651 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1653 iio_triggered_buffer_cleanup(indio_dev);
1657 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1659 int bmc150_accel_core_remove(struct device *dev)
1661 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1662 struct bmc150_accel_data *data = iio_priv(indio_dev);
1664 iio_device_unregister(indio_dev);
1666 pm_runtime_disable(dev);
1667 pm_runtime_set_suspended(dev);
1668 pm_runtime_put_noidle(dev);
1670 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1672 iio_triggered_buffer_cleanup(indio_dev);
1674 mutex_lock(&data->mutex);
1675 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1676 mutex_unlock(&data->mutex);
1680 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1682 #ifdef CONFIG_PM_SLEEP
1683 static int bmc150_accel_suspend(struct device *dev)
1685 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1686 struct bmc150_accel_data *data = iio_priv(indio_dev);
1688 mutex_lock(&data->mutex);
1689 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1690 mutex_unlock(&data->mutex);
1695 static int bmc150_accel_resume(struct device *dev)
1697 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1698 struct bmc150_accel_data *data = iio_priv(indio_dev);
1700 mutex_lock(&data->mutex);
1701 if (atomic_read(&data->active_intr))
1702 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1703 bmc150_accel_fifo_set_mode(data);
1704 mutex_unlock(&data->mutex);
1711 static int bmc150_accel_runtime_suspend(struct device *dev)
1713 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1714 struct bmc150_accel_data *data = iio_priv(indio_dev);
1717 dev_dbg(dev, __func__);
1718 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1725 static int bmc150_accel_runtime_resume(struct device *dev)
1727 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1728 struct bmc150_accel_data *data = iio_priv(indio_dev);
1732 dev_dbg(dev, __func__);
1734 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1737 ret = bmc150_accel_fifo_set_mode(data);
1741 sleep_val = bmc150_accel_get_startup_times(data);
1743 usleep_range(sleep_val * 1000, 20000);
1745 msleep_interruptible(sleep_val);
1751 const struct dev_pm_ops bmc150_accel_pm_ops = {
1752 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1753 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1754 bmc150_accel_runtime_resume, NULL)
1756 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1758 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1759 MODULE_LICENSE("GPL v2");
1760 MODULE_DESCRIPTION("BMC150 accelerometer driver");