drivers/infiniband/hw/hfi1/init.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <linux/pci.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/vmalloc.h>
  51 #include <linux/delay.h>
  52 #include <linux/idr.h>
  53 #include <linux/module.h>
  54 #include <linux/printk.h>
  55 #include <linux/hrtimer.h>
  56 #include <rdma/rdma_vt.h>
  57
  58 #include "hfi.h"
  59 #include "device.h"
  60 #include "common.h"
  61 #include "trace.h"
  62 #include "mad.h"
  63 #include "sdma.h"
  64 #include "debugfs.h"
  65 #include "verbs.h"
  66 #include "aspm.h"
  67 #include "affinity.h"
  68
  69 #undef pr_fmt
  70 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
  71
  72 /*
  73  * min buffers we want to have per context, after driver
  74  */
  75 #define HFI1_MIN_USER_CTXT_BUFCNT 7
  76
  77 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
  78 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
  79 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
  80 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
  81
  82 /*
  83  * Number of user receive contexts we are configured to use (to allow for more
  84  * pio buffers per ctxt, etc.)  Zero means use one user context per CPU.
  85  */
  86 int num_user_contexts = -1;
  87 module_param_named(num_user_contexts, num_user_contexts, uint, S_IRUGO);
  88 MODULE_PARM_DESC(
  89         num_user_contexts, "Set max number of user contexts to use");
  90
  91 uint krcvqs[RXE_NUM_DATA_VL];
  92 int krcvqsset;
  93 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
  94 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
  95
  96 /* computed based on above array */
  97 unsigned n_krcvqs;
  98
  99 static unsigned hfi1_rcvarr_split = 25;
 100 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
 101 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
 102
 103 static uint eager_buffer_size = (2 << 20); /* 2MB */
 104 module_param(eager_buffer_size, uint, S_IRUGO);
 105 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 2MB");
 106
 107 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
 108 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
 109 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
 110
 111 static uint hfi1_hdrq_entsize = 32;
 112 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, S_IRUGO);
 113 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
 114
 115 unsigned int user_credit_return_threshold = 33; /* default is 33% */
 116 module_param(user_credit_return_threshold, uint, S_IRUGO);
 117 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
 118
 119 static inline u64 encode_rcv_header_entry_size(u16);
 120
 121 static struct idr hfi1_unit_table;
 122 u32 hfi1_cpulist_count;
 123 unsigned long *hfi1_cpulist;
 124
 125 /*
 126  * Common code for creating the receive context array.
 127  */
 128 int hfi1_create_ctxts(struct hfi1_devdata *dd)
 129 {
 130         unsigned i;
 131         int ret;
 132
 133         /* Control context has to be always 0 */
 134         BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
 135
 136         dd->rcd = kzalloc_node(dd->num_rcv_contexts * sizeof(*dd->rcd),
 137                                GFP_KERNEL, dd->node);
 138         if (!dd->rcd)
 139                 goto nomem;
 140
 141         /* create one or more kernel contexts */
 142         for (i = 0; i < dd->first_user_ctxt; ++i) {
 143                 struct hfi1_pportdata *ppd;
 144                 struct hfi1_ctxtdata *rcd;
 145
 146                 ppd = dd->pport + (i % dd->num_pports);
 147                 rcd = hfi1_create_ctxtdata(ppd, i, dd->node);
 148                 if (!rcd) {
 149                         dd_dev_err(dd,
 150                                    "Unable to allocate kernel receive context, failing\n");
 151                         goto nomem;
 152                 }
 153                 /*
 154                  * Set up the kernel context flags here and now because they
 155                  * use default values for all receive side memories.  User
 156                  * contexts will be handled as they are created.
 157                  */
 158                 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
 159                         HFI1_CAP_KGET(NODROP_RHQ_FULL) |
 160                         HFI1_CAP_KGET(NODROP_EGR_FULL) |
 161                         HFI1_CAP_KGET(DMA_RTAIL);
 162
 163                 /* Control context must use DMA_RTAIL */
 164                 if (rcd->ctxt == HFI1_CTRL_CTXT)
 165                         rcd->flags |= HFI1_CAP_DMA_RTAIL;
 166                 rcd->seq_cnt = 1;
 167
 168                 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
 169                 if (!rcd->sc) {
 170                         dd_dev_err(dd,
 171                                    "Unable to allocate kernel send context, failing\n");
 172                         dd->rcd[rcd->ctxt] = NULL;
 173                         hfi1_free_ctxtdata(dd, rcd);
 174                         goto nomem;
 175                 }
 176
 177                 ret = hfi1_init_ctxt(rcd->sc);
 178                 if (ret < 0) {
 179                         dd_dev_err(dd,
 180                                    "Failed to setup kernel receive context, failing\n");
 181                         sc_free(rcd->sc);
 182                         dd->rcd[rcd->ctxt] = NULL;
 183                         hfi1_free_ctxtdata(dd, rcd);
 184                         ret = -EFAULT;
 185                         goto bail;
 186                 }
 187         }
 188
 189         /*
 190          * Initialize aspm, to be done after gen3 transition and setting up
 191          * contexts and before enabling interrupts
 192          */
 193         aspm_init(dd);
 194
 195         return 0;
 196 nomem:
 197         ret = -ENOMEM;
 198 bail:
 199         kfree(dd->rcd);
 200         dd->rcd = NULL;
 201         return ret;
 202 }
 203
 204 /*
 205  * Common code for user and kernel context setup.
 206  */
 207 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt,
 208                                            int numa)
 209 {
 210         struct hfi1_devdata *dd = ppd->dd;
 211         struct hfi1_ctxtdata *rcd;
 212         unsigned kctxt_ngroups = 0;
 213         u32 base;
 214
 215         if (dd->rcv_entries.nctxt_extra >
 216             dd->num_rcv_contexts - dd->first_user_ctxt)
 217                 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
 218                                  (dd->num_rcv_contexts - dd->first_user_ctxt));
 219         rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
 220         if (rcd) {
 221                 u32 rcvtids, max_entries;
 222
 223                 hfi1_cdbg(PROC, "setting up context %u\n", ctxt);
 224
 225                 INIT_LIST_HEAD(&rcd->qp_wait_list);
 226                 rcd->ppd = ppd;
 227                 rcd->dd = dd;
 228                 rcd->cnt = 1;
 229                 rcd->ctxt = ctxt;
 230                 dd->rcd[ctxt] = rcd;
 231                 rcd->numa_id = numa;
 232                 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
 233
 234                 mutex_init(&rcd->exp_lock);
 235
 236                 /*
 237                  * Calculate the context's RcvArray entry starting point.
 238                  * We do this here because we have to take into account all
 239                  * the RcvArray entries that previous context would have
 240                  * taken and we have to account for any extra groups
 241                  * assigned to the kernel or user contexts.
 242                  */
 243                 if (ctxt < dd->first_user_ctxt) {
 244                         if (ctxt < kctxt_ngroups) {
 245                                 base = ctxt * (dd->rcv_entries.ngroups + 1);
 246                                 rcd->rcv_array_groups++;
 247                         } else
 248                                 base = kctxt_ngroups +
 249                                         (ctxt * dd->rcv_entries.ngroups);
 250                 } else {
 251                         u16 ct = ctxt - dd->first_user_ctxt;
 252
 253                         base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
 254                                 kctxt_ngroups);
 255                         if (ct < dd->rcv_entries.nctxt_extra) {
 256                                 base += ct * (dd->rcv_entries.ngroups + 1);
 257                                 rcd->rcv_array_groups++;
 258                         } else
 259                                 base += dd->rcv_entries.nctxt_extra +
 260                                         (ct * dd->rcv_entries.ngroups);
 261                 }
 262                 rcd->eager_base = base * dd->rcv_entries.group_size;
 263
 264                 /* Validate and initialize Rcv Hdr Q variables */
 265                 if (rcvhdrcnt % HDRQ_INCREMENT) {
 266                         dd_dev_err(dd,
 267                                    "ctxt%u: header queue count %d must be divisible by %lu\n",
 268                                    rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
 269                         goto bail;
 270                 }
 271                 rcd->rcvhdrq_cnt = rcvhdrcnt;
 272                 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
 273                 /*
 274                  * Simple Eager buffer allocation: we have already pre-allocated
 275                  * the number of RcvArray entry groups. Each ctxtdata structure
 276                  * holds the number of groups for that context.
 277                  *
 278                  * To follow CSR requirements and maintain cacheline alignment,
 279                  * make sure all sizes and bases are multiples of group_size.
 280                  *
 281                  * The expected entry count is what is left after assigning
 282                  * eager.
 283                  */
 284                 max_entries = rcd->rcv_array_groups *
 285                         dd->rcv_entries.group_size;
 286                 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
 287                 rcd->egrbufs.count = round_down(rcvtids,
 288                                                 dd->rcv_entries.group_size);
 289                 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
 290                         dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
 291                                    rcd->ctxt);
 292                         rcd->egrbufs.count = MAX_EAGER_ENTRIES;
 293                 }
 294                 hfi1_cdbg(PROC,
 295                           "ctxt%u: max Eager buffer RcvArray entries: %u\n",
 296                           rcd->ctxt, rcd->egrbufs.count);
 297
 298                 /*
 299                  * Allocate array that will hold the eager buffer accounting
 300                  * data.
 301                  * This will allocate the maximum possible buffer count based
 302                  * on the value of the RcvArray split parameter.
 303                  * The resulting value will be rounded down to the closest
 304                  * multiple of dd->rcv_entries.group_size.
 305                  */
 306                 rcd->egrbufs.buffers = kcalloc(rcd->egrbufs.count,
 307                                                sizeof(*rcd->egrbufs.buffers),
 308                                                GFP_KERNEL);
 309                 if (!rcd->egrbufs.buffers)
 310                         goto bail;
 311                 rcd->egrbufs.rcvtids = kcalloc(rcd->egrbufs.count,
 312                                                sizeof(*rcd->egrbufs.rcvtids),
 313                                                GFP_KERNEL);
 314                 if (!rcd->egrbufs.rcvtids)
 315                         goto bail;
 316                 rcd->egrbufs.size = eager_buffer_size;
 317                 /*
 318                  * The size of the buffers programmed into the RcvArray
 319                  * entries needs to be big enough to handle the highest
 320                  * MTU supported.
 321                  */
 322                 if (rcd->egrbufs.size < hfi1_max_mtu) {
 323                         rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
 324                         hfi1_cdbg(PROC,
 325                                   "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
 326                                     rcd->ctxt, rcd->egrbufs.size);
 327                 }
 328                 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
 329
 330                 if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
 331                         rcd->opstats = kzalloc(sizeof(*rcd->opstats),
 332                                 GFP_KERNEL);
 333                         if (!rcd->opstats)
 334                                 goto bail;
 335                 }
 336         }
 337         return rcd;
 338 bail:
 339         kfree(rcd->egrbufs.rcvtids);
 340         kfree(rcd->egrbufs.buffers);
 341         kfree(rcd);
 342         return NULL;
 343 }
 344
 345 /*
 346  * Convert a receive header entry size that to the encoding used in the CSR.
 347  *
 348  * Return a zero if the given size is invalid.
 349  */
 350 static inline u64 encode_rcv_header_entry_size(u16 size)
 351 {
 352         /* there are only 3 valid receive header entry sizes */
 353         if (size == 2)
 354                 return 1;
 355         if (size == 16)
 356                 return 2;
 357         else if (size == 32)
 358                 return 4;
 359         return 0; /* invalid */
 360 }
 361
 362 /*
 363  * Select the largest ccti value over all SLs to determine the intra-
 364  * packet gap for the link.
 365  *
 366  * called with cca_timer_lock held (to protect access to cca_timer
 367  * array), and rcu_read_lock() (to protect access to cc_state).
 368  */
 369 void set_link_ipg(struct hfi1_pportdata *ppd)
 370 {
 371         struct hfi1_devdata *dd = ppd->dd;
 372         struct cc_state *cc_state;
 373         int i;
 374         u16 cce, ccti_limit, max_ccti = 0;
 375         u16 shift, mult;
 376         u64 src;
 377         u32 current_egress_rate; /* Mbits /sec */
 378         u32 max_pkt_time;
 379         /*
 380          * max_pkt_time is the maximum packet egress time in units
 381          * of the fabric clock period 1/(805 MHz).
 382          */
 383
 384         cc_state = get_cc_state(ppd);
 385
 386         if (!cc_state)
 387                 /*
 388                  * This should _never_ happen - rcu_read_lock() is held,
 389                  * and set_link_ipg() should not be called if cc_state
 390                  * is NULL.
 391                  */
 392                 return;
 393
 394         for (i = 0; i < OPA_MAX_SLS; i++) {
 395                 u16 ccti = ppd->cca_timer[i].ccti;
 396
 397                 if (ccti > max_ccti)
 398                         max_ccti = ccti;
 399         }
 400
 401         ccti_limit = cc_state->cct.ccti_limit;
 402         if (max_ccti > ccti_limit)
 403                 max_ccti = ccti_limit;
 404
 405         cce = cc_state->cct.entries[max_ccti].entry;
 406         shift = (cce & 0xc000) >> 14;
 407         mult = (cce & 0x3fff);
 408
 409         current_egress_rate = active_egress_rate(ppd);
 410
 411         max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
 412
 413         src = (max_pkt_time >> shift) * mult;
 414
 415         src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
 416         src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
 417
 418         write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
 419 }
 420
 421 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
 422 {
 423         struct cca_timer *cca_timer;
 424         struct hfi1_pportdata *ppd;
 425         int sl;
 426         u16 ccti_timer, ccti_min;
 427         struct cc_state *cc_state;
 428         unsigned long flags;
 429         enum hrtimer_restart ret = HRTIMER_NORESTART;
 430
 431         cca_timer = container_of(t, struct cca_timer, hrtimer);
 432         ppd = cca_timer->ppd;
 433         sl = cca_timer->sl;
 434
 435         rcu_read_lock();
 436
 437         cc_state = get_cc_state(ppd);
 438
 439         if (!cc_state) {
 440                 rcu_read_unlock();
 441                 return HRTIMER_NORESTART;
 442         }
 443
 444         /*
 445          * 1) decrement ccti for SL
 446          * 2) calculate IPG for link (set_link_ipg())
 447          * 3) restart timer, unless ccti is at min value
 448          */
 449
 450         ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
 451         ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
 452
 453         spin_lock_irqsave(&ppd->cca_timer_lock, flags);
 454
 455         if (cca_timer->ccti > ccti_min) {
 456                 cca_timer->ccti--;
 457                 set_link_ipg(ppd);
 458         }
 459
 460         if (cca_timer->ccti > ccti_min) {
 461                 unsigned long nsec = 1024 * ccti_timer;
 462                 /* ccti_timer is in units of 1.024 usec */
 463                 hrtimer_forward_now(t, ns_to_ktime(nsec));
 464                 ret = HRTIMER_RESTART;
 465         }
 466
 467         spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
 468         rcu_read_unlock();
 469         return ret;
 470 }
 471
 472 /*
 473  * Common code for initializing the physical port structure.
 474  */
 475 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
 476                          struct hfi1_devdata *dd, u8 hw_pidx, u8 port)
 477 {
 478         int i;
 479         uint default_pkey_idx;
 480         struct cc_state *cc_state;
 481
 482         ppd->dd = dd;
 483         ppd->hw_pidx = hw_pidx;
 484         ppd->port = port; /* IB port number, not index */
 485
 486         default_pkey_idx = 1;
 487
 488         ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
 489         if (loopback) {
 490                 hfi1_early_err(&pdev->dev,
 491                                "Faking data partition 0x8001 in idx %u\n",
 492                                !default_pkey_idx);
 493                 ppd->pkeys[!default_pkey_idx] = 0x8001;
 494         }
 495
 496         INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
 497         INIT_WORK(&ppd->link_up_work, handle_link_up);
 498         INIT_WORK(&ppd->link_down_work, handle_link_down);
 499         INIT_WORK(&ppd->freeze_work, handle_freeze);
 500         INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
 501         INIT_WORK(&ppd->sma_message_work, handle_sma_message);
 502         INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
 503         INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
 504         INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
 505
 506         mutex_init(&ppd->hls_lock);
 507         spin_lock_init(&ppd->sdma_alllock);
 508         spin_lock_init(&ppd->qsfp_info.qsfp_lock);
 509
 510         ppd->qsfp_info.ppd = ppd;
 511         ppd->sm_trap_qp = 0x0;
 512         ppd->sa_qp = 0x1;
 513
 514         ppd->hfi1_wq = NULL;
 515
 516         spin_lock_init(&ppd->cca_timer_lock);
 517
 518         for (i = 0; i < OPA_MAX_SLS; i++) {
 519                 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
 520                              HRTIMER_MODE_REL);
 521                 ppd->cca_timer[i].ppd = ppd;
 522                 ppd->cca_timer[i].sl = i;
 523                 ppd->cca_timer[i].ccti = 0;
 524                 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
 525         }
 526
 527         ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
 528
 529         spin_lock_init(&ppd->cc_state_lock);
 530         spin_lock_init(&ppd->cc_log_lock);
 531         cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
 532         RCU_INIT_POINTER(ppd->cc_state, cc_state);
 533         if (!cc_state)
 534                 goto bail;
 535         return;
 536
 537 bail:
 538
 539         hfi1_early_err(&pdev->dev,
 540                        "Congestion Control Agent disabled for port %d\n", port);
 541 }
 542
 543 /*
 544  * Do initialization for device that is only needed on
 545  * first detect, not on resets.
 546  */
 547 static int loadtime_init(struct hfi1_devdata *dd)
 548 {
 549         return 0;
 550 }
 551
 552 /**
 553  * init_after_reset - re-initialize after a reset
 554  * @dd: the hfi1_ib device
 555  *
 556  * sanity check at least some of the values after reset, and
 557  * ensure no receive or transmit (explicitly, in case reset
 558  * failed
 559  */
 560 static int init_after_reset(struct hfi1_devdata *dd)
 561 {
 562         int i;
 563
 564         /*
 565          * Ensure chip does no sends or receives, tail updates, or
 566          * pioavail updates while we re-initialize.  This is mostly
 567          * for the driver data structures, not chip registers.
 568          */
 569         for (i = 0; i < dd->num_rcv_contexts; i++)
 570                 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
 571                                   HFI1_RCVCTRL_INTRAVAIL_DIS |
 572                                   HFI1_RCVCTRL_TAILUPD_DIS, i);
 573         pio_send_control(dd, PSC_GLOBAL_DISABLE);
 574         for (i = 0; i < dd->num_send_contexts; i++)
 575                 sc_disable(dd->send_contexts[i].sc);
 576
 577         return 0;
 578 }
 579
 580 static void enable_chip(struct hfi1_devdata *dd)
 581 {
 582         u32 rcvmask;
 583         u32 i;
 584
 585         /* enable PIO send */
 586         pio_send_control(dd, PSC_GLOBAL_ENABLE);
 587
 588         /*
 589          * Enable kernel ctxts' receive and receive interrupt.
 590          * Other ctxts done as user opens and initializes them.
 591          */
 592         for (i = 0; i < dd->first_user_ctxt; ++i) {
 593                 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
 594                 rcvmask |= HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, DMA_RTAIL) ?
 595                         HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
 596                 if (!HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, MULTI_PKT_EGR))
 597                         rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
 598                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_RHQ_FULL))
 599                         rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
 600                 if (HFI1_CAP_KGET_MASK(dd->rcd[i]->flags, NODROP_EGR_FULL))
 601                         rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
 602                 hfi1_rcvctrl(dd, rcvmask, i);
 603                 sc_enable(dd->rcd[i]->sc);
 604         }
 605 }
 606
 607 /**
 608  * create_workqueues - create per port workqueues
 609  * @dd: the hfi1_ib device
 610  */
 611 static int create_workqueues(struct hfi1_devdata *dd)
 612 {
 613         int pidx;
 614         struct hfi1_pportdata *ppd;
 615
 616         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 617                 ppd = dd->pport + pidx;
 618                 if (!ppd->hfi1_wq) {
 619                         ppd->hfi1_wq =
 620                                 alloc_workqueue(
 621                                     "hfi%d_%d",
 622                                     WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE,
 623                                     dd->num_sdma,
 624                                     dd->unit, pidx);
 625                         if (!ppd->hfi1_wq)
 626                                 goto wq_error;
 627                 }
 628         }
 629         return 0;
 630 wq_error:
 631         pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
 632         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 633                 ppd = dd->pport + pidx;
 634                 if (ppd->hfi1_wq) {
 635                         destroy_workqueue(ppd->hfi1_wq);
 636                         ppd->hfi1_wq = NULL;
 637                 }
 638         }
 639         return -ENOMEM;
 640 }
 641
 642 /**
 643  * hfi1_init - do the actual initialization sequence on the chip
 644  * @dd: the hfi1_ib device
 645  * @reinit: re-initializing, so don't allocate new memory
 646  *
 647  * Do the actual initialization sequence on the chip.  This is done
 648  * both from the init routine called from the PCI infrastructure, and
 649  * when we reset the chip, or detect that it was reset internally,
 650  * or it's administratively re-enabled.
 651  *
 652  * Memory allocation here and in called routines is only done in
 653  * the first case (reinit == 0).  We have to be careful, because even
 654  * without memory allocation, we need to re-write all the chip registers
 655  * TIDs, etc. after the reset or enable has completed.
 656  */
 657 int hfi1_init(struct hfi1_devdata *dd, int reinit)
 658 {
 659         int ret = 0, pidx, lastfail = 0;
 660         unsigned i, len;
 661         struct hfi1_ctxtdata *rcd;
 662         struct hfi1_pportdata *ppd;
 663
 664         /* Set up recv low level handlers */
 665         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EXPECTED] =
 666                                                 kdeth_process_expected;
 667         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_EAGER] =
 668                                                 kdeth_process_eager;
 669         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_IB] = process_receive_ib;
 670         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_ERROR] =
 671                                                 process_receive_error;
 672         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_BYPASS] =
 673                                                 process_receive_bypass;
 674         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID5] =
 675                                                 process_receive_invalid;
 676         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID6] =
 677                                                 process_receive_invalid;
 678         dd->normal_rhf_rcv_functions[RHF_RCV_TYPE_INVALID7] =
 679                                                 process_receive_invalid;
 680         dd->rhf_rcv_function_map = dd->normal_rhf_rcv_functions;
 681
 682         /* Set up send low level handlers */
 683         dd->process_pio_send = hfi1_verbs_send_pio;
 684         dd->process_dma_send = hfi1_verbs_send_dma;
 685         dd->pio_inline_send = pio_copy;
 686
 687         if (is_ax(dd)) {
 688                 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
 689                 dd->do_drop = 1;
 690         } else {
 691                 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
 692                 dd->do_drop = 0;
 693         }
 694
 695         /* make sure the link is not "up" */
 696         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 697                 ppd = dd->pport + pidx;
 698                 ppd->linkup = 0;
 699         }
 700
 701         if (reinit)
 702                 ret = init_after_reset(dd);
 703         else
 704                 ret = loadtime_init(dd);
 705         if (ret)
 706                 goto done;
 707
 708         /* allocate dummy tail memory for all receive contexts */
 709         dd->rcvhdrtail_dummy_kvaddr = dma_zalloc_coherent(
 710                 &dd->pcidev->dev, sizeof(u64),
 711                 &dd->rcvhdrtail_dummy_physaddr,
 712                 GFP_KERNEL);
 713
 714         if (!dd->rcvhdrtail_dummy_kvaddr) {
 715                 dd_dev_err(dd, "cannot allocate dummy tail memory\n");
 716                 ret = -ENOMEM;
 717                 goto done;
 718         }
 719
 720         /* dd->rcd can be NULL if early initialization failed */
 721         for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
 722                 /*
 723                  * Set up the (kernel) rcvhdr queue and egr TIDs.  If doing
 724                  * re-init, the simplest way to handle this is to free
 725                  * existing, and re-allocate.
 726                  * Need to re-create rest of ctxt 0 ctxtdata as well.
 727                  */
 728                 rcd = dd->rcd[i];
 729                 if (!rcd)
 730                         continue;
 731
 732                 rcd->do_interrupt = &handle_receive_interrupt;
 733
 734                 lastfail = hfi1_create_rcvhdrq(dd, rcd);
 735                 if (!lastfail)
 736                         lastfail = hfi1_setup_eagerbufs(rcd);
 737                 if (lastfail) {
 738                         dd_dev_err(dd,
 739                                    "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
 740                         ret = lastfail;
 741                 }
 742         }
 743
 744         /* Allocate enough memory for user event notification. */
 745         len = PAGE_ALIGN(dd->chip_rcv_contexts * HFI1_MAX_SHARED_CTXTS *
 746                          sizeof(*dd->events));
 747         dd->events = vmalloc_user(len);
 748         if (!dd->events)
 749                 dd_dev_err(dd, "Failed to allocate user events page\n");
 750         /*
 751          * Allocate a page for device and port status.
 752          * Page will be shared amongst all user processes.
 753          */
 754         dd->status = vmalloc_user(PAGE_SIZE);
 755         if (!dd->status)
 756                 dd_dev_err(dd, "Failed to allocate dev status page\n");
 757         else
 758                 dd->freezelen = PAGE_SIZE - (sizeof(*dd->status) -
 759                                              sizeof(dd->status->freezemsg));
 760         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 761                 ppd = dd->pport + pidx;
 762                 if (dd->status)
 763                         /* Currently, we only have one port */
 764                         ppd->statusp = &dd->status->port;
 765
 766                 set_mtu(ppd);
 767         }
 768
 769         /* enable chip even if we have an error, so we can debug cause */
 770         enable_chip(dd);
 771
 772 done:
 773         /*
 774          * Set status even if port serdes is not initialized
 775          * so that diags will work.
 776          */
 777         if (dd->status)
 778                 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
 779                         HFI1_STATUS_INITTED;
 780         if (!ret) {
 781                 /* enable all interrupts from the chip */
 782                 set_intr_state(dd, 1);
 783
 784                 /* chip is OK for user apps; mark it as initialized */
 785                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 786                         ppd = dd->pport + pidx;
 787
 788                         /*
 789                          * start the serdes - must be after interrupts are
 790                          * enabled so we are notified when the link goes up
 791                          */
 792                         lastfail = bringup_serdes(ppd);
 793                         if (lastfail)
 794                                 dd_dev_info(dd,
 795                                             "Failed to bring up port %u\n",
 796                                             ppd->port);
 797
 798                         /*
 799                          * Set status even if port serdes is not initialized
 800                          * so that diags will work.
 801                          */
 802                         if (ppd->statusp)
 803                                 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
 804                                                         HFI1_STATUS_INITTED;
 805                         if (!ppd->link_speed_enabled)
 806                                 continue;
 807                 }
 808         }
 809
 810         /* if ret is non-zero, we probably should do some cleanup here... */
 811         return ret;
 812 }
 813
 814 static inline struct hfi1_devdata *__hfi1_lookup(int unit)
 815 {
 816         return idr_find(&hfi1_unit_table, unit);
 817 }
 818
 819 struct hfi1_devdata *hfi1_lookup(int unit)
 820 {
 821         struct hfi1_devdata *dd;
 822         unsigned long flags;
 823
 824         spin_lock_irqsave(&hfi1_devs_lock, flags);
 825         dd = __hfi1_lookup(unit);
 826         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
 827
 828         return dd;
 829 }
 830
 831 /*
 832  * Stop the timers during unit shutdown, or after an error late
 833  * in initialization.
 834  */
 835 static void stop_timers(struct hfi1_devdata *dd)
 836 {
 837         struct hfi1_pportdata *ppd;
 838         int pidx;
 839
 840         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 841                 ppd = dd->pport + pidx;
 842                 if (ppd->led_override_timer.data) {
 843                         del_timer_sync(&ppd->led_override_timer);
 844                         atomic_set(&ppd->led_override_timer_active, 0);
 845                 }
 846         }
 847 }
 848
 849 /**
 850  * shutdown_device - shut down a device
 851  * @dd: the hfi1_ib device
 852  *
 853  * This is called to make the device quiet when we are about to
 854  * unload the driver, and also when the device is administratively
 855  * disabled.   It does not free any data structures.
 856  * Everything it does has to be setup again by hfi1_init(dd, 1)
 857  */
 858 static void shutdown_device(struct hfi1_devdata *dd)
 859 {
 860         struct hfi1_pportdata *ppd;
 861         unsigned pidx;
 862         int i;
 863
 864         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 865                 ppd = dd->pport + pidx;
 866
 867                 ppd->linkup = 0;
 868                 if (ppd->statusp)
 869                         *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
 870                                            HFI1_STATUS_IB_READY);
 871         }
 872         dd->flags &= ~HFI1_INITTED;
 873
 874         /* mask interrupts, but not errors */
 875         set_intr_state(dd, 0);
 876
 877         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 878                 ppd = dd->pport + pidx;
 879                 for (i = 0; i < dd->num_rcv_contexts; i++)
 880                         hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
 881                                           HFI1_RCVCTRL_CTXT_DIS |
 882                                           HFI1_RCVCTRL_INTRAVAIL_DIS |
 883                                           HFI1_RCVCTRL_PKEY_DIS |
 884                                           HFI1_RCVCTRL_ONE_PKT_EGR_DIS, i);
 885                 /*
 886                  * Gracefully stop all sends allowing any in progress to
 887                  * trickle out first.
 888                  */
 889                 for (i = 0; i < dd->num_send_contexts; i++)
 890                         sc_flush(dd->send_contexts[i].sc);
 891         }
 892
 893         /*
 894          * Enough for anything that's going to trickle out to have actually
 895          * done so.
 896          */
 897         udelay(20);
 898
 899         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
 900                 ppd = dd->pport + pidx;
 901
 902                 /* disable all contexts */
 903                 for (i = 0; i < dd->num_send_contexts; i++)
 904                         sc_disable(dd->send_contexts[i].sc);
 905                 /* disable the send device */
 906                 pio_send_control(dd, PSC_GLOBAL_DISABLE);
 907
 908                 shutdown_led_override(ppd);
 909
 910                 /*
 911                  * Clear SerdesEnable.
 912                  * We can't count on interrupts since we are stopping.
 913                  */
 914                 hfi1_quiet_serdes(ppd);
 915
 916                 if (ppd->hfi1_wq) {
 917                         destroy_workqueue(ppd->hfi1_wq);
 918                         ppd->hfi1_wq = NULL;
 919                 }
 920         }
 921         sdma_exit(dd);
 922 }
 923
 924 /**
 925  * hfi1_free_ctxtdata - free a context's allocated data
 926  * @dd: the hfi1_ib device
 927  * @rcd: the ctxtdata structure
 928  *
 929  * free up any allocated data for a context
 930  * This should not touch anything that would affect a simultaneous
 931  * re-allocation of context data, because it is called after hfi1_mutex
 932  * is released (and can be called from reinit as well).
 933  * It should never change any chip state, or global driver state.
 934  */
 935 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
 936 {
 937         unsigned e;
 938
 939         if (!rcd)
 940                 return;
 941
 942         if (rcd->rcvhdrq) {
 943                 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
 944                                   rcd->rcvhdrq, rcd->rcvhdrq_phys);
 945                 rcd->rcvhdrq = NULL;
 946                 if (rcd->rcvhdrtail_kvaddr) {
 947                         dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
 948                                           (void *)rcd->rcvhdrtail_kvaddr,
 949                                           rcd->rcvhdrqtailaddr_phys);
 950                         rcd->rcvhdrtail_kvaddr = NULL;
 951                 }
 952         }
 953
 954         /* all the RcvArray entries should have been cleared by now */
 955         kfree(rcd->egrbufs.rcvtids);
 956
 957         for (e = 0; e < rcd->egrbufs.alloced; e++) {
 958                 if (rcd->egrbufs.buffers[e].phys)
 959                         dma_free_coherent(&dd->pcidev->dev,
 960                                           rcd->egrbufs.buffers[e].len,
 961                                           rcd->egrbufs.buffers[e].addr,
 962                                           rcd->egrbufs.buffers[e].phys);
 963         }
 964         kfree(rcd->egrbufs.buffers);
 965
 966         sc_free(rcd->sc);
 967         vfree(rcd->user_event_mask);
 968         vfree(rcd->subctxt_uregbase);
 969         vfree(rcd->subctxt_rcvegrbuf);
 970         vfree(rcd->subctxt_rcvhdr_base);
 971         kfree(rcd->opstats);
 972         kfree(rcd);
 973 }
 974
 975 /*
 976  * Release our hold on the shared asic data.  If we are the last one,
 977  * return the structure to be finalized outside the lock.  Must be
 978  * holding hfi1_devs_lock.
 979  */
 980 static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
 981 {
 982         struct hfi1_asic_data *ad;
 983         int other;
 984
 985         if (!dd->asic_data)
 986                 return NULL;
 987         dd->asic_data->dds[dd->hfi1_id] = NULL;
 988         other = dd->hfi1_id ? 0 : 1;
 989         ad = dd->asic_data;
 990         dd->asic_data = NULL;
 991         /* return NULL if the other dd still has a link */
 992         return ad->dds[other] ? NULL : ad;
 993 }
 994
 995 static void finalize_asic_data(struct hfi1_devdata *dd,
 996                                struct hfi1_asic_data *ad)
 997 {
 998         clean_up_i2c(dd, ad);
 999         kfree(ad);
1000 }
1001
1002 static void __hfi1_free_devdata(struct kobject *kobj)
1003 {
1004         struct hfi1_devdata *dd =
1005                 container_of(kobj, struct hfi1_devdata, kobj);
1006         struct hfi1_asic_data *ad;
1007         unsigned long flags;
1008
1009         spin_lock_irqsave(&hfi1_devs_lock, flags);
1010         idr_remove(&hfi1_unit_table, dd->unit);
1011         list_del(&dd->list);
1012         ad = release_asic_data(dd);
1013         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1014         if (ad)
1015                 finalize_asic_data(dd, ad);
1016         free_platform_config(dd);
1017         rcu_barrier(); /* wait for rcu callbacks to complete */
1018         free_percpu(dd->int_counter);
1019         free_percpu(dd->rcv_limit);
1020         free_percpu(dd->send_schedule);
1021         rvt_dealloc_device(&dd->verbs_dev.rdi);
1022 }
1023
1024 static struct kobj_type hfi1_devdata_type = {
1025         .release = __hfi1_free_devdata,
1026 };
1027
1028 void hfi1_free_devdata(struct hfi1_devdata *dd)
1029 {
1030         kobject_put(&dd->kobj);
1031 }
1032
1033 /*
1034  * Allocate our primary per-unit data structure.  Must be done via verbs
1035  * allocator, because the verbs cleanup process both does cleanup and
1036  * free of the data structure.
1037  * "extra" is for chip-specific data.
1038  *
1039  * Use the idr mechanism to get a unit number for this unit.
1040  */
1041 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra)
1042 {
1043         unsigned long flags;
1044         struct hfi1_devdata *dd;
1045         int ret, nports;
1046
1047         /* extra is * number of ports */
1048         nports = extra / sizeof(struct hfi1_pportdata);
1049
1050         dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1051                                                      nports);
1052         if (!dd)
1053                 return ERR_PTR(-ENOMEM);
1054         dd->num_pports = nports;
1055         dd->pport = (struct hfi1_pportdata *)(dd + 1);
1056
1057         INIT_LIST_HEAD(&dd->list);
1058         idr_preload(GFP_KERNEL);
1059         spin_lock_irqsave(&hfi1_devs_lock, flags);
1060
1061         ret = idr_alloc(&hfi1_unit_table, dd, 0, 0, GFP_NOWAIT);
1062         if (ret >= 0) {
1063                 dd->unit = ret;
1064                 list_add(&dd->list, &hfi1_dev_list);
1065         }
1066
1067         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1068         idr_preload_end();
1069
1070         if (ret < 0) {
1071                 hfi1_early_err(&pdev->dev,
1072                                "Could not allocate unit ID: error %d\n", -ret);
1073                 goto bail;
1074         }
1075         /*
1076          * Initialize all locks for the device. This needs to be as early as
1077          * possible so locks are usable.
1078          */
1079         spin_lock_init(&dd->sc_lock);
1080         spin_lock_init(&dd->sendctrl_lock);
1081         spin_lock_init(&dd->rcvctrl_lock);
1082         spin_lock_init(&dd->uctxt_lock);
1083         spin_lock_init(&dd->hfi1_diag_trans_lock);
1084         spin_lock_init(&dd->sc_init_lock);
1085         spin_lock_init(&dd->dc8051_lock);
1086         spin_lock_init(&dd->dc8051_memlock);
1087         seqlock_init(&dd->sc2vl_lock);
1088         spin_lock_init(&dd->sde_map_lock);
1089         spin_lock_init(&dd->pio_map_lock);
1090         init_waitqueue_head(&dd->event_queue);
1091
1092         dd->int_counter = alloc_percpu(u64);
1093         if (!dd->int_counter) {
1094                 ret = -ENOMEM;
1095                 hfi1_early_err(&pdev->dev,
1096                                "Could not allocate per-cpu int_counter\n");
1097                 goto bail;
1098         }
1099
1100         dd->rcv_limit = alloc_percpu(u64);
1101         if (!dd->rcv_limit) {
1102                 ret = -ENOMEM;
1103                 hfi1_early_err(&pdev->dev,
1104                                "Could not allocate per-cpu rcv_limit\n");
1105                 goto bail;
1106         }
1107
1108         dd->send_schedule = alloc_percpu(u64);
1109         if (!dd->send_schedule) {
1110                 ret = -ENOMEM;
1111                 hfi1_early_err(&pdev->dev,
1112                                "Could not allocate per-cpu int_counter\n");
1113                 goto bail;
1114         }
1115
1116         if (!hfi1_cpulist_count) {
1117                 u32 count = num_online_cpus();
1118
1119                 hfi1_cpulist = kcalloc(BITS_TO_LONGS(count), sizeof(long),
1120                                        GFP_KERNEL);
1121                 if (hfi1_cpulist)
1122                         hfi1_cpulist_count = count;
1123                 else
1124                         hfi1_early_err(
1125                         &pdev->dev,
1126                         "Could not alloc cpulist info, cpu affinity might be wrong\n");
1127         }
1128         kobject_init(&dd->kobj, &hfi1_devdata_type);
1129         return dd;
1130
1131 bail:
1132         if (!list_empty(&dd->list))
1133                 list_del_init(&dd->list);
1134         rvt_dealloc_device(&dd->verbs_dev.rdi);
1135         return ERR_PTR(ret);
1136 }
1137
1138 /*
1139  * Called from freeze mode handlers, and from PCI error
1140  * reporting code.  Should be paranoid about state of
1141  * system and data structures.
1142  */
1143 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1144 {
1145         if (dd->flags & HFI1_INITTED) {
1146                 u32 pidx;
1147
1148                 dd->flags &= ~HFI1_INITTED;
1149                 if (dd->pport)
1150                         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1151                                 struct hfi1_pportdata *ppd;
1152
1153                                 ppd = dd->pport + pidx;
1154                                 if (dd->flags & HFI1_PRESENT)
1155                                         set_link_state(ppd, HLS_DN_DISABLE);
1156
1157                                 if (ppd->statusp)
1158                                         *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1159                         }
1160         }
1161
1162         /*
1163          * Mark as having had an error for driver, and also
1164          * for /sys and status word mapped to user programs.
1165          * This marks unit as not usable, until reset.
1166          */
1167         if (dd->status)
1168                 dd->status->dev |= HFI1_STATUS_HWERROR;
1169 }
1170
1171 static void remove_one(struct pci_dev *);
1172 static int init_one(struct pci_dev *, const struct pci_device_id *);
1173
1174 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1175 #define PFX DRIVER_NAME ": "
1176
1177 const struct pci_device_id hfi1_pci_tbl[] = {
1178         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1179         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1180         { 0, }
1181 };
1182
1183 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1184
1185 static struct pci_driver hfi1_pci_driver = {
1186         .name = DRIVER_NAME,
1187         .probe = init_one,
1188         .remove = remove_one,
1189         .id_table = hfi1_pci_tbl,
1190         .err_handler = &hfi1_pci_err_handler,
1191 };
1192
1193 static void __init compute_krcvqs(void)
1194 {
1195         int i;
1196
1197         for (i = 0; i < krcvqsset; i++)
1198                 n_krcvqs += krcvqs[i];
1199 }
1200
1201 /*
1202  * Do all the generic driver unit- and chip-independent memory
1203  * allocation and initialization.
1204  */
1205 static int __init hfi1_mod_init(void)
1206 {
1207         int ret;
1208
1209         ret = dev_init();
1210         if (ret)
1211                 goto bail;
1212
1213         ret = node_affinity_init();
1214         if (ret)
1215                 goto bail;
1216
1217         /* validate max MTU before any devices start */
1218         if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1219                 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1220                        hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1221                 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1222         }
1223         /* valid CUs run from 1-128 in powers of 2 */
1224         if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1225                 hfi1_cu = 1;
1226         /* valid credit return threshold is 0-100, variable is unsigned */
1227         if (user_credit_return_threshold > 100)
1228                 user_credit_return_threshold = 100;
1229
1230         compute_krcvqs();
1231         /*
1232          * sanitize receive interrupt count, time must wait until after
1233          * the hardware type is known
1234          */
1235         if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1236                 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1237         /* reject invalid combinations */
1238         if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1239                 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1240                 rcv_intr_count = 1;
1241         }
1242         if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1243                 /*
1244                  * Avoid indefinite packet delivery by requiring a timeout
1245                  * if count is > 1.
1246                  */
1247                 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1248                 rcv_intr_timeout = 1;
1249         }
1250         if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1251                 /*
1252                  * The dynamic algorithm expects a non-zero timeout
1253                  * and a count > 1.
1254                  */
1255                 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1256                 rcv_intr_dynamic = 0;
1257         }
1258
1259         /* sanitize link CRC options */
1260         link_crc_mask &= SUPPORTED_CRCS;
1261
1262         /*
1263          * These must be called before the driver is registered with
1264          * the PCI subsystem.
1265          */
1266         idr_init(&hfi1_unit_table);
1267
1268         hfi1_dbg_init();
1269         ret = hfi1_wss_init();
1270         if (ret < 0)
1271                 goto bail_wss;
1272         ret = pci_register_driver(&hfi1_pci_driver);
1273         if (ret < 0) {
1274                 pr_err("Unable to register driver: error %d\n", -ret);
1275                 goto bail_dev;
1276         }
1277         goto bail; /* all OK */
1278
1279 bail_dev:
1280         hfi1_wss_exit();
1281 bail_wss:
1282         hfi1_dbg_exit();
1283         idr_destroy(&hfi1_unit_table);
1284         dev_cleanup();
1285 bail:
1286         return ret;
1287 }
1288
1289 module_init(hfi1_mod_init);
1290
1291 /*
1292  * Do the non-unit driver cleanup, memory free, etc. at unload.
1293  */
1294 static void __exit hfi1_mod_cleanup(void)
1295 {
1296         pci_unregister_driver(&hfi1_pci_driver);
1297         node_affinity_destroy();
1298         hfi1_wss_exit();
1299         hfi1_dbg_exit();
1300         hfi1_cpulist_count = 0;
1301         kfree(hfi1_cpulist);
1302
1303         idr_destroy(&hfi1_unit_table);
1304         dispose_firmware();     /* asymmetric with obtain_firmware() */
1305         dev_cleanup();
1306 }
1307
1308 module_exit(hfi1_mod_cleanup);
1309
1310 /* this can only be called after a successful initialization */
1311 static void cleanup_device_data(struct hfi1_devdata *dd)
1312 {
1313         int ctxt;
1314         int pidx;
1315         struct hfi1_ctxtdata **tmp;
1316         unsigned long flags;
1317
1318         /* users can't do anything more with chip */
1319         for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1320                 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1321                 struct cc_state *cc_state;
1322                 int i;
1323
1324                 if (ppd->statusp)
1325                         *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1326
1327                 for (i = 0; i < OPA_MAX_SLS; i++)
1328                         hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1329
1330                 spin_lock(&ppd->cc_state_lock);
1331                 cc_state = get_cc_state_protected(ppd);
1332                 RCU_INIT_POINTER(ppd->cc_state, NULL);
1333                 spin_unlock(&ppd->cc_state_lock);
1334
1335                 if (cc_state)
1336                         call_rcu(&cc_state->rcu, cc_state_reclaim);
1337         }
1338
1339         free_credit_return(dd);
1340
1341         /*
1342          * Free any resources still in use (usually just kernel contexts)
1343          * at unload; we do for ctxtcnt, because that's what we allocate.
1344          * We acquire lock to be really paranoid that rcd isn't being
1345          * accessed from some interrupt-related code (that should not happen,
1346          * but best to be sure).
1347          */
1348         spin_lock_irqsave(&dd->uctxt_lock, flags);
1349         tmp = dd->rcd;
1350         dd->rcd = NULL;
1351         spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1352
1353         if (dd->rcvhdrtail_dummy_kvaddr) {
1354                 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1355                                   (void *)dd->rcvhdrtail_dummy_kvaddr,
1356                                   dd->rcvhdrtail_dummy_physaddr);
1357                 dd->rcvhdrtail_dummy_kvaddr = NULL;
1358         }
1359
1360         for (ctxt = 0; tmp && ctxt < dd->num_rcv_contexts; ctxt++) {
1361                 struct hfi1_ctxtdata *rcd = tmp[ctxt];
1362
1363                 tmp[ctxt] = NULL; /* debugging paranoia */
1364                 if (rcd) {
1365                         hfi1_clear_tids(rcd);
1366                         hfi1_free_ctxtdata(dd, rcd);
1367                 }
1368         }
1369         kfree(tmp);
1370         free_pio_map(dd);
1371         /* must follow rcv context free - need to remove rcv's hooks */
1372         for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1373                 sc_free(dd->send_contexts[ctxt].sc);
1374         dd->num_send_contexts = 0;
1375         kfree(dd->send_contexts);
1376         dd->send_contexts = NULL;
1377         kfree(dd->hw_to_sw);
1378         dd->hw_to_sw = NULL;
1379         kfree(dd->boardname);
1380         vfree(dd->events);
1381         vfree(dd->status);
1382 }
1383
1384 /*
1385  * Clean up on unit shutdown, or error during unit load after
1386  * successful initialization.
1387  */
1388 static void postinit_cleanup(struct hfi1_devdata *dd)
1389 {
1390         hfi1_start_cleanup(dd);
1391
1392         hfi1_pcie_ddcleanup(dd);
1393         hfi1_pcie_cleanup(dd->pcidev);
1394
1395         cleanup_device_data(dd);
1396
1397         hfi1_free_devdata(dd);
1398 }
1399
1400 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1401 {
1402         int ret = 0, j, pidx, initfail;
1403         struct hfi1_devdata *dd = ERR_PTR(-EINVAL);
1404         struct hfi1_pportdata *ppd;
1405
1406         /* First, lock the non-writable module parameters */
1407         HFI1_CAP_LOCK();
1408
1409         /* Validate some global module parameters */
1410         if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
1411                 hfi1_early_err(&pdev->dev, "Header queue  count too small\n");
1412                 ret = -EINVAL;
1413                 goto bail;
1414         }
1415         if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
1416                 hfi1_early_err(&pdev->dev,
1417                                "Receive header queue count cannot be greater than %u\n",
1418                                HFI1_MAX_HDRQ_EGRBUF_CNT);
1419                 ret = -EINVAL;
1420                 goto bail;
1421         }
1422         /* use the encoding function as a sanitization check */
1423         if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1424                 hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n",
1425                                hfi1_hdrq_entsize);
1426                 ret = -EINVAL;
1427                 goto bail;
1428         }
1429
1430         /* The receive eager buffer size must be set before the receive
1431          * contexts are created.
1432          *
1433          * Set the eager buffer size.  Validate that it falls in a range
1434          * allowed by the hardware - all powers of 2 between the min and
1435          * max.  The maximum valid MTU is within the eager buffer range
1436          * so we do not need to cap the max_mtu by an eager buffer size
1437          * setting.
1438          */
1439         if (eager_buffer_size) {
1440                 if (!is_power_of_2(eager_buffer_size))
1441                         eager_buffer_size =
1442                                 roundup_pow_of_two(eager_buffer_size);
1443                 eager_buffer_size =
1444                         clamp_val(eager_buffer_size,
1445                                   MIN_EAGER_BUFFER * 8,
1446                                   MAX_EAGER_BUFFER_TOTAL);
1447                 hfi1_early_info(&pdev->dev, "Eager buffer size %u\n",
1448                                 eager_buffer_size);
1449         } else {
1450                 hfi1_early_err(&pdev->dev, "Invalid Eager buffer size of 0\n");
1451                 ret = -EINVAL;
1452                 goto bail;
1453         }
1454
1455         /* restrict value of hfi1_rcvarr_split */
1456         hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1457
1458         ret = hfi1_pcie_init(pdev, ent);
1459         if (ret)
1460                 goto bail;
1461
1462         /*
1463          * Do device-specific initialization, function table setup, dd
1464          * allocation, etc.
1465          */
1466         switch (ent->device) {
1467         case PCI_DEVICE_ID_INTEL0:
1468         case PCI_DEVICE_ID_INTEL1:
1469                 dd = hfi1_init_dd(pdev, ent);
1470                 break;
1471         default:
1472                 hfi1_early_err(&pdev->dev,
1473                                "Failing on unknown Intel deviceid 0x%x\n",
1474                                ent->device);
1475                 ret = -ENODEV;
1476         }
1477
1478         if (IS_ERR(dd))
1479                 ret = PTR_ERR(dd);
1480         if (ret)
1481                 goto clean_bail; /* error already printed */
1482
1483         ret = create_workqueues(dd);
1484         if (ret)
1485                 goto clean_bail;
1486
1487         /* do the generic initialization */
1488         initfail = hfi1_init(dd, 0);
1489
1490         ret = hfi1_register_ib_device(dd);
1491
1492         /*
1493          * Now ready for use.  this should be cleared whenever we
1494          * detect a reset, or initiate one.  If earlier failure,
1495          * we still create devices, so diags, etc. can be used
1496          * to determine cause of problem.
1497          */
1498         if (!initfail && !ret) {
1499                 dd->flags |= HFI1_INITTED;
1500                 /* create debufs files after init and ib register */
1501                 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1502         }
1503
1504         j = hfi1_device_create(dd);
1505         if (j)
1506                 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1507
1508         if (initfail || ret) {
1509                 stop_timers(dd);
1510                 flush_workqueue(ib_wq);
1511                 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1512                         hfi1_quiet_serdes(dd->pport + pidx);
1513                         ppd = dd->pport + pidx;
1514                         if (ppd->hfi1_wq) {
1515                                 destroy_workqueue(ppd->hfi1_wq);
1516                                 ppd->hfi1_wq = NULL;
1517                         }
1518                 }
1519                 if (!j)
1520                         hfi1_device_remove(dd);
1521                 if (!ret)
1522                         hfi1_unregister_ib_device(dd);
1523                 postinit_cleanup(dd);
1524                 if (initfail)
1525                         ret = initfail;
1526                 goto bail;      /* everything already cleaned */
1527         }
1528
1529         sdma_start(dd);
1530
1531         return 0;
1532
1533 clean_bail:
1534         hfi1_pcie_cleanup(pdev);
1535 bail:
1536         return ret;
1537 }
1538
1539 static void remove_one(struct pci_dev *pdev)
1540 {
1541         struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1542
1543         /* close debugfs files before ib unregister */
1544         hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1545         /* unregister from IB core */
1546         hfi1_unregister_ib_device(dd);
1547
1548         /*
1549          * Disable the IB link, disable interrupts on the device,
1550          * clear dma engines, etc.
1551          */
1552         shutdown_device(dd);
1553
1554         stop_timers(dd);
1555
1556         /* wait until all of our (qsfp) queue_work() calls complete */
1557         flush_workqueue(ib_wq);
1558
1559         hfi1_device_remove(dd);
1560
1561         postinit_cleanup(dd);
1562 }
1563
1564 /**
1565  * hfi1_create_rcvhdrq - create a receive header queue
1566  * @dd: the hfi1_ib device
1567  * @rcd: the context data
1568  *
1569  * This must be contiguous memory (from an i/o perspective), and must be
1570  * DMA'able (which means for some systems, it will go through an IOMMU,
1571  * or be forced into a low address range).
1572  */
1573 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1574 {
1575         unsigned amt;
1576         u64 reg;
1577
1578         if (!rcd->rcvhdrq) {
1579                 dma_addr_t phys_hdrqtail;
1580                 gfp_t gfp_flags;
1581
1582                 /*
1583                  * rcvhdrqentsize is in DWs, so we have to convert to bytes
1584                  * (* sizeof(u32)).
1585                  */
1586                 amt = PAGE_ALIGN(rcd->rcvhdrq_cnt * rcd->rcvhdrqentsize *
1587                                  sizeof(u32));
1588
1589                 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1590                         GFP_USER : GFP_KERNEL;
1591                 rcd->rcvhdrq = dma_zalloc_coherent(
1592                         &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1593                         gfp_flags | __GFP_COMP);
1594
1595                 if (!rcd->rcvhdrq) {
1596                         dd_dev_err(dd,
1597                                    "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1598                                    amt, rcd->ctxt);
1599                         goto bail;
1600                 }
1601
1602                 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL)) {
1603                         rcd->rcvhdrtail_kvaddr = dma_zalloc_coherent(
1604                                 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1605                                 gfp_flags);
1606                         if (!rcd->rcvhdrtail_kvaddr)
1607                                 goto bail_free;
1608                         rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1609                 }
1610
1611                 rcd->rcvhdrq_size = amt;
1612         }
1613         /*
1614          * These values are per-context:
1615          *      RcvHdrCnt
1616          *      RcvHdrEntSize
1617          *      RcvHdrSize
1618          */
1619         reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT)
1620                         & RCV_HDR_CNT_CNT_MASK)
1621                 << RCV_HDR_CNT_CNT_SHIFT;
1622         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg);
1623         reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize)
1624                         & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK)
1625                 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
1626         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg);
1627         reg = (dd->rcvhdrsize & RCV_HDR_SIZE_HDR_SIZE_MASK)
1628                 << RCV_HDR_SIZE_HDR_SIZE_SHIFT;
1629         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg);
1630
1631         /*
1632          * Program dummy tail address for every receive context
1633          * before enabling any receive context
1634          */
1635         write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR,
1636                         dd->rcvhdrtail_dummy_physaddr);
1637
1638         return 0;
1639
1640 bail_free:
1641         dd_dev_err(dd,
1642                    "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1643                    rcd->ctxt);
1644         vfree(rcd->user_event_mask);
1645         rcd->user_event_mask = NULL;
1646         dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1647                           rcd->rcvhdrq_phys);
1648         rcd->rcvhdrq = NULL;
1649 bail:
1650         return -ENOMEM;
1651 }
1652
1653 /**
1654  * allocate eager buffers, both kernel and user contexts.
1655  * @rcd: the context we are setting up.
1656  *
1657  * Allocate the eager TID buffers and program them into hip.
1658  * They are no longer completely contiguous, we do multiple allocation
1659  * calls.  Otherwise we get the OOM code involved, by asking for too
1660  * much per call, with disastrous results on some kernels.
1661  */
1662 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1663 {
1664         struct hfi1_devdata *dd = rcd->dd;
1665         u32 max_entries, egrtop, alloced_bytes = 0, idx = 0;
1666         gfp_t gfp_flags;
1667         u16 order;
1668         int ret = 0;
1669         u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1670
1671         /*
1672          * GFP_USER, but without GFP_FS, so buffer cache can be
1673          * coalesced (we hope); otherwise, even at order 4,
1674          * heavy filesystem activity makes these fail, and we can
1675          * use compound pages.
1676          */
1677         gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1678
1679         /*
1680          * The minimum size of the eager buffers is a groups of MTU-sized
1681          * buffers.
1682          * The global eager_buffer_size parameter is checked against the
1683          * theoretical lower limit of the value. Here, we check against the
1684          * MTU.
1685          */
1686         if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1687                 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1688         /*
1689          * If using one-pkt-per-egr-buffer, lower the eager buffer
1690          * size to the max MTU (page-aligned).
1691          */
1692         if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1693                 rcd->egrbufs.rcvtid_size = round_mtu;
1694
1695         /*
1696          * Eager buffers sizes of 1MB or less require smaller TID sizes
1697          * to satisfy the "multiple of 8 RcvArray entries" requirement.
1698          */
1699         if (rcd->egrbufs.size <= (1 << 20))
1700                 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1701                         rounddown_pow_of_two(rcd->egrbufs.size / 8));
1702
1703         while (alloced_bytes < rcd->egrbufs.size &&
1704                rcd->egrbufs.alloced < rcd->egrbufs.count) {
1705                 rcd->egrbufs.buffers[idx].addr =
1706                         dma_zalloc_coherent(&dd->pcidev->dev,
1707                                             rcd->egrbufs.rcvtid_size,
1708                                             &rcd->egrbufs.buffers[idx].phys,
1709                                             gfp_flags);
1710                 if (rcd->egrbufs.buffers[idx].addr) {
1711                         rcd->egrbufs.buffers[idx].len =
1712                                 rcd->egrbufs.rcvtid_size;
1713                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1714                                 rcd->egrbufs.buffers[idx].addr;
1715                         rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].phys =
1716                                 rcd->egrbufs.buffers[idx].phys;
1717                         rcd->egrbufs.alloced++;
1718                         alloced_bytes += rcd->egrbufs.rcvtid_size;
1719                         idx++;
1720                 } else {
1721                         u32 new_size, i, j;
1722                         u64 offset = 0;
1723
1724                         /*
1725                          * Fail the eager buffer allocation if:
1726                          *   - we are already using the lowest acceptable size
1727                          *   - we are using one-pkt-per-egr-buffer (this implies
1728                          *     that we are accepting only one size)
1729                          */
1730                         if (rcd->egrbufs.rcvtid_size == round_mtu ||
1731                             !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1732                                 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1733                                            rcd->ctxt);
1734                                 goto bail_rcvegrbuf_phys;
1735                         }
1736
1737                         new_size = rcd->egrbufs.rcvtid_size / 2;
1738
1739                         /*
1740                          * If the first attempt to allocate memory failed, don't
1741                          * fail everything but continue with the next lower
1742                          * size.
1743                          */
1744                         if (idx == 0) {
1745                                 rcd->egrbufs.rcvtid_size = new_size;
1746                                 continue;
1747                         }
1748
1749                         /*
1750                          * Re-partition already allocated buffers to a smaller
1751                          * size.
1752                          */
1753                         rcd->egrbufs.alloced = 0;
1754                         for (i = 0, j = 0, offset = 0; j < idx; i++) {
1755                                 if (i >= rcd->egrbufs.count)
1756                                         break;
1757                                 rcd->egrbufs.rcvtids[i].phys =
1758                                         rcd->egrbufs.buffers[j].phys + offset;
1759                                 rcd->egrbufs.rcvtids[i].addr =
1760                                         rcd->egrbufs.buffers[j].addr + offset;
1761                                 rcd->egrbufs.alloced++;
1762                                 if ((rcd->egrbufs.buffers[j].phys + offset +
1763                                      new_size) ==
1764                                     (rcd->egrbufs.buffers[j].phys +
1765                                      rcd->egrbufs.buffers[j].len)) {
1766                                         j++;
1767                                         offset = 0;
1768                                 } else {
1769                                         offset += new_size;
1770                                 }
1771                         }
1772                         rcd->egrbufs.rcvtid_size = new_size;
1773                 }
1774         }
1775         rcd->egrbufs.numbufs = idx;
1776         rcd->egrbufs.size = alloced_bytes;
1777
1778         hfi1_cdbg(PROC,
1779                   "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1780                   rcd->ctxt, rcd->egrbufs.alloced,
1781                   rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
1782
1783         /*
1784          * Set the contexts rcv array head update threshold to the closest
1785          * power of 2 (so we can use a mask instead of modulo) below half
1786          * the allocated entries.
1787          */
1788         rcd->egrbufs.threshold =
1789                 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1790         /*
1791          * Compute the expected RcvArray entry base. This is done after
1792          * allocating the eager buffers in order to maximize the
1793          * expected RcvArray entries for the context.
1794          */
1795         max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
1796         egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
1797         rcd->expected_count = max_entries - egrtop;
1798         if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
1799                 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
1800
1801         rcd->expected_base = rcd->eager_base + egrtop;
1802         hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1803                   rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
1804                   rcd->eager_base, rcd->expected_base);
1805
1806         if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
1807                 hfi1_cdbg(PROC,
1808                           "ctxt%u: current Eager buffer size is invalid %u\n",
1809                           rcd->ctxt, rcd->egrbufs.rcvtid_size);
1810                 ret = -EINVAL;
1811                 goto bail;
1812         }
1813
1814         for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
1815                 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
1816                              rcd->egrbufs.rcvtids[idx].phys, order);
1817                 cond_resched();
1818         }
1819         goto bail;
1820
1821 bail_rcvegrbuf_phys:
1822         for (idx = 0; idx < rcd->egrbufs.alloced &&
1823              rcd->egrbufs.buffers[idx].addr;
1824              idx++) {
1825                 dma_free_coherent(&dd->pcidev->dev,
1826                                   rcd->egrbufs.buffers[idx].len,
1827                                   rcd->egrbufs.buffers[idx].addr,
1828                                   rcd->egrbufs.buffers[idx].phys);
1829                 rcd->egrbufs.buffers[idx].addr = NULL;
1830                 rcd->egrbufs.buffers[idx].phys = 0;
1831                 rcd->egrbufs.buffers[idx].len = 0;
1832         }
1833 bail:
1834         return ret;
1835 }