2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
43 #include <net/addrconf.h>
44 #include <net/devlink.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_cache.h>
51 #include <net/bonding.h>
53 #include <linux/mlx4/driver.h>
54 #include <linux/mlx4/cmd.h>
55 #include <linux/mlx4/qp.h>
58 #include <rdma/mlx4-abi.h>
60 #define DRV_NAME MLX4_IB_DRV_NAME
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
65 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
66 #define MLX4_IB_CARD_REV_A0 0xA0
68 MODULE_AUTHOR("Roland Dreier");
69 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
70 MODULE_LICENSE("Dual BSD/GPL");
71 MODULE_VERSION(DRV_VERSION);
73 int mlx4_ib_sm_guid_assign = 0;
74 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
75 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
77 static const char mlx4_ib_version[] =
78 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
81 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static struct workqueue_struct *wq;
85 static void init_query_mad(struct ib_smp *mad)
87 mad->base_version = 1;
88 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
89 mad->class_version = 1;
90 mad->method = IB_MGMT_METHOD_GET;
93 static int check_flow_steering_support(struct mlx4_dev *dev)
95 int eth_num_ports = 0;
98 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
104 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
106 dmfs &= (!ib_num_ports ||
107 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
109 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
110 if (ib_num_ports && mlx4_is_mfunc(dev)) {
111 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
118 static int num_ib_ports(struct mlx4_dev *dev)
123 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
129 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
131 struct mlx4_ib_dev *ibdev = to_mdev(device);
132 struct net_device *dev;
135 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
138 if (mlx4_is_bonded(ibdev->dev)) {
139 struct net_device *upper = NULL;
141 upper = netdev_master_upper_dev_get_rcu(dev);
143 struct net_device *active;
145 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
158 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
159 struct mlx4_ib_dev *ibdev,
162 struct mlx4_cmd_mailbox *mailbox;
164 struct mlx4_dev *dev = ibdev->dev;
166 union ib_gid *gid_tbl;
168 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 gid_tbl = mailbox->buf;
174 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
175 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
177 err = mlx4_cmd(dev, mailbox->dma,
178 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
179 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
181 if (mlx4_is_bonded(dev))
182 err += mlx4_cmd(dev, mailbox->dma,
183 MLX4_SET_PORT_GID_TABLE << 8 | 2,
184 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
187 mlx4_free_cmd_mailbox(dev, mailbox);
191 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
192 struct mlx4_ib_dev *ibdev,
195 struct mlx4_cmd_mailbox *mailbox;
197 struct mlx4_dev *dev = ibdev->dev;
208 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 gid_tbl = mailbox->buf;
213 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
214 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
215 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
216 gid_tbl[i].version = 2;
217 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
220 memset(&gid_tbl[i].gid, 0, 12);
224 err = mlx4_cmd(dev, mailbox->dma,
225 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
226 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 if (mlx4_is_bonded(dev))
229 err += mlx4_cmd(dev, mailbox->dma,
230 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
231 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
234 mlx4_free_cmd_mailbox(dev, mailbox);
238 static int mlx4_ib_update_gids(struct gid_entry *gids,
239 struct mlx4_ib_dev *ibdev,
242 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
243 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
248 static int mlx4_ib_add_gid(struct ib_device *device,
251 const union ib_gid *gid,
252 const struct ib_gid_attr *attr,
255 struct mlx4_ib_dev *ibdev = to_mdev(device);
256 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
257 struct mlx4_port_gid_table *port_gid_table;
258 int free = -1, found = -1;
262 struct gid_entry *gids = NULL;
264 if (!rdma_cap_roce_gid_table(device, port_num))
267 if (port_num > MLX4_MAX_PORTS)
273 port_gid_table = &iboe->gids[port_num - 1];
274 spin_lock_bh(&iboe->lock);
275 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
276 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
277 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
281 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
282 free = i; /* HW has space */
289 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
290 if (!port_gid_table->gids[free].ctx) {
293 *context = port_gid_table->gids[free].ctx;
294 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
295 port_gid_table->gids[free].gid_type = attr->gid_type;
296 port_gid_table->gids[free].ctx->real_index = free;
297 port_gid_table->gids[free].ctx->refcount = 1;
302 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
306 if (!ret && hw_update) {
307 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
311 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
312 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
313 gids[i].gid_type = port_gid_table->gids[i].gid_type;
317 spin_unlock_bh(&iboe->lock);
319 if (!ret && hw_update) {
320 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
327 static int mlx4_ib_del_gid(struct ib_device *device,
332 struct gid_cache_context *ctx = *context;
333 struct mlx4_ib_dev *ibdev = to_mdev(device);
334 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
335 struct mlx4_port_gid_table *port_gid_table;
338 struct gid_entry *gids = NULL;
340 if (!rdma_cap_roce_gid_table(device, port_num))
343 if (port_num > MLX4_MAX_PORTS)
346 port_gid_table = &iboe->gids[port_num - 1];
347 spin_lock_bh(&iboe->lock);
350 if (!ctx->refcount) {
351 unsigned int real_index = ctx->real_index;
353 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
354 kfree(port_gid_table->gids[real_index].ctx);
355 port_gid_table->gids[real_index].ctx = NULL;
359 if (!ret && hw_update) {
362 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
366 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
367 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
370 spin_unlock_bh(&iboe->lock);
372 if (!ret && hw_update) {
373 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
379 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
380 u8 port_num, int index)
382 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
383 struct gid_cache_context *ctx = NULL;
385 struct mlx4_port_gid_table *port_gid_table;
386 int real_index = -EINVAL;
390 struct ib_gid_attr attr;
392 if (port_num > MLX4_MAX_PORTS)
395 if (mlx4_is_bonded(ibdev->dev))
398 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
401 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
408 if (!memcmp(&gid, &zgid, sizeof(gid)))
411 spin_lock_irqsave(&iboe->lock, flags);
412 port_gid_table = &iboe->gids[port_num - 1];
414 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
415 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
416 attr.gid_type == port_gid_table->gids[i].gid_type) {
417 ctx = port_gid_table->gids[i].ctx;
421 real_index = ctx->real_index;
422 spin_unlock_irqrestore(&iboe->lock, flags);
426 static int mlx4_ib_query_device(struct ib_device *ibdev,
427 struct ib_device_attr *props,
428 struct ib_udata *uhw)
430 struct mlx4_ib_dev *dev = to_mdev(ibdev);
431 struct ib_smp *in_mad = NULL;
432 struct ib_smp *out_mad = NULL;
435 struct mlx4_uverbs_ex_query_device cmd;
436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
437 struct mlx4_clock_params clock_params;
440 if (uhw->inlen < sizeof(cmd))
443 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
454 resp.response_length = offsetof(typeof(resp), response_length) +
455 sizeof(resp.response_length);
456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
458 if (!in_mad || !out_mad)
461 init_query_mad(in_mad);
462 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
464 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
465 1, NULL, NULL, in_mad, out_mad);
469 memset(props, 0, sizeof *props);
471 have_ib_ports = num_ib_ports(dev->dev);
473 props->fw_ver = dev->dev->caps.fw_ver;
474 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
475 IB_DEVICE_PORT_ACTIVE_EVENT |
476 IB_DEVICE_SYS_IMAGE_GUID |
477 IB_DEVICE_RC_RNR_NAK_GEN |
478 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
480 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
482 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
484 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
486 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
488 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
489 if (dev->dev->caps.max_gso_sz &&
490 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
491 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
492 props->device_cap_flags |= IB_DEVICE_UD_TSO;
493 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
494 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
495 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
496 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
497 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
498 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
499 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
500 props->device_cap_flags |= IB_DEVICE_XRC;
501 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
503 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
504 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
505 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
507 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
509 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
510 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
512 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
514 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
516 props->vendor_part_id = dev->dev->persist->pdev->device;
517 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
518 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
520 props->max_mr_size = ~0ull;
521 props->page_size_cap = dev->dev->caps.page_size_cap;
522 props->max_qp = dev->dev->quotas.qp;
523 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
524 props->max_sge = min(dev->dev->caps.max_sq_sg,
525 dev->dev->caps.max_rq_sg);
526 props->max_sge_rd = MLX4_MAX_SGE_RD;
527 props->max_cq = dev->dev->quotas.cq;
528 props->max_cqe = dev->dev->caps.max_cqes;
529 props->max_mr = dev->dev->quotas.mpt;
530 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
531 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
532 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
533 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
534 props->max_srq = dev->dev->quotas.srq;
535 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
536 props->max_srq_sge = dev->dev->caps.max_srq_sge;
537 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
538 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
539 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
540 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
541 props->masked_atomic_cap = props->atomic_cap;
542 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
543 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
544 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
545 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
546 props->max_mcast_grp;
547 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
548 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
549 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
551 if (!mlx4_is_slave(dev->dev))
552 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
554 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
555 resp.response_length += sizeof(resp.hca_core_clock_offset);
556 if (!err && !mlx4_is_slave(dev->dev)) {
557 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
558 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
563 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
574 static enum rdma_link_layer
575 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
577 struct mlx4_dev *dev = to_mdev(device)->dev;
579 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
580 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
583 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
584 struct ib_port_attr *props, int netw_view)
586 struct ib_smp *in_mad = NULL;
587 struct ib_smp *out_mad = NULL;
588 int ext_active_speed;
589 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
592 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
593 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
594 if (!in_mad || !out_mad)
597 init_query_mad(in_mad);
598 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
599 in_mad->attr_mod = cpu_to_be32(port);
601 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
602 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
604 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
610 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
611 props->lmc = out_mad->data[34] & 0x7;
612 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
613 props->sm_sl = out_mad->data[36] & 0xf;
614 props->state = out_mad->data[32] & 0xf;
615 props->phys_state = out_mad->data[33] >> 4;
616 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
618 props->gid_tbl_len = out_mad->data[50];
620 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
621 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
622 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
623 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
624 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
625 props->active_width = out_mad->data[31] & 0xf;
626 props->active_speed = out_mad->data[35] >> 4;
627 props->max_mtu = out_mad->data[41] & 0xf;
628 props->active_mtu = out_mad->data[36] >> 4;
629 props->subnet_timeout = out_mad->data[51] & 0x1f;
630 props->max_vl_num = out_mad->data[37] >> 4;
631 props->init_type_reply = out_mad->data[41] >> 4;
633 /* Check if extended speeds (EDR/FDR/...) are supported */
634 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
635 ext_active_speed = out_mad->data[62] >> 4;
637 switch (ext_active_speed) {
639 props->active_speed = IB_SPEED_FDR;
642 props->active_speed = IB_SPEED_EDR;
647 /* If reported active speed is QDR, check if is FDR-10 */
648 if (props->active_speed == IB_SPEED_QDR) {
649 init_query_mad(in_mad);
650 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
651 in_mad->attr_mod = cpu_to_be32(port);
653 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
654 NULL, NULL, in_mad, out_mad);
658 /* Checking LinkSpeedActive for FDR-10 */
659 if (out_mad->data[15] & 0x1)
660 props->active_speed = IB_SPEED_FDR10;
663 /* Avoid wrong speed value returned by FW if the IB link is down. */
664 if (props->state == IB_PORT_DOWN)
665 props->active_speed = IB_SPEED_SDR;
673 static u8 state_to_phys_state(enum ib_port_state state)
675 return state == IB_PORT_ACTIVE ? 5 : 3;
678 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
679 struct ib_port_attr *props, int netw_view)
682 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
683 struct mlx4_ib_iboe *iboe = &mdev->iboe;
684 struct net_device *ndev;
686 struct mlx4_cmd_mailbox *mailbox;
688 int is_bonded = mlx4_is_bonded(mdev->dev);
690 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
692 return PTR_ERR(mailbox);
694 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
695 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
700 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ?
701 IB_WIDTH_4X : IB_WIDTH_1X;
702 props->active_speed = IB_SPEED_QDR;
703 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
704 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
705 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
706 props->pkey_tbl_len = 1;
707 props->max_mtu = IB_MTU_4096;
708 props->max_vl_num = 2;
709 props->state = IB_PORT_DOWN;
710 props->phys_state = state_to_phys_state(props->state);
711 props->active_mtu = IB_MTU_256;
712 spin_lock_bh(&iboe->lock);
713 ndev = iboe->netdevs[port - 1];
714 if (ndev && is_bonded) {
715 rcu_read_lock(); /* required to get upper dev */
716 ndev = netdev_master_upper_dev_get_rcu(ndev);
722 tmp = iboe_get_mtu(ndev->mtu);
723 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
725 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
726 IB_PORT_ACTIVE : IB_PORT_DOWN;
727 props->phys_state = state_to_phys_state(props->state);
729 spin_unlock_bh(&iboe->lock);
731 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
735 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
736 struct ib_port_attr *props, int netw_view)
740 memset(props, 0, sizeof *props);
742 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
743 ib_link_query_port(ibdev, port, props, netw_view) :
744 eth_link_query_port(ibdev, port, props, netw_view);
749 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
750 struct ib_port_attr *props)
752 /* returns host view */
753 return __mlx4_ib_query_port(ibdev, port, props, 0);
756 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
757 union ib_gid *gid, int netw_view)
759 struct ib_smp *in_mad = NULL;
760 struct ib_smp *out_mad = NULL;
762 struct mlx4_ib_dev *dev = to_mdev(ibdev);
764 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
766 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
767 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
768 if (!in_mad || !out_mad)
771 init_query_mad(in_mad);
772 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
773 in_mad->attr_mod = cpu_to_be32(port);
775 if (mlx4_is_mfunc(dev->dev) && netw_view)
776 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
778 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
782 memcpy(gid->raw, out_mad->data + 8, 8);
784 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
786 /* For any index > 0, return the null guid */
793 init_query_mad(in_mad);
794 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
795 in_mad->attr_mod = cpu_to_be32(index / 8);
797 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
798 NULL, NULL, in_mad, out_mad);
802 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
806 memset(gid->raw + 8, 0, 8);
812 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
817 if (rdma_protocol_ib(ibdev, port))
818 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
820 if (!rdma_protocol_roce(ibdev, port))
823 if (!rdma_cap_roce_gid_table(ibdev, port))
826 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
827 if (ret == -EAGAIN) {
828 memcpy(gid, &zgid, sizeof(*gid));
835 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
837 union sl2vl_tbl_to_u64 sl2vl64;
838 struct ib_smp *in_mad = NULL;
839 struct ib_smp *out_mad = NULL;
840 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
844 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
849 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
850 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
851 if (!in_mad || !out_mad)
854 init_query_mad(in_mad);
855 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
856 in_mad->attr_mod = 0;
858 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
859 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
861 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
866 for (jj = 0; jj < 8; jj++)
867 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
868 *sl2vl_tbl = sl2vl64.sl64;
876 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
882 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
883 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
885 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
887 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
891 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
895 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
896 u16 *pkey, int netw_view)
898 struct ib_smp *in_mad = NULL;
899 struct ib_smp *out_mad = NULL;
900 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
903 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
904 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
905 if (!in_mad || !out_mad)
908 init_query_mad(in_mad);
909 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
910 in_mad->attr_mod = cpu_to_be32(index / 32);
912 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
913 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
915 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
920 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
928 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
930 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
933 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
934 struct ib_device_modify *props)
936 struct mlx4_cmd_mailbox *mailbox;
939 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
942 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
945 if (mlx4_is_slave(to_mdev(ibdev)->dev))
948 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
949 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
950 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
953 * If possible, pass node desc to FW, so it can generate
954 * a 144 trap. If cmd fails, just ignore.
956 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
960 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
961 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
962 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
964 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
969 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
972 struct mlx4_cmd_mailbox *mailbox;
975 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
977 return PTR_ERR(mailbox);
979 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
980 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
981 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
983 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
984 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
987 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
988 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
991 mlx4_free_cmd_mailbox(dev->dev, mailbox);
995 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
996 struct ib_port_modify *props)
998 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
999 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1000 struct ib_port_attr attr;
1004 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1005 * of whether port link layer is ETH or IB. For ETH ports, qkey
1006 * violations and port capabilities are not meaningful.
1011 mutex_lock(&mdev->cap_mask_mutex);
1013 err = mlx4_ib_query_port(ibdev, port, &attr);
1017 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1018 ~props->clr_port_cap_mask;
1020 err = mlx4_ib_SET_PORT(mdev, port,
1021 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1025 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1029 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1030 struct ib_udata *udata)
1032 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1033 struct mlx4_ib_ucontext *context;
1034 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1035 struct mlx4_ib_alloc_ucontext_resp resp;
1038 if (!dev->ib_active)
1039 return ERR_PTR(-EAGAIN);
1041 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1042 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1043 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1044 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1046 resp.dev_caps = dev->dev->caps.userspace_caps;
1047 resp.qp_tab_size = dev->dev->caps.num_qps;
1048 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1049 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1050 resp.cqe_size = dev->dev->caps.cqe_size;
1053 context = kzalloc(sizeof(*context), GFP_KERNEL);
1055 return ERR_PTR(-ENOMEM);
1057 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1060 return ERR_PTR(err);
1063 INIT_LIST_HEAD(&context->db_page_list);
1064 mutex_init(&context->db_page_mutex);
1066 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1067 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1069 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1072 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1074 return ERR_PTR(-EFAULT);
1077 return &context->ibucontext;
1080 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1082 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1084 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1090 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1092 /* vma_open is called when a new VMA is created on top of our VMA.
1093 * This is done through either mremap flow or split_vma (usually due
1094 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1095 * vma, as this VMA is strongly hardware related. Therefore we set the
1096 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1097 * calling us again and trying to do incorrect actions. We assume that
1098 * the original vma size is exactly a single page that there will be no
1099 * "splitting" operations on.
1101 area->vm_ops = NULL;
1104 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1106 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1108 /* It's guaranteed that all VMAs opened on a FD are closed before the
1109 * file itself is closed, therefore no sync is needed with the regular
1110 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1111 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1112 * The close operation is usually called under mm->mmap_sem except when
1113 * process is exiting. The exiting case is handled explicitly as part
1114 * of mlx4_ib_disassociate_ucontext.
1116 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1117 area->vm_private_data;
1119 /* set the vma context pointer to null in the mlx4_ib driver's private
1120 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1122 mlx4_ib_vma_priv_data->vma = NULL;
1125 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1126 .open = mlx4_ib_vma_open,
1127 .close = mlx4_ib_vma_close
1130 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1134 struct vm_area_struct *vma;
1135 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1136 struct task_struct *owning_process = NULL;
1137 struct mm_struct *owning_mm = NULL;
1139 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1140 if (!owning_process)
1143 owning_mm = get_task_mm(owning_process);
1145 pr_info("no mm, disassociate ucontext is pending task termination\n");
1147 /* make sure that task is dead before returning, it may
1148 * prevent a rare case of module down in parallel to a
1149 * call to mlx4_ib_vma_close.
1151 put_task_struct(owning_process);
1153 owning_process = get_pid_task(ibcontext->tgid,
1155 if (!owning_process ||
1156 owning_process->state == TASK_DEAD) {
1157 pr_info("disassociate ucontext done, task was terminated\n");
1158 /* in case task was dead need to release the task struct */
1160 put_task_struct(owning_process);
1166 /* need to protect from a race on closing the vma as part of
1167 * mlx4_ib_vma_close().
1169 down_read(&owning_mm->mmap_sem);
1170 for (i = 0; i < HW_BAR_COUNT; i++) {
1171 vma = context->hw_bar_info[i].vma;
1175 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1176 context->hw_bar_info[i].vma->vm_start,
1179 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1183 /* context going to be destroyed, should not access ops any more */
1184 context->hw_bar_info[i].vma->vm_ops = NULL;
1187 up_read(&owning_mm->mmap_sem);
1189 put_task_struct(owning_process);
1192 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1193 struct mlx4_ib_vma_private_data *vma_private_data)
1195 vma_private_data->vma = vma;
1196 vma->vm_private_data = vma_private_data;
1197 vma->vm_ops = &mlx4_ib_vm_ops;
1200 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1202 struct mlx4_ib_dev *dev = to_mdev(context->device);
1203 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1205 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1208 if (vma->vm_pgoff == 0) {
1209 /* We prevent double mmaping on same context */
1210 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1213 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1215 if (io_remap_pfn_range(vma, vma->vm_start,
1216 to_mucontext(context)->uar.pfn,
1217 PAGE_SIZE, vma->vm_page_prot))
1220 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1222 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1223 /* We prevent double mmaping on same context */
1224 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1227 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1229 if (io_remap_pfn_range(vma, vma->vm_start,
1230 to_mucontext(context)->uar.pfn +
1231 dev->dev->caps.num_uars,
1232 PAGE_SIZE, vma->vm_page_prot))
1235 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1237 } else if (vma->vm_pgoff == 3) {
1238 struct mlx4_clock_params params;
1241 /* We prevent double mmaping on same context */
1242 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1245 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1250 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1251 if (io_remap_pfn_range(vma, vma->vm_start,
1252 (pci_resource_start(dev->dev->persist->pdev,
1256 PAGE_SIZE, vma->vm_page_prot))
1259 mlx4_ib_set_vma_data(vma,
1260 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1268 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1269 struct ib_ucontext *context,
1270 struct ib_udata *udata)
1272 struct mlx4_ib_pd *pd;
1275 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1277 return ERR_PTR(-ENOMEM);
1279 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1282 return ERR_PTR(err);
1286 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1287 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1289 return ERR_PTR(-EFAULT);
1295 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1297 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1303 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1304 struct ib_ucontext *context,
1305 struct ib_udata *udata)
1307 struct mlx4_ib_xrcd *xrcd;
1308 struct ib_cq_init_attr cq_attr = {};
1311 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1312 return ERR_PTR(-ENOSYS);
1314 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1316 return ERR_PTR(-ENOMEM);
1318 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1322 xrcd->pd = ib_alloc_pd(ibdev, 0);
1323 if (IS_ERR(xrcd->pd)) {
1324 err = PTR_ERR(xrcd->pd);
1329 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1330 if (IS_ERR(xrcd->cq)) {
1331 err = PTR_ERR(xrcd->cq);
1335 return &xrcd->ibxrcd;
1338 ib_dealloc_pd(xrcd->pd);
1340 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1343 return ERR_PTR(err);
1346 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1348 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1349 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1350 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1356 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1358 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1359 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1360 struct mlx4_ib_gid_entry *ge;
1362 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1367 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1368 ge->port = mqp->port;
1372 mutex_lock(&mqp->mutex);
1373 list_add_tail(&ge->list, &mqp->gid_list);
1374 mutex_unlock(&mqp->mutex);
1379 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1380 struct mlx4_ib_counters *ctr_table)
1382 struct counter_index *counter, *tmp_count;
1384 mutex_lock(&ctr_table->mutex);
1385 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1387 if (counter->allocated)
1388 mlx4_counter_free(ibdev->dev, counter->index);
1389 list_del(&counter->list);
1392 mutex_unlock(&ctr_table->mutex);
1395 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1398 struct net_device *ndev;
1404 spin_lock_bh(&mdev->iboe.lock);
1405 ndev = mdev->iboe.netdevs[mqp->port - 1];
1408 spin_unlock_bh(&mdev->iboe.lock);
1418 struct mlx4_ib_steering {
1419 struct list_head list;
1420 struct mlx4_flow_reg_id reg_id;
1424 #define LAST_ETH_FIELD vlan_tag
1425 #define LAST_IB_FIELD sl
1426 #define LAST_IPV4_FIELD dst_ip
1427 #define LAST_TCP_UDP_FIELD src_port
1429 /* Field is the last supported field */
1430 #define FIELDS_NOT_SUPPORTED(filter, field)\
1431 memchr_inv((void *)&filter.field +\
1432 sizeof(filter.field), 0,\
1434 offsetof(typeof(filter), field) -\
1435 sizeof(filter.field))
1437 static int parse_flow_attr(struct mlx4_dev *dev,
1439 union ib_flow_spec *ib_spec,
1440 struct _rule_hw *mlx4_spec)
1442 enum mlx4_net_trans_rule_id type;
1444 switch (ib_spec->type) {
1445 case IB_FLOW_SPEC_ETH:
1446 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1449 type = MLX4_NET_TRANS_RULE_ID_ETH;
1450 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1452 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1454 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1455 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1457 case IB_FLOW_SPEC_IB:
1458 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1461 type = MLX4_NET_TRANS_RULE_ID_IB;
1462 mlx4_spec->ib.l3_qpn =
1463 cpu_to_be32(qp_num);
1464 mlx4_spec->ib.qpn_mask =
1465 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1469 case IB_FLOW_SPEC_IPV4:
1470 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1473 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1474 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1475 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1476 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1477 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1480 case IB_FLOW_SPEC_TCP:
1481 case IB_FLOW_SPEC_UDP:
1482 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1485 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1486 MLX4_NET_TRANS_RULE_ID_TCP :
1487 MLX4_NET_TRANS_RULE_ID_UDP;
1488 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1489 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1490 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1491 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1497 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1498 mlx4_hw_rule_sz(dev, type) < 0)
1500 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1501 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1502 return mlx4_hw_rule_sz(dev, type);
1505 struct default_rules {
1506 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1507 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1508 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1511 static const struct default_rules default_table[] = {
1513 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1514 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1515 .rules_create_list = {IB_FLOW_SPEC_IB},
1516 .link_layer = IB_LINK_LAYER_INFINIBAND
1520 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1521 struct ib_flow_attr *flow_attr)
1525 const struct default_rules *pdefault_rules = default_table;
1526 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1528 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1529 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1530 memset(&field_types, 0, sizeof(field_types));
1532 if (link_layer != pdefault_rules->link_layer)
1535 ib_flow = flow_attr + 1;
1536 /* we assume the specs are sorted */
1537 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1538 j < flow_attr->num_of_specs; k++) {
1539 union ib_flow_spec *current_flow =
1540 (union ib_flow_spec *)ib_flow;
1542 /* same layer but different type */
1543 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1544 (pdefault_rules->mandatory_fields[k] &
1545 IB_FLOW_SPEC_LAYER_MASK)) &&
1546 (current_flow->type !=
1547 pdefault_rules->mandatory_fields[k]))
1550 /* same layer, try match next one */
1551 if (current_flow->type ==
1552 pdefault_rules->mandatory_fields[k]) {
1555 ((union ib_flow_spec *)ib_flow)->size;
1559 ib_flow = flow_attr + 1;
1560 for (j = 0; j < flow_attr->num_of_specs;
1561 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1562 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1563 /* same layer and same type */
1564 if (((union ib_flow_spec *)ib_flow)->type ==
1565 pdefault_rules->mandatory_not_fields[k])
1574 static int __mlx4_ib_create_default_rules(
1575 struct mlx4_ib_dev *mdev,
1577 const struct default_rules *pdefault_rules,
1578 struct _rule_hw *mlx4_spec) {
1582 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1584 union ib_flow_spec ib_spec;
1585 switch (pdefault_rules->rules_create_list[i]) {
1589 case IB_FLOW_SPEC_IB:
1590 ib_spec.type = IB_FLOW_SPEC_IB;
1591 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1598 /* We must put empty rule, qpn is being ignored */
1599 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1602 pr_info("invalid parsing\n");
1606 mlx4_spec = (void *)mlx4_spec + ret;
1612 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1614 enum mlx4_net_trans_promisc_mode flow_type,
1620 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1621 struct mlx4_cmd_mailbox *mailbox;
1622 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1625 static const u16 __mlx4_domain[] = {
1626 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1627 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1628 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1629 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1632 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1633 pr_err("Invalid priority value %d\n", flow_attr->priority);
1637 if (domain >= IB_FLOW_DOMAIN_NUM) {
1638 pr_err("Invalid domain value %d\n", domain);
1642 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1645 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1646 if (IS_ERR(mailbox))
1647 return PTR_ERR(mailbox);
1648 ctrl = mailbox->buf;
1650 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1651 flow_attr->priority);
1652 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1653 ctrl->port = flow_attr->port;
1654 ctrl->qpn = cpu_to_be32(qp->qp_num);
1656 ib_flow = flow_attr + 1;
1657 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1658 /* Add default flows */
1659 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1660 if (default_flow >= 0) {
1661 ret = __mlx4_ib_create_default_rules(
1662 mdev, qp, default_table + default_flow,
1663 mailbox->buf + size);
1665 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1670 for (i = 0; i < flow_attr->num_of_specs; i++) {
1671 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1672 mailbox->buf + size);
1674 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1677 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1681 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1682 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1685 pr_err("mcg table is full. Fail to register network rule.\n");
1686 else if (ret == -ENXIO)
1687 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1689 pr_err("Invalid argument. Fail to register network rule.\n");
1691 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1695 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1698 err = mlx4_cmd(dev, reg_id, 0, 0,
1699 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1702 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1707 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1711 union ib_flow_spec *ib_spec;
1712 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1715 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1716 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1717 return 0; /* do nothing */
1719 ib_flow = flow_attr + 1;
1720 ib_spec = (union ib_flow_spec *)ib_flow;
1722 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1723 return 0; /* do nothing */
1725 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1726 flow_attr->port, qp->qp_num,
1727 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1732 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1733 struct ib_flow_attr *flow_attr,
1734 enum mlx4_net_trans_promisc_mode *type)
1738 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1739 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1740 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1744 if (flow_attr->num_of_specs == 0) {
1745 type[0] = MLX4_FS_MC_SNIFFER;
1746 type[1] = MLX4_FS_UC_SNIFFER;
1748 union ib_flow_spec *ib_spec;
1750 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1751 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1754 /* if all is zero than MC and UC */
1755 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1756 type[0] = MLX4_FS_MC_SNIFFER;
1757 type[1] = MLX4_FS_UC_SNIFFER;
1759 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1760 ib_spec->eth.mask.dst_mac[1],
1761 ib_spec->eth.mask.dst_mac[2],
1762 ib_spec->eth.mask.dst_mac[3],
1763 ib_spec->eth.mask.dst_mac[4],
1764 ib_spec->eth.mask.dst_mac[5]};
1766 /* Above xor was only on MC bit, non empty mask is valid
1767 * only if this bit is set and rest are zero.
1769 if (!is_zero_ether_addr(&mac[0]))
1772 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1773 type[0] = MLX4_FS_MC_SNIFFER;
1775 type[0] = MLX4_FS_UC_SNIFFER;
1782 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1783 struct ib_flow_attr *flow_attr,
1786 int err = 0, i = 0, j = 0;
1787 struct mlx4_ib_flow *mflow;
1788 enum mlx4_net_trans_promisc_mode type[2];
1789 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1790 int is_bonded = mlx4_is_bonded(dev);
1792 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1793 return ERR_PTR(-EINVAL);
1795 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1796 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1797 return ERR_PTR(-EOPNOTSUPP);
1799 memset(type, 0, sizeof(type));
1801 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1807 switch (flow_attr->type) {
1808 case IB_FLOW_ATTR_NORMAL:
1809 /* If dont trap flag (continue match) is set, under specific
1810 * condition traffic be replicated to given qp,
1811 * without stealing it
1813 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1814 err = mlx4_ib_add_dont_trap_rule(dev,
1820 type[0] = MLX4_FS_REGULAR;
1824 case IB_FLOW_ATTR_ALL_DEFAULT:
1825 type[0] = MLX4_FS_ALL_DEFAULT;
1828 case IB_FLOW_ATTR_MC_DEFAULT:
1829 type[0] = MLX4_FS_MC_DEFAULT;
1832 case IB_FLOW_ATTR_SNIFFER:
1833 type[0] = MLX4_FS_MIRROR_RX_PORT;
1834 type[1] = MLX4_FS_MIRROR_SX_PORT;
1842 while (i < ARRAY_SIZE(type) && type[i]) {
1843 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1844 &mflow->reg_id[i].id);
1846 goto err_create_flow;
1848 /* Application always sees one port so the mirror rule
1849 * must be on port #2
1851 flow_attr->port = 2;
1852 err = __mlx4_ib_create_flow(qp, flow_attr,
1854 &mflow->reg_id[j].mirror);
1855 flow_attr->port = 1;
1857 goto err_create_flow;
1864 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1865 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1866 &mflow->reg_id[i].id);
1868 goto err_create_flow;
1871 flow_attr->port = 2;
1872 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1873 &mflow->reg_id[j].mirror);
1874 flow_attr->port = 1;
1876 goto err_create_flow;
1879 /* function to create mirror rule */
1883 return &mflow->ibflow;
1887 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1888 mflow->reg_id[i].id);
1893 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1894 mflow->reg_id[j].mirror);
1899 return ERR_PTR(err);
1902 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1906 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1907 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1909 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1910 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1913 if (mflow->reg_id[i].mirror) {
1914 err = __mlx4_ib_destroy_flow(mdev->dev,
1915 mflow->reg_id[i].mirror);
1926 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1929 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1930 struct mlx4_dev *dev = mdev->dev;
1931 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1932 struct mlx4_ib_steering *ib_steering = NULL;
1933 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1934 struct mlx4_flow_reg_id reg_id;
1936 if (mdev->dev->caps.steering_mode ==
1937 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1938 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1943 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1945 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1948 pr_err("multicast attach op failed, err %d\n", err);
1953 if (mlx4_is_bonded(dev)) {
1954 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1955 (mqp->port == 1) ? 2 : 1,
1957 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1958 prot, ®_id.mirror);
1963 err = add_gid_entry(ibqp, gid);
1968 memcpy(ib_steering->gid.raw, gid->raw, 16);
1969 ib_steering->reg_id = reg_id;
1970 mutex_lock(&mqp->mutex);
1971 list_add(&ib_steering->list, &mqp->steering_rules);
1972 mutex_unlock(&mqp->mutex);
1977 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1980 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1981 prot, reg_id.mirror);
1988 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1990 struct mlx4_ib_gid_entry *ge;
1991 struct mlx4_ib_gid_entry *tmp;
1992 struct mlx4_ib_gid_entry *ret = NULL;
1994 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1995 if (!memcmp(raw, ge->gid.raw, 16)) {
2004 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2007 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2008 struct mlx4_dev *dev = mdev->dev;
2009 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2010 struct net_device *ndev;
2011 struct mlx4_ib_gid_entry *ge;
2012 struct mlx4_flow_reg_id reg_id = {0, 0};
2013 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2015 if (mdev->dev->caps.steering_mode ==
2016 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2017 struct mlx4_ib_steering *ib_steering;
2019 mutex_lock(&mqp->mutex);
2020 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2021 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2022 list_del(&ib_steering->list);
2026 mutex_unlock(&mqp->mutex);
2027 if (&ib_steering->list == &mqp->steering_rules) {
2028 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2031 reg_id = ib_steering->reg_id;
2035 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2040 if (mlx4_is_bonded(dev)) {
2041 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2042 prot, reg_id.mirror);
2047 mutex_lock(&mqp->mutex);
2048 ge = find_gid_entry(mqp, gid->raw);
2050 spin_lock_bh(&mdev->iboe.lock);
2051 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2054 spin_unlock_bh(&mdev->iboe.lock);
2057 list_del(&ge->list);
2060 pr_warn("could not find mgid entry\n");
2062 mutex_unlock(&mqp->mutex);
2067 static int init_node_data(struct mlx4_ib_dev *dev)
2069 struct ib_smp *in_mad = NULL;
2070 struct ib_smp *out_mad = NULL;
2071 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2074 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2075 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2076 if (!in_mad || !out_mad)
2079 init_query_mad(in_mad);
2080 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2081 if (mlx4_is_master(dev->dev))
2082 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2084 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2088 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2090 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2092 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2096 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2097 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2105 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2108 struct mlx4_ib_dev *dev =
2109 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2110 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2113 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2116 struct mlx4_ib_dev *dev =
2117 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2118 return sprintf(buf, "%x\n", dev->dev->rev_id);
2121 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2124 struct mlx4_ib_dev *dev =
2125 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2126 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2127 dev->dev->board_id);
2130 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2131 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2132 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2134 static struct device_attribute *mlx4_class_attributes[] = {
2140 struct diag_counter {
2145 #define DIAG_COUNTER(_name, _offset) \
2146 { .name = #_name, .offset = _offset }
2148 static const struct diag_counter diag_basic[] = {
2149 DIAG_COUNTER(rq_num_lle, 0x00),
2150 DIAG_COUNTER(sq_num_lle, 0x04),
2151 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2152 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2153 DIAG_COUNTER(rq_num_lpe, 0x18),
2154 DIAG_COUNTER(sq_num_lpe, 0x1C),
2155 DIAG_COUNTER(rq_num_wrfe, 0x20),
2156 DIAG_COUNTER(sq_num_wrfe, 0x24),
2157 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2158 DIAG_COUNTER(sq_num_bre, 0x34),
2159 DIAG_COUNTER(sq_num_rire, 0x44),
2160 DIAG_COUNTER(rq_num_rire, 0x48),
2161 DIAG_COUNTER(sq_num_rae, 0x4C),
2162 DIAG_COUNTER(rq_num_rae, 0x50),
2163 DIAG_COUNTER(sq_num_roe, 0x54),
2164 DIAG_COUNTER(sq_num_tree, 0x5C),
2165 DIAG_COUNTER(sq_num_rree, 0x64),
2166 DIAG_COUNTER(rq_num_rnr, 0x68),
2167 DIAG_COUNTER(sq_num_rnr, 0x6C),
2168 DIAG_COUNTER(rq_num_oos, 0x100),
2169 DIAG_COUNTER(sq_num_oos, 0x104),
2172 static const struct diag_counter diag_ext[] = {
2173 DIAG_COUNTER(rq_num_dup, 0x130),
2174 DIAG_COUNTER(sq_num_to, 0x134),
2177 static const struct diag_counter diag_device_only[] = {
2178 DIAG_COUNTER(num_cqovf, 0x1A0),
2179 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2182 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2185 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2186 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2188 if (!diag[!!port_num].name)
2191 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2192 diag[!!port_num].num_counters,
2193 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2196 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2197 struct rdma_hw_stats *stats,
2200 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2201 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2202 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2203 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2207 ret = mlx4_query_diag_counters(dev->dev,
2208 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2209 diag[!!port].offset, hw_value,
2210 diag[!!port].num_counters, port);
2215 for (i = 0; i < diag[!!port].num_counters; i++)
2216 stats->value[i] = hw_value[i];
2218 return diag[!!port].num_counters;
2221 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2229 num_counters = ARRAY_SIZE(diag_basic);
2231 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2232 num_counters += ARRAY_SIZE(diag_ext);
2235 num_counters += ARRAY_SIZE(diag_device_only);
2237 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2241 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2245 *num = num_counters;
2254 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2262 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2263 name[i] = diag_basic[i].name;
2264 offset[i] = diag_basic[i].offset;
2267 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2268 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2269 name[j] = diag_ext[i].name;
2270 offset[j] = diag_ext[i].offset;
2275 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2276 name[j] = diag_device_only[i].name;
2277 offset[j] = diag_device_only[i].offset;
2282 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2284 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2287 bool per_port = !!(ibdev->dev->caps.flags2 &
2288 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2290 if (mlx4_is_slave(ibdev->dev))
2293 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2294 /* i == 1 means we are building port counters */
2298 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2300 &diag[i].num_counters, i);
2304 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2308 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2309 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2315 kfree(diag[i - 1].name);
2316 kfree(diag[i - 1].offset);
2322 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2326 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2327 kfree(ibdev->diag_counters[i].offset);
2328 kfree(ibdev->diag_counters[i].name);
2332 #define MLX4_IB_INVALID_MAC ((u64)-1)
2333 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2334 struct net_device *dev,
2338 u64 release_mac = MLX4_IB_INVALID_MAC;
2339 struct mlx4_ib_qp *qp;
2341 read_lock(&dev_base_lock);
2342 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2343 read_unlock(&dev_base_lock);
2345 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2347 /* no need for update QP1 and mac registration in non-SRIOV */
2348 if (!mlx4_is_mfunc(ibdev->dev))
2351 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2352 qp = ibdev->qp1_proxy[port - 1];
2356 struct mlx4_update_qp_params update_params;
2358 mutex_lock(&qp->mutex);
2359 old_smac = qp->pri.smac;
2360 if (new_smac == old_smac)
2363 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2365 if (new_smac_index < 0)
2368 update_params.smac_index = new_smac_index;
2369 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2371 release_mac = new_smac;
2374 /* if old port was zero, no mac was yet registered for this QP */
2375 if (qp->pri.smac_port)
2376 release_mac = old_smac;
2377 qp->pri.smac = new_smac;
2378 qp->pri.smac_port = port;
2379 qp->pri.smac_index = new_smac_index;
2383 if (release_mac != MLX4_IB_INVALID_MAC)
2384 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2386 mutex_unlock(&qp->mutex);
2387 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2390 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2391 struct net_device *dev,
2392 unsigned long event)
2395 struct mlx4_ib_iboe *iboe;
2396 int update_qps_port = -1;
2401 iboe = &ibdev->iboe;
2403 spin_lock_bh(&iboe->lock);
2404 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2406 iboe->netdevs[port - 1] =
2407 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2409 if (dev == iboe->netdevs[port - 1] &&
2410 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2411 event == NETDEV_UP || event == NETDEV_CHANGE))
2412 update_qps_port = port;
2415 spin_unlock_bh(&iboe->lock);
2417 if (update_qps_port > 0)
2418 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2421 static int mlx4_ib_netdev_event(struct notifier_block *this,
2422 unsigned long event, void *ptr)
2424 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2425 struct mlx4_ib_dev *ibdev;
2427 if (!net_eq(dev_net(dev), &init_net))
2430 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2431 mlx4_ib_scan_netdevs(ibdev, dev, event);
2436 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2442 if (mlx4_is_master(ibdev->dev)) {
2443 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2445 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2447 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2449 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2450 /* master has the identity virt2phys pkey mapping */
2451 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2452 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2453 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2454 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2458 /* initialize pkey cache */
2459 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2461 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2463 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2469 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2471 int i, j, eq = 0, total_eqs = 0;
2473 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2474 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2475 if (!ibdev->eq_table)
2478 for (i = 1; i <= dev->caps.num_ports; i++) {
2479 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2481 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2483 ibdev->eq_table[eq] = total_eqs;
2484 if (!mlx4_assign_eq(dev, i,
2485 &ibdev->eq_table[eq]))
2488 ibdev->eq_table[eq] = -1;
2492 for (i = eq; i < dev->caps.num_comp_vectors;
2493 ibdev->eq_table[i++] = -1)
2496 /* Advertise the new number of EQs to clients */
2497 ibdev->ib_dev.num_comp_vectors = eq;
2500 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2503 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2505 /* no eqs were allocated */
2506 if (!ibdev->eq_table)
2509 /* Reset the advertised EQ number */
2510 ibdev->ib_dev.num_comp_vectors = 0;
2512 for (i = 0; i < total_eqs; i++)
2513 mlx4_release_eq(dev, ibdev->eq_table[i]);
2515 kfree(ibdev->eq_table);
2516 ibdev->eq_table = NULL;
2519 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2520 struct ib_port_immutable *immutable)
2522 struct ib_port_attr attr;
2523 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2526 err = mlx4_ib_query_port(ibdev, port_num, &attr);
2530 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2531 immutable->gid_tbl_len = attr.gid_tbl_len;
2533 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2534 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2536 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2537 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2538 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2539 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2540 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2543 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2548 static void get_fw_ver_str(struct ib_device *device, char *str,
2551 struct mlx4_ib_dev *dev =
2552 container_of(device, struct mlx4_ib_dev, ib_dev);
2553 snprintf(str, str_len, "%d.%d.%d",
2554 (int) (dev->dev->caps.fw_ver >> 32),
2555 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2556 (int) dev->dev->caps.fw_ver & 0xffff);
2559 static void *mlx4_ib_add(struct mlx4_dev *dev)
2561 struct mlx4_ib_dev *ibdev;
2565 struct mlx4_ib_iboe *iboe;
2566 int ib_num_ports = 0;
2567 int num_req_counters;
2570 struct counter_index *new_counter_index = NULL;
2572 pr_info_once("%s", mlx4_ib_version);
2575 mlx4_foreach_ib_transport_port(i, dev)
2578 /* No point in registering a device with no ports... */
2582 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2584 dev_err(&dev->persist->pdev->dev,
2585 "Device struct alloc failed\n");
2589 iboe = &ibdev->iboe;
2591 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2594 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2597 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2599 if (!ibdev->uar_map)
2601 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2604 ibdev->bond_next_port = 0;
2606 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2607 ibdev->ib_dev.owner = THIS_MODULE;
2608 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2609 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2610 ibdev->num_ports = num_ports;
2611 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2612 1 : ibdev->num_ports;
2613 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2614 ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
2615 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2616 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2617 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2619 if (dev->caps.userspace_caps)
2620 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2622 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2624 ibdev->ib_dev.uverbs_cmd_mask =
2625 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2626 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2627 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2628 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2629 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2630 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2631 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2632 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2633 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2634 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2635 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2636 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2637 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2638 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2639 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2640 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2641 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2642 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2643 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2644 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2645 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2646 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2647 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2648 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2650 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2651 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2652 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2653 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2654 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2655 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2656 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2657 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2658 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2659 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2660 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2661 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2662 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2663 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2664 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2665 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2666 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2667 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2668 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2669 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2670 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2671 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2672 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2673 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2674 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2675 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2676 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2677 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2678 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2679 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2680 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2681 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2682 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2683 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2684 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2685 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2686 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2687 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2688 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2689 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2690 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2691 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2692 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2693 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2695 if (!mlx4_is_slave(ibdev->dev)) {
2696 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2697 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2698 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2699 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2702 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2703 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2704 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2705 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2707 ibdev->ib_dev.uverbs_cmd_mask |=
2708 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2709 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2712 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2713 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2714 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2715 ibdev->ib_dev.uverbs_cmd_mask |=
2716 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2717 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2720 if (check_flow_steering_support(dev)) {
2721 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2722 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2723 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2725 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2726 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2727 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2730 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2731 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2732 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2733 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2735 mlx4_ib_alloc_eqs(dev, ibdev);
2737 spin_lock_init(&iboe->lock);
2739 if (init_node_data(ibdev))
2741 mlx4_init_sl2vl_tbl(ibdev);
2743 for (i = 0; i < ibdev->num_ports; ++i) {
2744 mutex_init(&ibdev->counters_table[i].mutex);
2745 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2748 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2749 for (i = 0; i < num_req_counters; ++i) {
2750 mutex_init(&ibdev->qp1_proxy_lock[i]);
2752 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2753 IB_LINK_LAYER_ETHERNET) {
2754 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2755 /* if failed to allocate a new counter, use default */
2758 mlx4_get_default_counter_index(dev,
2762 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2763 counter_index = mlx4_get_default_counter_index(dev,
2766 new_counter_index = kmalloc(sizeof(*new_counter_index),
2768 if (!new_counter_index) {
2770 mlx4_counter_free(ibdev->dev, counter_index);
2773 new_counter_index->index = counter_index;
2774 new_counter_index->allocated = allocated;
2775 list_add_tail(&new_counter_index->list,
2776 &ibdev->counters_table[i].counters_list);
2777 ibdev->counters_table[i].default_counter = counter_index;
2778 pr_info("counter index %d for port %d allocated %d\n",
2779 counter_index, i + 1, allocated);
2781 if (mlx4_is_bonded(dev))
2782 for (i = 1; i < ibdev->num_ports ; ++i) {
2784 kmalloc(sizeof(struct counter_index),
2786 if (!new_counter_index)
2788 new_counter_index->index = counter_index;
2789 new_counter_index->allocated = 0;
2790 list_add_tail(&new_counter_index->list,
2791 &ibdev->counters_table[i].counters_list);
2792 ibdev->counters_table[i].default_counter =
2796 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2799 spin_lock_init(&ibdev->sm_lock);
2800 mutex_init(&ibdev->cap_mask_mutex);
2801 INIT_LIST_HEAD(&ibdev->qp_list);
2802 spin_lock_init(&ibdev->reset_flow_resource_lock);
2804 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2806 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2807 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2808 MLX4_IB_UC_STEER_QPN_ALIGN,
2809 &ibdev->steer_qpn_base, 0);
2813 ibdev->ib_uc_qpns_bitmap =
2814 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2817 if (!ibdev->ib_uc_qpns_bitmap) {
2818 dev_err(&dev->persist->pdev->dev,
2819 "bit map alloc failed\n");
2820 goto err_steer_qp_release;
2823 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count);
2825 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2826 dev, ibdev->steer_qpn_base,
2827 ibdev->steer_qpn_base +
2828 ibdev->steer_qpn_count - 1);
2830 goto err_steer_free_bitmap;
2833 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2834 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2836 if (mlx4_ib_alloc_diag_counters(ibdev))
2837 goto err_steer_free_bitmap;
2839 if (ib_register_device(&ibdev->ib_dev, NULL))
2840 goto err_diag_counters;
2842 if (mlx4_ib_mad_init(ibdev))
2845 if (mlx4_ib_init_sriov(ibdev))
2848 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE ||
2849 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2850 if (!iboe->nb.notifier_call) {
2851 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2852 err = register_netdevice_notifier(&iboe->nb);
2854 iboe->nb.notifier_call = NULL;
2858 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2859 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2866 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2867 if (device_create_file(&ibdev->ib_dev.dev,
2868 mlx4_class_attributes[j]))
2872 ibdev->ib_active = true;
2873 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2874 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2877 if (mlx4_is_mfunc(ibdev->dev))
2880 /* create paravirt contexts for any VFs which are active */
2881 if (mlx4_is_master(ibdev->dev)) {
2882 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2883 if (j == mlx4_master_func_num(ibdev->dev))
2885 if (mlx4_is_slave_active(ibdev->dev, j))
2886 do_slave_init(ibdev, j, 1);
2892 if (ibdev->iboe.nb.notifier_call) {
2893 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2894 pr_warn("failure unregistering notifier\n");
2895 ibdev->iboe.nb.notifier_call = NULL;
2897 flush_workqueue(wq);
2899 mlx4_ib_close_sriov(ibdev);
2902 mlx4_ib_mad_cleanup(ibdev);
2905 ib_unregister_device(&ibdev->ib_dev);
2908 mlx4_ib_diag_cleanup(ibdev);
2910 err_steer_free_bitmap:
2911 kfree(ibdev->ib_uc_qpns_bitmap);
2913 err_steer_qp_release:
2914 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2915 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2916 ibdev->steer_qpn_count);
2918 for (i = 0; i < ibdev->num_ports; ++i)
2919 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2922 iounmap(ibdev->uar_map);
2925 mlx4_uar_free(dev, &ibdev->priv_uar);
2928 mlx4_pd_free(dev, ibdev->priv_pdn);
2931 ib_dealloc_device(&ibdev->ib_dev);
2936 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2940 WARN_ON(!dev->ib_uc_qpns_bitmap);
2942 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2943 dev->steer_qpn_count,
2944 get_count_order(count));
2948 *qpn = dev->steer_qpn_base + offset;
2952 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2955 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2958 BUG_ON(qpn < dev->steer_qpn_base);
2960 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2961 qpn - dev->steer_qpn_base,
2962 get_count_order(count));
2965 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2970 struct ib_flow_attr *flow = NULL;
2971 struct ib_flow_spec_ib *ib_spec;
2974 flow_size = sizeof(struct ib_flow_attr) +
2975 sizeof(struct ib_flow_spec_ib);
2976 flow = kzalloc(flow_size, GFP_KERNEL);
2979 flow->port = mqp->port;
2980 flow->num_of_specs = 1;
2981 flow->size = flow_size;
2982 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2983 ib_spec->type = IB_FLOW_SPEC_IB;
2984 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2985 /* Add an empty rule for IB L2 */
2986 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2988 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2993 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2999 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3001 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3005 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3006 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3007 ibdev->ib_active = false;
3008 flush_workqueue(wq);
3010 mlx4_ib_close_sriov(ibdev);
3011 mlx4_ib_mad_cleanup(ibdev);
3012 ib_unregister_device(&ibdev->ib_dev);
3013 mlx4_ib_diag_cleanup(ibdev);
3014 if (ibdev->iboe.nb.notifier_call) {
3015 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3016 pr_warn("failure unregistering notifier\n");
3017 ibdev->iboe.nb.notifier_call = NULL;
3020 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3021 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3022 ibdev->steer_qpn_count);
3023 kfree(ibdev->ib_uc_qpns_bitmap);
3026 iounmap(ibdev->uar_map);
3027 for (p = 0; p < ibdev->num_ports; ++p)
3028 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3030 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3031 mlx4_CLOSE_PORT(dev, p);
3033 mlx4_ib_free_eqs(dev, ibdev);
3035 mlx4_uar_free(dev, &ibdev->priv_uar);
3036 mlx4_pd_free(dev, ibdev->priv_pdn);
3037 ib_dealloc_device(&ibdev->ib_dev);
3040 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3042 struct mlx4_ib_demux_work **dm = NULL;
3043 struct mlx4_dev *dev = ibdev->dev;
3045 unsigned long flags;
3046 struct mlx4_active_ports actv_ports;
3048 unsigned int first_port;
3050 if (!mlx4_is_master(dev))
3053 actv_ports = mlx4_get_active_ports(dev, slave);
3054 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3055 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3057 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3059 pr_err("failed to allocate memory for tunneling qp update\n");
3063 for (i = 0; i < ports; i++) {
3064 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3066 pr_err("failed to allocate memory for tunneling qp update work struct\n");
3071 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3072 dm[i]->port = first_port + i + 1;
3073 dm[i]->slave = slave;
3074 dm[i]->do_init = do_init;
3077 /* initialize or tear down tunnel QPs for the slave */
3078 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3079 if (!ibdev->sriov.is_going_down) {
3080 for (i = 0; i < ports; i++)
3081 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3082 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3084 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3085 for (i = 0; i < ports; i++)
3093 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3095 struct mlx4_ib_qp *mqp;
3096 unsigned long flags_qp;
3097 unsigned long flags_cq;
3098 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3099 struct list_head cq_notify_list;
3100 struct mlx4_cq *mcq;
3101 unsigned long flags;
3103 pr_warn("mlx4_ib_handle_catas_error was started\n");
3104 INIT_LIST_HEAD(&cq_notify_list);
3106 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3107 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3109 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3110 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3111 if (mqp->sq.tail != mqp->sq.head) {
3112 send_mcq = to_mcq(mqp->ibqp.send_cq);
3113 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3114 if (send_mcq->mcq.comp &&
3115 mqp->ibqp.send_cq->comp_handler) {
3116 if (!send_mcq->mcq.reset_notify_added) {
3117 send_mcq->mcq.reset_notify_added = 1;
3118 list_add_tail(&send_mcq->mcq.reset_notify,
3122 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3124 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3125 /* Now, handle the QP's receive queue */
3126 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3127 /* no handling is needed for SRQ */
3128 if (!mqp->ibqp.srq) {
3129 if (mqp->rq.tail != mqp->rq.head) {
3130 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3131 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3132 if (recv_mcq->mcq.comp &&
3133 mqp->ibqp.recv_cq->comp_handler) {
3134 if (!recv_mcq->mcq.reset_notify_added) {
3135 recv_mcq->mcq.reset_notify_added = 1;
3136 list_add_tail(&recv_mcq->mcq.reset_notify,
3140 spin_unlock_irqrestore(&recv_mcq->lock,
3144 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3147 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3150 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3151 pr_warn("mlx4_ib_handle_catas_error ended\n");
3154 static void handle_bonded_port_state_event(struct work_struct *work)
3156 struct ib_event_work *ew =
3157 container_of(work, struct ib_event_work, work);
3158 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3159 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3161 struct ib_event ibev;
3164 spin_lock_bh(&ibdev->iboe.lock);
3165 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3166 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3167 enum ib_port_state curr_port_state;
3173 (netif_running(curr_netdev) &&
3174 netif_carrier_ok(curr_netdev)) ?
3175 IB_PORT_ACTIVE : IB_PORT_DOWN;
3177 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3178 curr_port_state : IB_PORT_ACTIVE;
3180 spin_unlock_bh(&ibdev->iboe.lock);
3182 ibev.device = &ibdev->ib_dev;
3183 ibev.element.port_num = 1;
3184 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3185 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3187 ib_dispatch_event(&ibev);
3190 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3195 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3197 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3201 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3204 static void ib_sl2vl_update_work(struct work_struct *work)
3206 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3207 struct mlx4_ib_dev *mdev = ew->ib_dev;
3208 int port = ew->port;
3210 mlx4_ib_sl2vl_update(mdev, port);
3215 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3218 struct ib_event_work *ew;
3220 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3222 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3225 queue_work(wq, &ew->work);
3227 pr_err("failed to allocate memory for sl2vl update work\n");
3231 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3232 enum mlx4_dev_event event, unsigned long param)
3234 struct ib_event ibev;
3235 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3236 struct mlx4_eqe *eqe = NULL;
3237 struct ib_event_work *ew;
3240 if (mlx4_is_bonded(dev) &&
3241 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3242 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3243 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3246 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3248 queue_work(wq, &ew->work);
3252 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3253 eqe = (struct mlx4_eqe *)param;
3258 case MLX4_DEV_EVENT_PORT_UP:
3259 if (p > ibdev->num_ports)
3261 if (!mlx4_is_slave(dev) &&
3262 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3263 IB_LINK_LAYER_INFINIBAND) {
3264 if (mlx4_is_master(dev))
3265 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3266 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3267 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3268 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3270 ibev.event = IB_EVENT_PORT_ACTIVE;
3273 case MLX4_DEV_EVENT_PORT_DOWN:
3274 if (p > ibdev->num_ports)
3276 ibev.event = IB_EVENT_PORT_ERR;
3279 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3280 ibdev->ib_active = false;
3281 ibev.event = IB_EVENT_DEVICE_FATAL;
3282 mlx4_ib_handle_catas_error(ibdev);
3285 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3286 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3288 pr_err("failed to allocate memory for events work\n");
3292 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3293 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3295 /* need to queue only for port owner, which uses GEN_EQE */
3296 if (mlx4_is_master(dev))
3297 queue_work(wq, &ew->work);
3299 handle_port_mgmt_change_event(&ew->work);
3302 case MLX4_DEV_EVENT_SLAVE_INIT:
3303 /* here, p is the slave id */
3304 do_slave_init(ibdev, p, 1);
3305 if (mlx4_is_master(dev)) {
3308 for (i = 1; i <= ibdev->num_ports; i++) {
3309 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3310 == IB_LINK_LAYER_INFINIBAND)
3311 mlx4_ib_slave_alias_guid_event(ibdev,
3318 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3319 if (mlx4_is_master(dev)) {
3322 for (i = 1; i <= ibdev->num_ports; i++) {
3323 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3324 == IB_LINK_LAYER_INFINIBAND)
3325 mlx4_ib_slave_alias_guid_event(ibdev,
3330 /* here, p is the slave id */
3331 do_slave_init(ibdev, p, 0);
3338 ibev.device = ibdev_ptr;
3339 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3341 ib_dispatch_event(&ibev);
3344 static struct mlx4_interface mlx4_ib_interface = {
3346 .remove = mlx4_ib_remove,
3347 .event = mlx4_ib_event,
3348 .protocol = MLX4_PROT_IB_IPV6,
3349 .flags = MLX4_INTFF_BONDING
3352 static int __init mlx4_ib_init(void)
3356 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3360 err = mlx4_ib_mcg_init();
3364 err = mlx4_register_interface(&mlx4_ib_interface);
3371 mlx4_ib_mcg_destroy();
3374 destroy_workqueue(wq);
3378 static void __exit mlx4_ib_cleanup(void)
3380 mlx4_unregister_interface(&mlx4_ib_interface);
3381 mlx4_ib_mcg_destroy();
3382 destroy_workqueue(wq);
3385 module_init(mlx4_ib_init);
3386 module_exit(mlx4_ib_cleanup);