2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
39 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
46 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
67 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
69 return mlx5_buf_offset(&buf->buf, n * size);
72 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
74 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
77 static u8 sw_ownership_bit(int n, int nent)
79 return (n & nent) ? 1 : 0;
82 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
84 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
85 struct mlx5_cqe64 *cqe64;
87 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
89 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
90 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
97 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
99 return get_sw_cqe(cq, cq->mcq.cons_index);
102 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
104 switch (wq->wr_data[idx]) {
108 case IB_WR_LOCAL_INV:
109 return IB_WC_LOCAL_INV;
115 pr_warn("unknown completion status\n");
120 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
121 struct mlx5_ib_wq *wq, int idx)
124 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
125 case MLX5_OPCODE_RDMA_WRITE_IMM:
126 wc->wc_flags |= IB_WC_WITH_IMM;
127 case MLX5_OPCODE_RDMA_WRITE:
128 wc->opcode = IB_WC_RDMA_WRITE;
130 case MLX5_OPCODE_SEND_IMM:
131 wc->wc_flags |= IB_WC_WITH_IMM;
132 case MLX5_OPCODE_SEND:
133 case MLX5_OPCODE_SEND_INVAL:
134 wc->opcode = IB_WC_SEND;
136 case MLX5_OPCODE_RDMA_READ:
137 wc->opcode = IB_WC_RDMA_READ;
138 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
140 case MLX5_OPCODE_ATOMIC_CS:
141 wc->opcode = IB_WC_COMP_SWAP;
144 case MLX5_OPCODE_ATOMIC_FA:
145 wc->opcode = IB_WC_FETCH_ADD;
148 case MLX5_OPCODE_ATOMIC_MASKED_CS:
149 wc->opcode = IB_WC_MASKED_COMP_SWAP;
152 case MLX5_OPCODE_ATOMIC_MASKED_FA:
153 wc->opcode = IB_WC_MASKED_FETCH_ADD;
156 case MLX5_OPCODE_UMR:
157 wc->opcode = get_umr_comp(wq, idx);
163 MLX5_GRH_IN_BUFFER = 1,
167 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
168 struct mlx5_ib_qp *qp)
170 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
171 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
172 struct mlx5_ib_srq *srq;
173 struct mlx5_ib_wq *wq;
177 if (qp->ibqp.srq || qp->ibqp.xrcd) {
178 struct mlx5_core_srq *msrq = NULL;
181 msrq = mlx5_core_get_srq(dev->mdev,
182 be32_to_cpu(cqe->srqn));
183 srq = to_mibsrq(msrq);
185 srq = to_msrq(qp->ibqp.srq);
188 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
189 wc->wr_id = srq->wrid[wqe_ctr];
190 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
191 if (msrq && atomic_dec_and_test(&msrq->refcount))
192 complete(&msrq->free);
196 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
199 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
201 switch (cqe->op_own >> 4) {
202 case MLX5_CQE_RESP_WR_IMM:
203 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
204 wc->wc_flags = IB_WC_WITH_IMM;
205 wc->ex.imm_data = cqe->imm_inval_pkey;
207 case MLX5_CQE_RESP_SEND:
208 wc->opcode = IB_WC_RECV;
209 wc->wc_flags = IB_WC_IP_CSUM_OK;
210 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
211 (cqe->hds_ip_ext & CQE_L4_OK))))
214 case MLX5_CQE_RESP_SEND_IMM:
215 wc->opcode = IB_WC_RECV;
216 wc->wc_flags = IB_WC_WITH_IMM;
217 wc->ex.imm_data = cqe->imm_inval_pkey;
219 case MLX5_CQE_RESP_SEND_INV:
220 wc->opcode = IB_WC_RECV;
221 wc->wc_flags = IB_WC_WITH_INVALIDATE;
222 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
225 wc->slid = be16_to_cpu(cqe->slid);
226 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
227 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
228 wc->dlid_path_bits = cqe->ml_path;
229 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
230 wc->wc_flags |= g ? IB_WC_GRH : 0;
231 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
232 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
234 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
240 if (ll != IB_LINK_LAYER_ETHERNET)
243 switch (wc->sl & 0x3) {
244 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
245 wc->network_hdr_type = RDMA_NETWORK_IB;
247 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
248 wc->network_hdr_type = RDMA_NETWORK_IPV6;
250 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
251 wc->network_hdr_type = RDMA_NETWORK_IPV4;
254 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
257 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
259 __be32 *p = (__be32 *)cqe;
262 mlx5_ib_warn(dev, "dump error cqe\n");
263 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
264 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
265 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
269 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
270 struct mlx5_err_cqe *cqe,
275 switch (cqe->syndrome) {
276 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
277 wc->status = IB_WC_LOC_LEN_ERR;
279 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
280 wc->status = IB_WC_LOC_QP_OP_ERR;
282 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
283 wc->status = IB_WC_LOC_PROT_ERR;
285 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
287 wc->status = IB_WC_WR_FLUSH_ERR;
289 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
290 wc->status = IB_WC_MW_BIND_ERR;
292 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
293 wc->status = IB_WC_BAD_RESP_ERR;
295 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
296 wc->status = IB_WC_LOC_ACCESS_ERR;
298 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
299 wc->status = IB_WC_REM_INV_REQ_ERR;
301 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
302 wc->status = IB_WC_REM_ACCESS_ERR;
304 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
305 wc->status = IB_WC_REM_OP_ERR;
307 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
308 wc->status = IB_WC_RETRY_EXC_ERR;
311 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
312 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
315 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
316 wc->status = IB_WC_REM_ABORT_ERR;
319 wc->status = IB_WC_GENERAL_ERR;
323 wc->vendor_err = cqe->vendor_err_synd;
328 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
330 /* TBD: waiting decision
335 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
337 struct mlx5_wqe_data_seg *dpseg;
340 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
341 sizeof(struct mlx5_wqe_raddr_seg) +
342 sizeof(struct mlx5_wqe_atomic_seg);
343 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
347 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
354 if (!is_atomic_response(qp, idx))
357 byte_count = be32_to_cpu(cqe64->byte_cnt);
358 addr = mlx5_get_atomic_laddr(qp, idx);
360 if (byte_count == 4) {
361 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
363 for (i = 0; i < byte_count; i += 8) {
364 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
372 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
378 idx = tail & (qp->sq.wqe_cnt - 1);
379 handle_atomic(qp, cqe64, idx);
383 tail = qp->sq.w_list[idx].next;
385 tail = qp->sq.w_list[idx].next;
386 qp->sq.last_poll = tail;
389 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
391 mlx5_buf_free(dev->mdev, &buf->buf);
394 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
395 struct ib_sig_err *item)
397 u16 syndrome = be16_to_cpu(cqe->syndrome);
399 #define GUARD_ERR (1 << 13)
400 #define APPTAG_ERR (1 << 12)
401 #define REFTAG_ERR (1 << 11)
403 if (syndrome & GUARD_ERR) {
404 item->err_type = IB_SIG_BAD_GUARD;
405 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
406 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
408 if (syndrome & REFTAG_ERR) {
409 item->err_type = IB_SIG_BAD_REFTAG;
410 item->expected = be32_to_cpu(cqe->expected_reftag);
411 item->actual = be32_to_cpu(cqe->actual_reftag);
413 if (syndrome & APPTAG_ERR) {
414 item->err_type = IB_SIG_BAD_APPTAG;
415 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
416 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
418 pr_err("Got signature completion error with bad syndrome %04x\n",
422 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
423 item->key = be32_to_cpu(cqe->mkey);
426 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
427 struct ib_wc *wc, int *npolled)
429 struct mlx5_ib_wq *wq;
436 cur = wq->head - wq->tail;
442 for (i = 0; i < cur && np < num_entries; i++) {
443 idx = wq->last_poll & (wq->wqe_cnt - 1);
444 wc->wr_id = wq->wrid[idx];
445 wc->status = IB_WC_WR_FLUSH_ERR;
446 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
451 wq->last_poll = wq->w_list[idx].next;
456 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
457 struct ib_wc *wc, int *npolled)
459 struct mlx5_ib_wq *wq;
465 cur = wq->head - wq->tail;
471 for (i = 0; i < cur && np < num_entries; i++) {
472 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
473 wc->status = IB_WC_WR_FLUSH_ERR;
474 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
483 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
484 struct ib_wc *wc, int *npolled)
486 struct mlx5_ib_qp *qp;
489 /* Find uncompleted WQEs belonging to that cq and retrun mmics ones */
490 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
491 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
492 if (*npolled >= num_entries)
496 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
497 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
498 if (*npolled >= num_entries)
503 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
504 struct mlx5_ib_qp **cur_qp,
507 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
508 struct mlx5_err_cqe *err_cqe;
509 struct mlx5_cqe64 *cqe64;
510 struct mlx5_core_qp *mqp;
511 struct mlx5_ib_wq *wq;
512 struct mlx5_sig_err_cqe *sig_err_cqe;
513 struct mlx5_core_mkey *mmkey;
514 struct mlx5_ib_mr *mr;
522 cqe = next_cqe_sw(cq);
526 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
528 ++cq->mcq.cons_index;
530 /* Make sure we read CQ entry contents after we've checked the
535 opcode = cqe64->op_own >> 4;
536 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
537 if (likely(cq->resize_buf)) {
538 free_cq_buf(dev, &cq->buf);
539 cq->buf = *cq->resize_buf;
540 kfree(cq->resize_buf);
541 cq->resize_buf = NULL;
544 mlx5_ib_warn(dev, "unexpected resize cqe\n");
548 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
549 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
550 /* We do not have to take the QP table lock here,
551 * because CQs will be locked while QPs are removed
554 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
555 if (unlikely(!mqp)) {
556 mlx5_ib_warn(dev, "CQE@CQ %06x for unknown QPN %6x\n",
561 *cur_qp = to_mibqp(mqp);
564 wc->qp = &(*cur_qp)->ibqp;
568 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
569 idx = wqe_ctr & (wq->wqe_cnt - 1);
570 handle_good_req(wc, cqe64, wq, idx);
571 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
572 wc->wr_id = wq->wrid[idx];
573 wq->tail = wq->wqe_head[idx] + 1;
574 wc->status = IB_WC_SUCCESS;
576 case MLX5_CQE_RESP_WR_IMM:
577 case MLX5_CQE_RESP_SEND:
578 case MLX5_CQE_RESP_SEND_IMM:
579 case MLX5_CQE_RESP_SEND_INV:
580 handle_responder(wc, cqe64, *cur_qp);
581 wc->status = IB_WC_SUCCESS;
583 case MLX5_CQE_RESIZE_CQ:
585 case MLX5_CQE_REQ_ERR:
586 case MLX5_CQE_RESP_ERR:
587 err_cqe = (struct mlx5_err_cqe *)cqe64;
588 mlx5_handle_error_cqe(dev, err_cqe, wc);
589 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
590 opcode == MLX5_CQE_REQ_ERR ?
591 "Requestor" : "Responder", cq->mcq.cqn);
592 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
593 err_cqe->syndrome, err_cqe->vendor_err_synd);
594 if (opcode == MLX5_CQE_REQ_ERR) {
596 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
597 idx = wqe_ctr & (wq->wqe_cnt - 1);
598 wc->wr_id = wq->wrid[idx];
599 wq->tail = wq->wqe_head[idx] + 1;
601 struct mlx5_ib_srq *srq;
603 if ((*cur_qp)->ibqp.srq) {
604 srq = to_msrq((*cur_qp)->ibqp.srq);
605 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
606 wc->wr_id = srq->wrid[wqe_ctr];
607 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
610 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
615 case MLX5_CQE_SIG_ERR:
616 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
618 read_lock(&dev->mdev->priv.mkey_table.lock);
619 mmkey = __mlx5_mr_lookup(dev->mdev,
620 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
621 if (unlikely(!mmkey)) {
622 read_unlock(&dev->mdev->priv.mkey_table.lock);
623 mlx5_ib_warn(dev, "CQE@CQ %06x for unknown MR %6x\n",
624 cq->mcq.cqn, be32_to_cpu(sig_err_cqe->mkey));
628 mr = to_mibmr(mmkey);
629 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
630 mr->sig->sig_err_exists = true;
631 mr->sig->sigerr_count++;
633 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
634 cq->mcq.cqn, mr->sig->err_item.key,
635 mr->sig->err_item.err_type,
636 mr->sig->err_item.sig_err_offset,
637 mr->sig->err_item.expected,
638 mr->sig->err_item.actual);
640 read_unlock(&dev->mdev->priv.mkey_table.lock);
647 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
650 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
651 struct mlx5_ib_wc *soft_wc, *next;
654 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
655 if (npolled >= num_entries)
658 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
661 wc[npolled++] = soft_wc->wc;
662 list_del(&soft_wc->list);
669 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
671 struct mlx5_ib_cq *cq = to_mcq(ibcq);
672 struct mlx5_ib_qp *cur_qp = NULL;
673 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
674 struct mlx5_core_dev *mdev = dev->mdev;
680 spin_lock_irqsave(&cq->lock, flags);
681 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
682 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
686 if (unlikely(!list_empty(&cq->wc_list)))
687 soft_polled = poll_soft_wc(cq, num_entries, wc);
689 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
690 err = mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled);
696 mlx5_cq_set_ci(&cq->mcq);
698 spin_unlock_irqrestore(&cq->lock, flags);
700 if (err == 0 || err == -EAGAIN)
701 return soft_polled + npolled;
706 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
708 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
709 struct mlx5_ib_cq *cq = to_mcq(ibcq);
710 void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
711 unsigned long irq_flags;
714 spin_lock_irqsave(&cq->lock, irq_flags);
715 if (cq->notify_flags != IB_CQ_NEXT_COMP)
716 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
718 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
720 spin_unlock_irqrestore(&cq->lock, irq_flags);
722 mlx5_cq_arm(&cq->mcq,
723 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
724 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
726 MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
727 to_mcq(ibcq)->mcq.cons_index);
732 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
733 int nent, int cqe_size)
737 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
741 buf->cqe_size = cqe_size;
747 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
748 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
749 int entries, u32 **cqb,
750 int *cqe_size, int *index, int *inlen)
752 struct mlx5_ib_create_cq ucmd;
762 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
763 sizeof(ucmd)) ? (sizeof(ucmd) -
764 sizeof(ucmd.reserved)) : sizeof(ucmd);
766 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
769 if (ucmdlen == sizeof(ucmd) &&
773 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
776 *cqe_size = ucmd.cqe_size;
778 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
779 entries * ucmd.cqe_size,
780 IB_ACCESS_LOCAL_WRITE, 1);
781 if (IS_ERR(cq->buf.umem)) {
782 err = PTR_ERR(cq->buf.umem);
786 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
791 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
793 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
794 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
796 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
797 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
798 *cqb = mlx5_vzalloc(*inlen);
804 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
805 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
807 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
808 MLX5_SET(cqc, cqc, log_page_size,
809 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
811 *index = to_mucontext(context)->uuari.uars[0].index;
816 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
819 ib_umem_release(cq->buf.umem);
823 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
825 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
826 ib_umem_release(cq->buf.umem);
829 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
833 struct mlx5_cqe64 *cqe64;
835 for (i = 0; i < buf->nent; i++) {
836 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
837 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
838 cqe64->op_own = MLX5_CQE_INVALID << 4;
842 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
843 int entries, int cqe_size,
844 u32 **cqb, int *index, int *inlen)
850 err = mlx5_db_alloc(dev->mdev, &cq->db);
854 cq->mcq.set_ci_db = cq->db.db;
855 cq->mcq.arm_db = cq->db.db + 1;
856 cq->mcq.cqe_sz = cqe_size;
858 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
862 init_cq_buf(cq, &cq->buf);
864 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
865 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages;
866 *cqb = mlx5_vzalloc(*inlen);
872 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
873 mlx5_fill_page_array(&cq->buf.buf, pas);
875 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
876 MLX5_SET(cqc, cqc, log_page_size,
877 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
879 *index = dev->mdev->priv.uuari.uars[0].index;
884 free_cq_buf(dev, &cq->buf);
887 mlx5_db_free(dev->mdev, &cq->db);
891 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
893 free_cq_buf(dev, &cq->buf);
894 mlx5_db_free(dev->mdev, &cq->db);
897 static void notify_soft_wc_handler(struct work_struct *work)
899 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
902 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
905 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
906 const struct ib_cq_init_attr *attr,
907 struct ib_ucontext *context,
908 struct ib_udata *udata)
910 int entries = attr->cqe;
911 int vector = attr->comp_vector;
912 struct mlx5_ib_dev *dev = to_mdev(ibdev);
913 struct mlx5_ib_cq *cq;
914 int uninitialized_var(index);
915 int uninitialized_var(inlen);
924 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
925 return ERR_PTR(-EINVAL);
927 if (check_cq_create_flags(attr->flags))
928 return ERR_PTR(-EOPNOTSUPP);
930 entries = roundup_pow_of_two(entries + 1);
931 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
932 return ERR_PTR(-EINVAL);
934 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
936 return ERR_PTR(-ENOMEM);
938 cq->ibcq.cqe = entries - 1;
939 mutex_init(&cq->resize_mutex);
940 spin_lock_init(&cq->lock);
941 cq->resize_buf = NULL;
942 cq->resize_umem = NULL;
943 cq->create_flags = attr->flags;
944 INIT_LIST_HEAD(&cq->list_send_qp);
945 INIT_LIST_HEAD(&cq->list_recv_qp);
948 err = create_cq_user(dev, udata, context, cq, entries,
949 &cqb, &cqe_size, &index, &inlen);
953 /* for now choose 64 bytes till we have a proper interface */
955 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
960 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
963 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
967 cq->cqe_size = cqe_size;
969 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
970 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
971 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
972 MLX5_SET(cqc, cqc, uar_page, index);
973 MLX5_SET(cqc, cqc, c_eqn, eqn);
974 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
975 if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
976 MLX5_SET(cqc, cqc, oi, 1);
978 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
982 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
985 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
987 cq->mcq.comp = mlx5_ib_cq_comp;
988 cq->mcq.event = mlx5_ib_cq_event;
990 INIT_LIST_HEAD(&cq->wc_list);
993 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1003 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1008 destroy_cq_user(cq, context);
1010 destroy_cq_kernel(dev, cq);
1015 return ERR_PTR(err);
1019 int mlx5_ib_destroy_cq(struct ib_cq *cq)
1021 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1022 struct mlx5_ib_cq *mcq = to_mcq(cq);
1023 struct ib_ucontext *context = NULL;
1026 context = cq->uobject->context;
1028 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1030 destroy_cq_user(mcq, context);
1032 destroy_cq_kernel(dev, mcq);
1039 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1041 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1044 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1046 struct mlx5_cqe64 *cqe64, *dest64;
1055 /* First we need to find the current producer index, so we
1056 * know where to start cleaning from. It doesn't matter if HW
1057 * adds new entries after this loop -- the QP we're worried
1058 * about is already in RESET, so the new entries won't come
1059 * from our QP and therefore don't need to be checked.
1061 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1062 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1065 /* Now sweep backwards through the CQ, removing CQ entries
1066 * that match our QP by copying older entries on top of them.
1068 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1069 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1070 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1071 if (is_equal_rsn(cqe64, rsn)) {
1072 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1073 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1075 } else if (nfreed) {
1076 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1077 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1078 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1079 memcpy(dest, cqe, cq->mcq.cqe_sz);
1080 dest64->op_own = owner_bit |
1081 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1086 cq->mcq.cons_index += nfreed;
1087 /* Make sure update of buffer contents is done before
1088 * updating consumer index.
1091 mlx5_cq_set_ci(&cq->mcq);
1095 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1100 spin_lock_irq(&cq->lock);
1101 __mlx5_ib_cq_clean(cq, qpn, srq);
1102 spin_unlock_irq(&cq->lock);
1105 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1107 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1108 struct mlx5_ib_cq *mcq = to_mcq(cq);
1111 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1114 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1115 cq_period, cq_count);
1117 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1122 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1123 int entries, struct ib_udata *udata, int *npas,
1124 int *page_shift, int *cqe_size)
1126 struct mlx5_ib_resize_cq ucmd;
1127 struct ib_umem *umem;
1130 struct ib_ucontext *context = cq->buf.umem->context;
1132 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1136 if (ucmd.reserved0 || ucmd.reserved1)
1139 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1140 IB_ACCESS_LOCAL_WRITE, 1);
1142 err = PTR_ERR(umem);
1146 mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
1149 cq->resize_umem = umem;
1150 *cqe_size = ucmd.cqe_size;
1155 static void un_resize_user(struct mlx5_ib_cq *cq)
1157 ib_umem_release(cq->resize_umem);
1160 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1161 int entries, int cqe_size)
1165 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1166 if (!cq->resize_buf)
1169 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1173 init_cq_buf(cq, cq->resize_buf);
1178 kfree(cq->resize_buf);
1182 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1184 free_cq_buf(dev, cq->resize_buf);
1185 cq->resize_buf = NULL;
1188 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1190 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1191 struct mlx5_cqe64 *scqe64;
1192 struct mlx5_cqe64 *dcqe64;
1201 ssize = cq->buf.cqe_size;
1202 dsize = cq->resize_buf->cqe_size;
1203 if (ssize != dsize) {
1204 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1208 i = cq->mcq.cons_index;
1209 scqe = get_sw_cqe(cq, i);
1210 scqe64 = ssize == 64 ? scqe : scqe + 64;
1213 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1217 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1218 dcqe = get_cqe_from_buf(cq->resize_buf,
1219 (i + 1) & (cq->resize_buf->nent),
1221 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1222 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1223 memcpy(dcqe, scqe, dsize);
1224 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1227 scqe = get_sw_cqe(cq, i);
1228 scqe64 = ssize == 64 ? scqe : scqe + 64;
1230 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1234 if (scqe == start_cqe) {
1235 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1240 ++cq->mcq.cons_index;
1244 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1246 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1247 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1255 int uninitialized_var(cqe_size);
1256 unsigned long flags;
1258 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1259 pr_info("Firmware does not support resize CQ\n");
1264 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1265 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1267 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1271 entries = roundup_pow_of_two(entries + 1);
1272 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1275 if (entries == ibcq->cqe + 1)
1278 mutex_lock(&cq->resize_mutex);
1280 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1284 err = resize_kernel(dev, cq, entries, cqe_size);
1286 npas = cq->resize_buf->buf.npages;
1287 page_shift = cq->resize_buf->buf.page_shift;
1294 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1295 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1297 in = mlx5_vzalloc(inlen);
1303 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1305 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1308 mlx5_fill_page_array(&cq->resize_buf->buf, pas);
1310 MLX5_SET(modify_cq_in, in,
1311 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1312 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1313 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1314 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1316 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1318 MLX5_SET(cqc, cqc, log_page_size,
1319 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1320 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size));
1321 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1323 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1324 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1326 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1331 cq->ibcq.cqe = entries - 1;
1332 ib_umem_release(cq->buf.umem);
1333 cq->buf.umem = cq->resize_umem;
1334 cq->resize_umem = NULL;
1336 struct mlx5_ib_cq_buf tbuf;
1339 spin_lock_irqsave(&cq->lock, flags);
1340 if (cq->resize_buf) {
1341 err = copy_resize_cqes(cq);
1344 cq->buf = *cq->resize_buf;
1345 kfree(cq->resize_buf);
1346 cq->resize_buf = NULL;
1350 cq->ibcq.cqe = entries - 1;
1351 spin_unlock_irqrestore(&cq->lock, flags);
1353 free_cq_buf(dev, &tbuf);
1355 mutex_unlock(&cq->resize_mutex);
1367 un_resize_kernel(dev, cq);
1369 mutex_unlock(&cq->resize_mutex);
1373 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1375 struct mlx5_ib_cq *cq;
1381 return cq->cqe_size;
1384 /* Called from atomic context */
1385 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1387 struct mlx5_ib_wc *soft_wc;
1388 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1389 unsigned long flags;
1391 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1396 spin_lock_irqsave(&cq->lock, flags);
1397 list_add_tail(&soft_wc->list, &cq->wc_list);
1398 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1399 wc->status != IB_WC_SUCCESS) {
1400 cq->notify_flags = 0;
1401 schedule_work(&cq->notify_work);
1403 spin_unlock_irqrestore(&cq->lock, flags);