drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_addr.h>
  48 #include <rdma/ib_cache.h>
  49 #include <linux/mlx5/port.h>
  50 #include <linux/mlx5/vport.h>
  51 #include <linux/list.h>
  52 #include <rdma/ib_smi.h>
  53 #include <rdma/ib_umem.h>
  54 #include <linux/in.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/mlx5/fs.h>
  57 #include "user.h"
  58 #include "mlx5_ib.h"
  59
  60 #define DRIVER_NAME "mlx5_ib"
  61 #define DRIVER_VERSION "2.2-1"
  62 #define DRIVER_RELDATE  "Feb 2014"
  63
  64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  66 MODULE_LICENSE("Dual BSD/GPL");
  67 MODULE_VERSION(DRIVER_VERSION);
  68
  69 static int deprecated_prof_sel = 2;
  70 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  71 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  72
  73 static char mlx5_version[] =
  74         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  75         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  76
  77 enum {
  78         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  79 };
  80
  81 static enum rdma_link_layer
  82 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  83 {
  84         switch (port_type_cap) {
  85         case MLX5_CAP_PORT_TYPE_IB:
  86                 return IB_LINK_LAYER_INFINIBAND;
  87         case MLX5_CAP_PORT_TYPE_ETH:
  88                 return IB_LINK_LAYER_ETHERNET;
  89         default:
  90                 return IB_LINK_LAYER_UNSPECIFIED;
  91         }
  92 }
  93
  94 static enum rdma_link_layer
  95 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  96 {
  97         struct mlx5_ib_dev *dev = to_mdev(device);
  98         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  99
 100         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 101 }
 102
 103 static int mlx5_netdev_event(struct notifier_block *this,
 104                              unsigned long event, void *ptr)
 105 {
 106         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 107         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 108                                                  roce.nb);
 109
 110         if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
 111                 return NOTIFY_DONE;
 112
 113         write_lock(&ibdev->roce.netdev_lock);
 114         if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 115                 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
 116         write_unlock(&ibdev->roce.netdev_lock);
 117
 118         return NOTIFY_DONE;
 119 }
 120
 121 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 122                                              u8 port_num)
 123 {
 124         struct mlx5_ib_dev *ibdev = to_mdev(device);
 125         struct net_device *ndev;
 126
 127         /* Ensure ndev does not disappear before we invoke dev_hold()
 128          */
 129         read_lock(&ibdev->roce.netdev_lock);
 130         ndev = ibdev->roce.netdev;
 131         if (ndev)
 132                 dev_hold(ndev);
 133         read_unlock(&ibdev->roce.netdev_lock);
 134
 135         return ndev;
 136 }
 137
 138 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 139                                 struct ib_port_attr *props)
 140 {
 141         struct mlx5_ib_dev *dev = to_mdev(device);
 142         struct net_device *ndev;
 143         enum ib_mtu ndev_ib_mtu;
 144         u16 qkey_viol_cntr;
 145
 146         memset(props, 0, sizeof(*props));
 147
 148         props->port_cap_flags  |= IB_PORT_CM_SUP;
 149         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 150
 151         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 152                                                 roce_address_table_size);
 153         props->max_mtu          = IB_MTU_4096;
 154         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 155         props->pkey_tbl_len     = 1;
 156         props->state            = IB_PORT_DOWN;
 157         props->phys_state       = 3;
 158
 159         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 160         props->qkey_viol_cntr = qkey_viol_cntr;
 161
 162         ndev = mlx5_ib_get_netdev(device, port_num);
 163         if (!ndev)
 164                 return 0;
 165
 166         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 167                 props->state      = IB_PORT_ACTIVE;
 168                 props->phys_state = 5;
 169         }
 170
 171         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 172
 173         dev_put(ndev);
 174
 175         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 176
 177         props->active_width     = IB_WIDTH_4X;  /* TODO */
 178         props->active_speed     = IB_SPEED_QDR; /* TODO */
 179
 180         return 0;
 181 }
 182
 183 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 184                                      const struct ib_gid_attr *attr,
 185                                      void *mlx5_addr)
 186 {
 187 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 188         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 189                                                source_l3_address);
 190         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 191                                                source_mac_47_32);
 192
 193         if (!gid)
 194                 return;
 195
 196         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 197
 198         if (is_vlan_dev(attr->ndev)) {
 199                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 200                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 201         }
 202
 203         switch (attr->gid_type) {
 204         case IB_GID_TYPE_IB:
 205                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 206                 break;
 207         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 208                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 209                 break;
 210
 211         default:
 212                 WARN_ON(true);
 213         }
 214
 215         if (attr->gid_type != IB_GID_TYPE_IB) {
 216                 if (ipv6_addr_v4mapped((void *)gid))
 217                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 218                                     MLX5_ROCE_L3_TYPE_IPV4);
 219                 else
 220                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 221                                     MLX5_ROCE_L3_TYPE_IPV6);
 222         }
 223
 224         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 225             !ipv6_addr_v4mapped((void *)gid))
 226                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 227         else
 228                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 229 }
 230
 231 static int set_roce_addr(struct ib_device *device, u8 port_num,
 232                          unsigned int index,
 233                          const union ib_gid *gid,
 234                          const struct ib_gid_attr *attr)
 235 {
 236         struct mlx5_ib_dev *dev = to_mdev(device);
 237         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 238         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 239         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 240         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 241
 242         if (ll != IB_LINK_LAYER_ETHERNET)
 243                 return -EINVAL;
 244
 245         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 246
 247         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 248         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 249         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 250 }
 251
 252 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 253                            unsigned int index, const union ib_gid *gid,
 254                            const struct ib_gid_attr *attr,
 255                            __always_unused void **context)
 256 {
 257         return set_roce_addr(device, port_num, index, gid, attr);
 258 }
 259
 260 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 261                            unsigned int index, __always_unused void **context)
 262 {
 263         return set_roce_addr(device, port_num, index, NULL, NULL);
 264 }
 265
 266 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 267                                int index)
 268 {
 269         struct ib_gid_attr attr;
 270         union ib_gid gid;
 271
 272         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 273                 return 0;
 274
 275         if (!attr.ndev)
 276                 return 0;
 277
 278         dev_put(attr.ndev);
 279
 280         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 281                 return 0;
 282
 283         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 284 }
 285
 286 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 287 {
 288         return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 289 }
 290
 291 enum {
 292         MLX5_VPORT_ACCESS_METHOD_MAD,
 293         MLX5_VPORT_ACCESS_METHOD_HCA,
 294         MLX5_VPORT_ACCESS_METHOD_NIC,
 295 };
 296
 297 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 298 {
 299         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 300                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 301
 302         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 303             IB_LINK_LAYER_ETHERNET)
 304                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 305
 306         return MLX5_VPORT_ACCESS_METHOD_HCA;
 307 }
 308
 309 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 310                             struct ib_device_attr *props)
 311 {
 312         u8 tmp;
 313         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 314         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 315         u8 atomic_req_8B_endianness_mode =
 316                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 317
 318         /* Check if HW supports 8 bytes standard atomic operations and capable
 319          * of host endianness respond
 320          */
 321         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 322         if (((atomic_operations & tmp) == tmp) &&
 323             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 324             (atomic_req_8B_endianness_mode)) {
 325                 props->atomic_cap = IB_ATOMIC_HCA;
 326         } else {
 327                 props->atomic_cap = IB_ATOMIC_NONE;
 328         }
 329 }
 330
 331 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 332                                         __be64 *sys_image_guid)
 333 {
 334         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 335         struct mlx5_core_dev *mdev = dev->mdev;
 336         u64 tmp;
 337         int err;
 338
 339         switch (mlx5_get_vport_access_method(ibdev)) {
 340         case MLX5_VPORT_ACCESS_METHOD_MAD:
 341                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 342                                                             sys_image_guid);
 343
 344         case MLX5_VPORT_ACCESS_METHOD_HCA:
 345                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 346                 break;
 347
 348         case MLX5_VPORT_ACCESS_METHOD_NIC:
 349                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 350                 break;
 351
 352         default:
 353                 return -EINVAL;
 354         }
 355
 356         if (!err)
 357                 *sys_image_guid = cpu_to_be64(tmp);
 358
 359         return err;
 360
 361 }
 362
 363 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 364                                 u16 *max_pkeys)
 365 {
 366         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 367         struct mlx5_core_dev *mdev = dev->mdev;
 368
 369         switch (mlx5_get_vport_access_method(ibdev)) {
 370         case MLX5_VPORT_ACCESS_METHOD_MAD:
 371                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 372
 373         case MLX5_VPORT_ACCESS_METHOD_HCA:
 374         case MLX5_VPORT_ACCESS_METHOD_NIC:
 375                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 376                                                 pkey_table_size));
 377                 return 0;
 378
 379         default:
 380                 return -EINVAL;
 381         }
 382 }
 383
 384 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 385                                 u32 *vendor_id)
 386 {
 387         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 388
 389         switch (mlx5_get_vport_access_method(ibdev)) {
 390         case MLX5_VPORT_ACCESS_METHOD_MAD:
 391                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 392
 393         case MLX5_VPORT_ACCESS_METHOD_HCA:
 394         case MLX5_VPORT_ACCESS_METHOD_NIC:
 395                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 396
 397         default:
 398                 return -EINVAL;
 399         }
 400 }
 401
 402 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 403                                 __be64 *node_guid)
 404 {
 405         u64 tmp;
 406         int err;
 407
 408         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 409         case MLX5_VPORT_ACCESS_METHOD_MAD:
 410                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 411
 412         case MLX5_VPORT_ACCESS_METHOD_HCA:
 413                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 414                 break;
 415
 416         case MLX5_VPORT_ACCESS_METHOD_NIC:
 417                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 418                 break;
 419
 420         default:
 421                 return -EINVAL;
 422         }
 423
 424         if (!err)
 425                 *node_guid = cpu_to_be64(tmp);
 426
 427         return err;
 428 }
 429
 430 struct mlx5_reg_node_desc {
 431         u8      desc[64];
 432 };
 433
 434 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 435 {
 436         struct mlx5_reg_node_desc in;
 437
 438         if (mlx5_use_mad_ifc(dev))
 439                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 440
 441         memset(&in, 0, sizeof(in));
 442
 443         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 444                                     sizeof(struct mlx5_reg_node_desc),
 445                                     MLX5_REG_NODE_DESC, 0, 0);
 446 }
 447
 448 static int mlx5_ib_query_device(struct ib_device *ibdev,
 449                                 struct ib_device_attr *props,
 450                                 struct ib_udata *uhw)
 451 {
 452         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 453         struct mlx5_core_dev *mdev = dev->mdev;
 454         int err = -ENOMEM;
 455         int max_rq_sg;
 456         int max_sq_sg;
 457         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 458         struct mlx5_ib_query_device_resp resp = {};
 459         size_t resp_len;
 460         u64 max_tso;
 461
 462         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 463         if (uhw->outlen && uhw->outlen < resp_len)
 464                 return -EINVAL;
 465         else
 466                 resp.response_length = resp_len;
 467
 468         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 469                 return -EINVAL;
 470
 471         memset(props, 0, sizeof(*props));
 472         err = mlx5_query_system_image_guid(ibdev,
 473                                            &props->sys_image_guid);
 474         if (err)
 475                 return err;
 476
 477         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 478         if (err)
 479                 return err;
 480
 481         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 482         if (err)
 483                 return err;
 484
 485         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 486                 (fw_rev_min(dev->mdev) << 16) |
 487                 fw_rev_sub(dev->mdev);
 488         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 489                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 490                 IB_DEVICE_SYS_IMAGE_GUID                |
 491                 IB_DEVICE_RC_RNR_NAK_GEN;
 492
 493         if (MLX5_CAP_GEN(mdev, pkv))
 494                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 495         if (MLX5_CAP_GEN(mdev, qkv))
 496                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 497         if (MLX5_CAP_GEN(mdev, apm))
 498                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 499         if (MLX5_CAP_GEN(mdev, xrc))
 500                 props->device_cap_flags |= IB_DEVICE_XRC;
 501         if (MLX5_CAP_GEN(mdev, imaicl)) {
 502                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 503                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 504                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 505                 /* We support 'Gappy' memory registration too */
 506                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 507         }
 508         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 509         if (MLX5_CAP_GEN(mdev, sho)) {
 510                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 511                 /* At this stage no support for signature handover */
 512                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 513                                       IB_PROT_T10DIF_TYPE_2 |
 514                                       IB_PROT_T10DIF_TYPE_3;
 515                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 516                                        IB_GUARD_T10DIF_CSUM;
 517         }
 518         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 519                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 520
 521         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 522                 if (MLX5_CAP_ETH(mdev, csum_cap))
 523                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 524
 525                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 526                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 527                         if (max_tso) {
 528                                 resp.tso_caps.max_tso = 1 << max_tso;
 529                                 resp.tso_caps.supported_qpts |=
 530                                         1 << IB_QPT_RAW_PACKET;
 531                                 resp.response_length += sizeof(resp.tso_caps);
 532                         }
 533                 }
 534
 535                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 536                         resp.rss_caps.rx_hash_function =
 537                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 538                         resp.rss_caps.rx_hash_fields_mask =
 539                                                 MLX5_RX_HASH_SRC_IPV4 |
 540                                                 MLX5_RX_HASH_DST_IPV4 |
 541                                                 MLX5_RX_HASH_SRC_IPV6 |
 542                                                 MLX5_RX_HASH_DST_IPV6 |
 543                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 544                                                 MLX5_RX_HASH_DST_PORT_TCP |
 545                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 546                                                 MLX5_RX_HASH_DST_PORT_UDP;
 547                         resp.response_length += sizeof(resp.rss_caps);
 548                 }
 549         } else {
 550                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 551                         resp.response_length += sizeof(resp.tso_caps);
 552                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 553                         resp.response_length += sizeof(resp.rss_caps);
 554         }
 555
 556         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 557                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 558                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 559         }
 560
 561         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 562             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 563                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 564
 565         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 566                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 567
 568         props->vendor_part_id      = mdev->pdev->device;
 569         props->hw_ver              = mdev->pdev->revision;
 570
 571         props->max_mr_size         = ~0ull;
 572         props->page_size_cap       = ~(min_page_size - 1);
 573         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 574         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 575         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 576                      sizeof(struct mlx5_wqe_data_seg);
 577         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 578                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 579                      sizeof(struct mlx5_wqe_data_seg);
 580         props->max_sge = min(max_rq_sg, max_sq_sg);
 581         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 582         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 583         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 584         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 585         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 586         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 587         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 588         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 589         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 590         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 591         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 592         props->max_srq_sge         = max_rq_sg - 1;
 593         props->max_fast_reg_page_list_len =
 594                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 595         get_atomic_caps(dev, props);
 596         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 597         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 598         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 599         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 600                                            props->max_mcast_grp;
 601         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 602         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 603         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 604
 605 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 606         if (MLX5_CAP_GEN(mdev, pg))
 607                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 608         props->odp_caps = dev->odp_caps;
 609 #endif
 610
 611         if (MLX5_CAP_GEN(mdev, cd))
 612                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 613
 614         if (!mlx5_core_is_pf(mdev))
 615                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 616
 617         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 618             IB_LINK_LAYER_ETHERNET) {
 619                 props->rss_caps.max_rwq_indirection_tables =
 620                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 621                 props->rss_caps.max_rwq_indirection_table_size =
 622                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 623                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 624                 props->max_wq_type_rq =
 625                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 626         }
 627
 628         if (uhw->outlen) {
 629                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 630
 631                 if (err)
 632                         return err;
 633         }
 634
 635         return 0;
 636 }
 637
 638 enum mlx5_ib_width {
 639         MLX5_IB_WIDTH_1X        = 1 << 0,
 640         MLX5_IB_WIDTH_2X        = 1 << 1,
 641         MLX5_IB_WIDTH_4X        = 1 << 2,
 642         MLX5_IB_WIDTH_8X        = 1 << 3,
 643         MLX5_IB_WIDTH_12X       = 1 << 4
 644 };
 645
 646 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 647                                   u8 *ib_width)
 648 {
 649         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 650         int err = 0;
 651
 652         if (active_width & MLX5_IB_WIDTH_1X) {
 653                 *ib_width = IB_WIDTH_1X;
 654         } else if (active_width & MLX5_IB_WIDTH_2X) {
 655                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 656                             (int)active_width);
 657                 err = -EINVAL;
 658         } else if (active_width & MLX5_IB_WIDTH_4X) {
 659                 *ib_width = IB_WIDTH_4X;
 660         } else if (active_width & MLX5_IB_WIDTH_8X) {
 661                 *ib_width = IB_WIDTH_8X;
 662         } else if (active_width & MLX5_IB_WIDTH_12X) {
 663                 *ib_width = IB_WIDTH_12X;
 664         } else {
 665                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 666                             (int)active_width);
 667                 err = -EINVAL;
 668         }
 669
 670         return err;
 671 }
 672
 673 static int mlx5_mtu_to_ib_mtu(int mtu)
 674 {
 675         switch (mtu) {
 676         case 256: return 1;
 677         case 512: return 2;
 678         case 1024: return 3;
 679         case 2048: return 4;
 680         case 4096: return 5;
 681         default:
 682                 pr_warn("invalid mtu\n");
 683                 return -1;
 684         }
 685 }
 686
 687 enum ib_max_vl_num {
 688         __IB_MAX_VL_0           = 1,
 689         __IB_MAX_VL_0_1         = 2,
 690         __IB_MAX_VL_0_3         = 3,
 691         __IB_MAX_VL_0_7         = 4,
 692         __IB_MAX_VL_0_14        = 5,
 693 };
 694
 695 enum mlx5_vl_hw_cap {
 696         MLX5_VL_HW_0    = 1,
 697         MLX5_VL_HW_0_1  = 2,
 698         MLX5_VL_HW_0_2  = 3,
 699         MLX5_VL_HW_0_3  = 4,
 700         MLX5_VL_HW_0_4  = 5,
 701         MLX5_VL_HW_0_5  = 6,
 702         MLX5_VL_HW_0_6  = 7,
 703         MLX5_VL_HW_0_7  = 8,
 704         MLX5_VL_HW_0_14 = 15
 705 };
 706
 707 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 708                                 u8 *max_vl_num)
 709 {
 710         switch (vl_hw_cap) {
 711         case MLX5_VL_HW_0:
 712                 *max_vl_num = __IB_MAX_VL_0;
 713                 break;
 714         case MLX5_VL_HW_0_1:
 715                 *max_vl_num = __IB_MAX_VL_0_1;
 716                 break;
 717         case MLX5_VL_HW_0_3:
 718                 *max_vl_num = __IB_MAX_VL_0_3;
 719                 break;
 720         case MLX5_VL_HW_0_7:
 721                 *max_vl_num = __IB_MAX_VL_0_7;
 722                 break;
 723         case MLX5_VL_HW_0_14:
 724                 *max_vl_num = __IB_MAX_VL_0_14;
 725                 break;
 726
 727         default:
 728                 return -EINVAL;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 735                                struct ib_port_attr *props)
 736 {
 737         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 738         struct mlx5_core_dev *mdev = dev->mdev;
 739         struct mlx5_hca_vport_context *rep;
 740         u16 max_mtu;
 741         u16 oper_mtu;
 742         int err;
 743         u8 ib_link_width_oper;
 744         u8 vl_hw_cap;
 745
 746         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 747         if (!rep) {
 748                 err = -ENOMEM;
 749                 goto out;
 750         }
 751
 752         memset(props, 0, sizeof(*props));
 753
 754         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 755         if (err)
 756                 goto out;
 757
 758         props->lid              = rep->lid;
 759         props->lmc              = rep->lmc;
 760         props->sm_lid           = rep->sm_lid;
 761         props->sm_sl            = rep->sm_sl;
 762         props->state            = rep->vport_state;
 763         props->phys_state       = rep->port_physical_state;
 764         props->port_cap_flags   = rep->cap_mask1;
 765         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 766         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 767         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 768         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 769         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 770         props->subnet_timeout   = rep->subnet_timeout;
 771         props->init_type_reply  = rep->init_type_reply;
 772         props->grh_required     = rep->grh_required;
 773
 774         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 775         if (err)
 776                 goto out;
 777
 778         err = translate_active_width(ibdev, ib_link_width_oper,
 779                                      &props->active_width);
 780         if (err)
 781                 goto out;
 782         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 783         if (err)
 784                 goto out;
 785
 786         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 787
 788         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 789
 790         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 791
 792         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 793
 794         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 795         if (err)
 796                 goto out;
 797
 798         err = translate_max_vl_num(ibdev, vl_hw_cap,
 799                                    &props->max_vl_num);
 800 out:
 801         kfree(rep);
 802         return err;
 803 }
 804
 805 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 806                        struct ib_port_attr *props)
 807 {
 808         switch (mlx5_get_vport_access_method(ibdev)) {
 809         case MLX5_VPORT_ACCESS_METHOD_MAD:
 810                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 811
 812         case MLX5_VPORT_ACCESS_METHOD_HCA:
 813                 return mlx5_query_hca_port(ibdev, port, props);
 814
 815         case MLX5_VPORT_ACCESS_METHOD_NIC:
 816                 return mlx5_query_port_roce(ibdev, port, props);
 817
 818         default:
 819                 return -EINVAL;
 820         }
 821 }
 822
 823 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 824                              union ib_gid *gid)
 825 {
 826         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 827         struct mlx5_core_dev *mdev = dev->mdev;
 828
 829         switch (mlx5_get_vport_access_method(ibdev)) {
 830         case MLX5_VPORT_ACCESS_METHOD_MAD:
 831                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 832
 833         case MLX5_VPORT_ACCESS_METHOD_HCA:
 834                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 835
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840 }
 841
 842 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 843                               u16 *pkey)
 844 {
 845         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 846         struct mlx5_core_dev *mdev = dev->mdev;
 847
 848         switch (mlx5_get_vport_access_method(ibdev)) {
 849         case MLX5_VPORT_ACCESS_METHOD_MAD:
 850                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 851
 852         case MLX5_VPORT_ACCESS_METHOD_HCA:
 853         case MLX5_VPORT_ACCESS_METHOD_NIC:
 854                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 855                                                  pkey);
 856         default:
 857                 return -EINVAL;
 858         }
 859 }
 860
 861 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 862                                  struct ib_device_modify *props)
 863 {
 864         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 865         struct mlx5_reg_node_desc in;
 866         struct mlx5_reg_node_desc out;
 867         int err;
 868
 869         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 870                 return -EOPNOTSUPP;
 871
 872         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 873                 return 0;
 874
 875         /*
 876          * If possible, pass node desc to FW, so it can generate
 877          * a 144 trap.  If cmd fails, just ignore.
 878          */
 879         memcpy(&in, props->node_desc, 64);
 880         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 881                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 882         if (err)
 883                 return err;
 884
 885         memcpy(ibdev->node_desc, props->node_desc, 64);
 886
 887         return err;
 888 }
 889
 890 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 891                                struct ib_port_modify *props)
 892 {
 893         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 894         struct ib_port_attr attr;
 895         u32 tmp;
 896         int err;
 897
 898         mutex_lock(&dev->cap_mask_mutex);
 899
 900         err = mlx5_ib_query_port(ibdev, port, &attr);
 901         if (err)
 902                 goto out;
 903
 904         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 905                 ~props->clr_port_cap_mask;
 906
 907         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 908
 909 out:
 910         mutex_unlock(&dev->cap_mask_mutex);
 911         return err;
 912 }
 913
 914 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 915                                                   struct ib_udata *udata)
 916 {
 917         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 918         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 919         struct mlx5_ib_alloc_ucontext_resp resp = {};
 920         struct mlx5_ib_ucontext *context;
 921         struct mlx5_uuar_info *uuari;
 922         struct mlx5_uar *uars;
 923         int gross_uuars;
 924         int num_uars;
 925         int ver;
 926         int uuarn;
 927         int err;
 928         int i;
 929         size_t reqlen;
 930         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 931                                      max_cqe_version);
 932
 933         if (!dev->ib_active)
 934                 return ERR_PTR(-EAGAIN);
 935
 936         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 937                 return ERR_PTR(-EINVAL);
 938
 939         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 940         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 941                 ver = 0;
 942         else if (reqlen >= min_req_v2)
 943                 ver = 2;
 944         else
 945                 return ERR_PTR(-EINVAL);
 946
 947         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 948         if (err)
 949                 return ERR_PTR(err);
 950
 951         if (req.flags)
 952                 return ERR_PTR(-EINVAL);
 953
 954         if (req.total_num_uuars > MLX5_MAX_UUARS)
 955                 return ERR_PTR(-ENOMEM);
 956
 957         if (req.total_num_uuars == 0)
 958                 return ERR_PTR(-EINVAL);
 959
 960         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 961                 return ERR_PTR(-EOPNOTSUPP);
 962
 963         if (reqlen > sizeof(req) &&
 964             !ib_is_udata_cleared(udata, sizeof(req),
 965                                  reqlen - sizeof(req)))
 966                 return ERR_PTR(-EOPNOTSUPP);
 967
 968         req.total_num_uuars = ALIGN(req.total_num_uuars,
 969                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
 970         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
 971                 return ERR_PTR(-EINVAL);
 972
 973         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
 974         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
 975         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
 976         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
 977                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
 978         resp.cache_line_size = L1_CACHE_BYTES;
 979         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
 980         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
 981         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 982         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 983         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
 984         resp.cqe_version = min_t(__u8,
 985                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
 986                                  req.max_cqe_version);
 987         resp.response_length = min(offsetof(typeof(resp), response_length) +
 988                                    sizeof(resp.response_length), udata->outlen);
 989
 990         context = kzalloc(sizeof(*context), GFP_KERNEL);
 991         if (!context)
 992                 return ERR_PTR(-ENOMEM);
 993
 994         uuari = &context->uuari;
 995         mutex_init(&uuari->lock);
 996         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
 997         if (!uars) {
 998                 err = -ENOMEM;
 999                 goto out_ctx;
1000         }
1001
1002         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1003                                 sizeof(*uuari->bitmap),
1004                                 GFP_KERNEL);
1005         if (!uuari->bitmap) {
1006                 err = -ENOMEM;
1007                 goto out_uar_ctx;
1008         }
1009         /*
1010          * clear all fast path uuars
1011          */
1012         for (i = 0; i < gross_uuars; i++) {
1013                 uuarn = i & 3;
1014                 if (uuarn == 2 || uuarn == 3)
1015                         set_bit(i, uuari->bitmap);
1016         }
1017
1018         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1019         if (!uuari->count) {
1020                 err = -ENOMEM;
1021                 goto out_bitmap;
1022         }
1023
1024         for (i = 0; i < num_uars; i++) {
1025                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1026                 if (err)
1027                         goto out_count;
1028         }
1029
1030 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1031         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1032 #endif
1033
1034         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1035                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1036                                                        &context->tdn);
1037                 if (err)
1038                         goto out_uars;
1039         }
1040
1041         INIT_LIST_HEAD(&context->vma_private_list);
1042         INIT_LIST_HEAD(&context->db_page_list);
1043         mutex_init(&context->db_page_mutex);
1044
1045         resp.tot_uuars = req.total_num_uuars;
1046         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1047
1048         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1049                 resp.response_length += sizeof(resp.cqe_version);
1050
1051         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1052                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1053                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1054         }
1055
1056         /*
1057          * We don't want to expose information from the PCI bar that is located
1058          * after 4096 bytes, so if the arch only supports larger pages, let's
1059          * pretend we don't support reading the HCA's core clock. This is also
1060          * forced by mmap function.
1061          */
1062         if (PAGE_SIZE <= 4096 &&
1063             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1064                 resp.comp_mask |=
1065                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1066                 resp.hca_core_clock_offset =
1067                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1068                         PAGE_SIZE;
1069                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1070                                         sizeof(resp.reserved2);
1071         }
1072
1073         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1074         if (err)
1075                 goto out_td;
1076
1077         uuari->ver = ver;
1078         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1079         uuari->uars = uars;
1080         uuari->num_uars = num_uars;
1081         context->cqe_version = resp.cqe_version;
1082
1083         return &context->ibucontext;
1084
1085 out_td:
1086         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1087                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1088
1089 out_uars:
1090         for (i--; i >= 0; i--)
1091                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1092 out_count:
1093         kfree(uuari->count);
1094
1095 out_bitmap:
1096         kfree(uuari->bitmap);
1097
1098 out_uar_ctx:
1099         kfree(uars);
1100
1101 out_ctx:
1102         kfree(context);
1103         return ERR_PTR(err);
1104 }
1105
1106 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1107 {
1108         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1109         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1110         struct mlx5_uuar_info *uuari = &context->uuari;
1111         int i;
1112
1113         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1114                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1115
1116         for (i = 0; i < uuari->num_uars; i++) {
1117                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1118                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1119         }
1120
1121         kfree(uuari->count);
1122         kfree(uuari->bitmap);
1123         kfree(uuari->uars);
1124         kfree(context);
1125
1126         return 0;
1127 }
1128
1129 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1130 {
1131         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1132 }
1133
1134 static int get_command(unsigned long offset)
1135 {
1136         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1137 }
1138
1139 static int get_arg(unsigned long offset)
1140 {
1141         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1142 }
1143
1144 static int get_index(unsigned long offset)
1145 {
1146         return get_arg(offset);
1147 }
1148
1149 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1150 {
1151         /* vma_open is called when a new VMA is created on top of our VMA.  This
1152          * is done through either mremap flow or split_vma (usually due to
1153          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1154          * as this VMA is strongly hardware related.  Therefore we set the
1155          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1156          * calling us again and trying to do incorrect actions.  We assume that
1157          * the original VMA size is exactly a single page, and therefore all
1158          * "splitting" operation will not happen to it.
1159          */
1160         area->vm_ops = NULL;
1161 }
1162
1163 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1164 {
1165         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1166
1167         /* It's guaranteed that all VMAs opened on a FD are closed before the
1168          * file itself is closed, therefore no sync is needed with the regular
1169          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1170          * However need a sync with accessing the vma as part of
1171          * mlx5_ib_disassociate_ucontext.
1172          * The close operation is usually called under mm->mmap_sem except when
1173          * process is exiting.
1174          * The exiting case is handled explicitly as part of
1175          * mlx5_ib_disassociate_ucontext.
1176          */
1177         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1178
1179         /* setting the vma context pointer to null in the mlx5_ib driver's
1180          * private data, to protect a race condition in
1181          * mlx5_ib_disassociate_ucontext().
1182          */
1183         mlx5_ib_vma_priv_data->vma = NULL;
1184         list_del(&mlx5_ib_vma_priv_data->list);
1185         kfree(mlx5_ib_vma_priv_data);
1186 }
1187
1188 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1189         .open = mlx5_ib_vma_open,
1190         .close = mlx5_ib_vma_close
1191 };
1192
1193 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1194                                 struct mlx5_ib_ucontext *ctx)
1195 {
1196         struct mlx5_ib_vma_private_data *vma_prv;
1197         struct list_head *vma_head = &ctx->vma_private_list;
1198
1199         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1200         if (!vma_prv)
1201                 return -ENOMEM;
1202
1203         vma_prv->vma = vma;
1204         vma->vm_private_data = vma_prv;
1205         vma->vm_ops =  &mlx5_ib_vm_ops;
1206
1207         list_add(&vma_prv->list, vma_head);
1208
1209         return 0;
1210 }
1211
1212 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1213 {
1214         int ret;
1215         struct vm_area_struct *vma;
1216         struct mlx5_ib_vma_private_data *vma_private, *n;
1217         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1218         struct task_struct *owning_process  = NULL;
1219         struct mm_struct   *owning_mm       = NULL;
1220
1221         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1222         if (!owning_process)
1223                 return;
1224
1225         owning_mm = get_task_mm(owning_process);
1226         if (!owning_mm) {
1227                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1228                 while (1) {
1229                         put_task_struct(owning_process);
1230                         usleep_range(1000, 2000);
1231                         owning_process = get_pid_task(ibcontext->tgid,
1232                                                       PIDTYPE_PID);
1233                         if (!owning_process ||
1234                             owning_process->state == TASK_DEAD) {
1235                                 pr_info("disassociate ucontext done, task was terminated\n");
1236                                 /* in case task was dead need to release the
1237                                  * task struct.
1238                                  */
1239                                 if (owning_process)
1240                                         put_task_struct(owning_process);
1241                                 return;
1242                         }
1243                 }
1244         }
1245
1246         /* need to protect from a race on closing the vma as part of
1247          * mlx5_ib_vma_close.
1248          */
1249         down_read(&owning_mm->mmap_sem);
1250         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1251                                  list) {
1252                 vma = vma_private->vma;
1253                 ret = zap_vma_ptes(vma, vma->vm_start,
1254                                    PAGE_SIZE);
1255                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1256                 /* context going to be destroyed, should
1257                  * not access ops any more.
1258                  */
1259                 vma->vm_ops = NULL;
1260                 list_del(&vma_private->list);
1261                 kfree(vma_private);
1262         }
1263         up_read(&owning_mm->mmap_sem);
1264         mmput(owning_mm);
1265         put_task_struct(owning_process);
1266 }
1267
1268 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1269 {
1270         switch (cmd) {
1271         case MLX5_IB_MMAP_WC_PAGE:
1272                 return "WC";
1273         case MLX5_IB_MMAP_REGULAR_PAGE:
1274                 return "best effort WC";
1275         case MLX5_IB_MMAP_NC_PAGE:
1276                 return "NC";
1277         default:
1278                 return NULL;
1279         }
1280 }
1281
1282 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1283                     struct vm_area_struct *vma,
1284                     struct mlx5_ib_ucontext *context)
1285 {
1286         struct mlx5_uuar_info *uuari = &context->uuari;
1287         int err;
1288         unsigned long idx;
1289         phys_addr_t pfn, pa;
1290         pgprot_t prot;
1291
1292         switch (cmd) {
1293         case MLX5_IB_MMAP_WC_PAGE:
1294 /* Some architectures don't support WC memory */
1295 #if defined(CONFIG_X86)
1296                 if (!pat_enabled())
1297                         return -EPERM;
1298 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1299                         return -EPERM;
1300 #endif
1301         /* fall through */
1302         case MLX5_IB_MMAP_REGULAR_PAGE:
1303                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1304                 prot = pgprot_writecombine(vma->vm_page_prot);
1305                 break;
1306         case MLX5_IB_MMAP_NC_PAGE:
1307                 prot = pgprot_noncached(vma->vm_page_prot);
1308                 break;
1309         default:
1310                 return -EINVAL;
1311         }
1312
1313         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1314                 return -EINVAL;
1315
1316         idx = get_index(vma->vm_pgoff);
1317         if (idx >= uuari->num_uars)
1318                 return -EINVAL;
1319
1320         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1321         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1322
1323         vma->vm_page_prot = prot;
1324         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1325                                  PAGE_SIZE, vma->vm_page_prot);
1326         if (err) {
1327                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1328                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1329                 return -EAGAIN;
1330         }
1331
1332         pa = pfn << PAGE_SHIFT;
1333         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1334                     vma->vm_start, &pa);
1335
1336         return mlx5_ib_set_vma_data(vma, context);
1337 }
1338
1339 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1340 {
1341         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1342         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1343         unsigned long command;
1344         phys_addr_t pfn;
1345
1346         command = get_command(vma->vm_pgoff);
1347         switch (command) {
1348         case MLX5_IB_MMAP_WC_PAGE:
1349         case MLX5_IB_MMAP_NC_PAGE:
1350         case MLX5_IB_MMAP_REGULAR_PAGE:
1351                 return uar_mmap(dev, command, vma, context);
1352
1353         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1354                 return -ENOSYS;
1355
1356         case MLX5_IB_MMAP_CORE_CLOCK:
1357                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1358                         return -EINVAL;
1359
1360                 if (vma->vm_flags & VM_WRITE)
1361                         return -EPERM;
1362
1363                 /* Don't expose to user-space information it shouldn't have */
1364                 if (PAGE_SIZE > 4096)
1365                         return -EOPNOTSUPP;
1366
1367                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1368                 pfn = (dev->mdev->iseg_base +
1369                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1370                         PAGE_SHIFT;
1371                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1372                                        PAGE_SIZE, vma->vm_page_prot))
1373                         return -EAGAIN;
1374
1375                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1376                             vma->vm_start,
1377                             (unsigned long long)pfn << PAGE_SHIFT);
1378                 break;
1379
1380         default:
1381                 return -EINVAL;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1388                                       struct ib_ucontext *context,
1389                                       struct ib_udata *udata)
1390 {
1391         struct mlx5_ib_alloc_pd_resp resp;
1392         struct mlx5_ib_pd *pd;
1393         int err;
1394
1395         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1396         if (!pd)
1397                 return ERR_PTR(-ENOMEM);
1398
1399         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1400         if (err) {
1401                 kfree(pd);
1402                 return ERR_PTR(err);
1403         }
1404
1405         if (context) {
1406                 resp.pdn = pd->pdn;
1407                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1408                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1409                         kfree(pd);
1410                         return ERR_PTR(-EFAULT);
1411                 }
1412         }
1413
1414         return &pd->ibpd;
1415 }
1416
1417 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1418 {
1419         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1420         struct mlx5_ib_pd *mpd = to_mpd(pd);
1421
1422         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1423         kfree(mpd);
1424
1425         return 0;
1426 }
1427
1428 static bool outer_header_zero(u32 *match_criteria)
1429 {
1430         int size = MLX5_ST_SZ_BYTES(fte_match_param);
1431         char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1432                                              outer_headers);
1433
1434         return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1435                                                   outer_headers_c + 1,
1436                                                   size - 1);
1437 }
1438
1439 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1440                            union ib_flow_spec *ib_spec)
1441 {
1442         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1443                                              outer_headers);
1444         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1445                                              outer_headers);
1446         switch (ib_spec->type) {
1447         case IB_FLOW_SPEC_ETH:
1448                 if (ib_spec->size != sizeof(ib_spec->eth))
1449                         return -EINVAL;
1450
1451                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1452                                              dmac_47_16),
1453                                 ib_spec->eth.mask.dst_mac);
1454                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1455                                              dmac_47_16),
1456                                 ib_spec->eth.val.dst_mac);
1457
1458                 if (ib_spec->eth.mask.vlan_tag) {
1459                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1460                                  vlan_tag, 1);
1461                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1462                                  vlan_tag, 1);
1463
1464                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1465                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1466                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1467                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1468
1469                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1470                                  first_cfi,
1471                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1472                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1473                                  first_cfi,
1474                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1475
1476                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1477                                  first_prio,
1478                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1479                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1480                                  first_prio,
1481                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1482                 }
1483                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1484                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1485                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1486                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1487                 break;
1488         case IB_FLOW_SPEC_IPV4:
1489                 if (ib_spec->size != sizeof(ib_spec->ipv4))
1490                         return -EINVAL;
1491
1492                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1493                          ethertype, 0xffff);
1494                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1495                          ethertype, ETH_P_IP);
1496
1497                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1498                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1499                        &ib_spec->ipv4.mask.src_ip,
1500                        sizeof(ib_spec->ipv4.mask.src_ip));
1501                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1502                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1503                        &ib_spec->ipv4.val.src_ip,
1504                        sizeof(ib_spec->ipv4.val.src_ip));
1505                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1506                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1507                        &ib_spec->ipv4.mask.dst_ip,
1508                        sizeof(ib_spec->ipv4.mask.dst_ip));
1509                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1510                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1511                        &ib_spec->ipv4.val.dst_ip,
1512                        sizeof(ib_spec->ipv4.val.dst_ip));
1513                 break;
1514         case IB_FLOW_SPEC_IPV6:
1515                 if (ib_spec->size != sizeof(ib_spec->ipv6))
1516                         return -EINVAL;
1517
1518                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1519                          ethertype, 0xffff);
1520                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1521                          ethertype, ETH_P_IPV6);
1522
1523                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1524                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1525                        &ib_spec->ipv6.mask.src_ip,
1526                        sizeof(ib_spec->ipv6.mask.src_ip));
1527                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1528                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1529                        &ib_spec->ipv6.val.src_ip,
1530                        sizeof(ib_spec->ipv6.val.src_ip));
1531                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1532                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1533                        &ib_spec->ipv6.mask.dst_ip,
1534                        sizeof(ib_spec->ipv6.mask.dst_ip));
1535                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1536                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1537                        &ib_spec->ipv6.val.dst_ip,
1538                        sizeof(ib_spec->ipv6.val.dst_ip));
1539                 break;
1540         case IB_FLOW_SPEC_TCP:
1541                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1542                         return -EINVAL;
1543
1544                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1545                          0xff);
1546                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1547                          IPPROTO_TCP);
1548
1549                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1550                          ntohs(ib_spec->tcp_udp.mask.src_port));
1551                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1552                          ntohs(ib_spec->tcp_udp.val.src_port));
1553
1554                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1555                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1556                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1557                          ntohs(ib_spec->tcp_udp.val.dst_port));
1558                 break;
1559         case IB_FLOW_SPEC_UDP:
1560                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1561                         return -EINVAL;
1562
1563                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1564                          0xff);
1565                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1566                          IPPROTO_UDP);
1567
1568                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1569                          ntohs(ib_spec->tcp_udp.mask.src_port));
1570                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1571                          ntohs(ib_spec->tcp_udp.val.src_port));
1572
1573                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1574                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1575                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1576                          ntohs(ib_spec->tcp_udp.val.dst_port));
1577                 break;
1578         default:
1579                 return -EINVAL;
1580         }
1581
1582         return 0;
1583 }
1584
1585 /* If a flow could catch both multicast and unicast packets,
1586  * it won't fall into the multicast flow steering table and this rule
1587  * could steal other multicast packets.
1588  */
1589 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1590 {
1591         struct ib_flow_spec_eth *eth_spec;
1592
1593         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1594             ib_attr->size < sizeof(struct ib_flow_attr) +
1595             sizeof(struct ib_flow_spec_eth) ||
1596             ib_attr->num_of_specs < 1)
1597                 return false;
1598
1599         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1600         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1601             eth_spec->size != sizeof(*eth_spec))
1602                 return false;
1603
1604         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1605                is_multicast_ether_addr(eth_spec->val.dst_mac);
1606 }
1607
1608 static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1609 {
1610         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1611         bool has_ipv4_spec = false;
1612         bool eth_type_ipv4 = true;
1613         unsigned int spec_index;
1614
1615         /* Validate that ethertype is correct */
1616         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1617                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1618                     ib_spec->eth.mask.ether_type) {
1619                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1620                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1621                                 eth_type_ipv4 = false;
1622                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1623                         has_ipv4_spec = true;
1624                 }
1625                 ib_spec = (void *)ib_spec + ib_spec->size;
1626         }
1627         return !has_ipv4_spec || eth_type_ipv4;
1628 }
1629
1630 static void put_flow_table(struct mlx5_ib_dev *dev,
1631                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1632 {
1633         prio->refcount -= !!ft_added;
1634         if (!prio->refcount) {
1635                 mlx5_destroy_flow_table(prio->flow_table);
1636                 prio->flow_table = NULL;
1637         }
1638 }
1639
1640 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1641 {
1642         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1643         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1644                                                           struct mlx5_ib_flow_handler,
1645                                                           ibflow);
1646         struct mlx5_ib_flow_handler *iter, *tmp;
1647
1648         mutex_lock(&dev->flow_db.lock);
1649
1650         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1651                 mlx5_del_flow_rule(iter->rule);
1652                 list_del(&iter->list);
1653                 kfree(iter);
1654         }
1655
1656         mlx5_del_flow_rule(handler->rule);
1657         put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1658         mutex_unlock(&dev->flow_db.lock);
1659
1660         kfree(handler);
1661
1662         return 0;
1663 }
1664
1665 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1666 {
1667         priority *= 2;
1668         if (!dont_trap)
1669                 priority++;
1670         return priority;
1671 }
1672
1673 #define MLX5_FS_MAX_TYPES        10
1674 #define MLX5_FS_MAX_ENTRIES      32000UL
1675 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1676                                                 struct ib_flow_attr *flow_attr)
1677 {
1678         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1679         struct mlx5_flow_namespace *ns = NULL;
1680         struct mlx5_ib_flow_prio *prio;
1681         struct mlx5_flow_table *ft;
1682         int num_entries;
1683         int num_groups;
1684         int priority;
1685         int err = 0;
1686
1687         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1688                 if (flow_is_multicast_only(flow_attr) &&
1689                     !dont_trap)
1690                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1691                 else
1692                         priority = ib_prio_to_core_prio(flow_attr->priority,
1693                                                         dont_trap);
1694                 ns = mlx5_get_flow_namespace(dev->mdev,
1695                                              MLX5_FLOW_NAMESPACE_BYPASS);
1696                 num_entries = MLX5_FS_MAX_ENTRIES;
1697                 num_groups = MLX5_FS_MAX_TYPES;
1698                 prio = &dev->flow_db.prios[priority];
1699         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1700                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1701                 ns = mlx5_get_flow_namespace(dev->mdev,
1702                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1703                 build_leftovers_ft_param(&priority,
1704                                          &num_entries,
1705                                          &num_groups);
1706                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1707         }
1708
1709         if (!ns)
1710                 return ERR_PTR(-ENOTSUPP);
1711
1712         ft = prio->flow_table;
1713         if (!ft) {
1714                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1715                                                          num_entries,
1716                                                          num_groups,
1717                                                          0);
1718
1719                 if (!IS_ERR(ft)) {
1720                         prio->refcount = 0;
1721                         prio->flow_table = ft;
1722                 } else {
1723                         err = PTR_ERR(ft);
1724                 }
1725         }
1726
1727         return err ? ERR_PTR(err) : prio;
1728 }
1729
1730 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1731                                                      struct mlx5_ib_flow_prio *ft_prio,
1732                                                      struct ib_flow_attr *flow_attr,
1733                                                      struct mlx5_flow_destination *dst)
1734 {
1735         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1736         struct mlx5_ib_flow_handler *handler;
1737         struct mlx5_flow_spec *spec;
1738         void *ib_flow = flow_attr + 1;
1739         unsigned int spec_index;
1740         u32 action;
1741         int err = 0;
1742
1743         if (!is_valid_attr(flow_attr))
1744                 return ERR_PTR(-EINVAL);
1745
1746         spec = mlx5_vzalloc(sizeof(*spec));
1747         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1748         if (!handler || !spec) {
1749                 err = -ENOMEM;
1750                 goto free;
1751         }
1752
1753         INIT_LIST_HEAD(&handler->list);
1754
1755         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1756                 err = parse_flow_attr(spec->match_criteria,
1757                                       spec->match_value, ib_flow);
1758                 if (err < 0)
1759                         goto free;
1760
1761                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1762         }
1763
1764         /* Outer header support only */
1765         spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1766                 << 0;
1767         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1768                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1769         handler->rule = mlx5_add_flow_rule(ft, spec,
1770                                            action,
1771                                            MLX5_FS_DEFAULT_FLOW_TAG,
1772                                            dst);
1773
1774         if (IS_ERR(handler->rule)) {
1775                 err = PTR_ERR(handler->rule);
1776                 goto free;
1777         }
1778
1779         handler->prio = ft_prio - dev->flow_db.prios;
1780
1781         ft_prio->flow_table = ft;
1782 free:
1783         if (err)
1784                 kfree(handler);
1785         kvfree(spec);
1786         return err ? ERR_PTR(err) : handler;
1787 }
1788
1789 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1790                                                           struct mlx5_ib_flow_prio *ft_prio,
1791                                                           struct ib_flow_attr *flow_attr,
1792                                                           struct mlx5_flow_destination *dst)
1793 {
1794         struct mlx5_ib_flow_handler *handler_dst = NULL;
1795         struct mlx5_ib_flow_handler *handler = NULL;
1796
1797         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1798         if (!IS_ERR(handler)) {
1799                 handler_dst = create_flow_rule(dev, ft_prio,
1800                                                flow_attr, dst);
1801                 if (IS_ERR(handler_dst)) {
1802                         mlx5_del_flow_rule(handler->rule);
1803                         kfree(handler);
1804                         handler = handler_dst;
1805                 } else {
1806                         list_add(&handler_dst->list, &handler->list);
1807                 }
1808         }
1809
1810         return handler;
1811 }
1812 enum {
1813         LEFTOVERS_MC,
1814         LEFTOVERS_UC,
1815 };
1816
1817 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1818                                                           struct mlx5_ib_flow_prio *ft_prio,
1819                                                           struct ib_flow_attr *flow_attr,
1820                                                           struct mlx5_flow_destination *dst)
1821 {
1822         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1823         struct mlx5_ib_flow_handler *handler = NULL;
1824
1825         static struct {
1826                 struct ib_flow_attr     flow_attr;
1827                 struct ib_flow_spec_eth eth_flow;
1828         } leftovers_specs[] = {
1829                 [LEFTOVERS_MC] = {
1830                         .flow_attr = {
1831                                 .num_of_specs = 1,
1832                                 .size = sizeof(leftovers_specs[0])
1833                         },
1834                         .eth_flow = {
1835                                 .type = IB_FLOW_SPEC_ETH,
1836                                 .size = sizeof(struct ib_flow_spec_eth),
1837                                 .mask = {.dst_mac = {0x1} },
1838                                 .val =  {.dst_mac = {0x1} }
1839                         }
1840                 },
1841                 [LEFTOVERS_UC] = {
1842                         .flow_attr = {
1843                                 .num_of_specs = 1,
1844                                 .size = sizeof(leftovers_specs[0])
1845                         },
1846                         .eth_flow = {
1847                                 .type = IB_FLOW_SPEC_ETH,
1848                                 .size = sizeof(struct ib_flow_spec_eth),
1849                                 .mask = {.dst_mac = {0x1} },
1850                                 .val = {.dst_mac = {} }
1851                         }
1852                 }
1853         };
1854
1855         handler = create_flow_rule(dev, ft_prio,
1856                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1857                                    dst);
1858         if (!IS_ERR(handler) &&
1859             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1860                 handler_ucast = create_flow_rule(dev, ft_prio,
1861                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1862                                                  dst);
1863                 if (IS_ERR(handler_ucast)) {
1864                         kfree(handler);
1865                         handler = handler_ucast;
1866                 } else {
1867                         list_add(&handler_ucast->list, &handler->list);
1868                 }
1869         }
1870
1871         return handler;
1872 }
1873
1874 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1875                                            struct ib_flow_attr *flow_attr,
1876                                            int domain)
1877 {
1878         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1879         struct mlx5_ib_flow_handler *handler = NULL;
1880         struct mlx5_flow_destination *dst = NULL;
1881         struct mlx5_ib_flow_prio *ft_prio;
1882         int err;
1883
1884         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1885                 return ERR_PTR(-ENOSPC);
1886
1887         if (domain != IB_FLOW_DOMAIN_USER ||
1888             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1889             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
1890                 return ERR_PTR(-EINVAL);
1891
1892         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1893         if (!dst)
1894                 return ERR_PTR(-ENOMEM);
1895
1896         mutex_lock(&dev->flow_db.lock);
1897
1898         ft_prio = get_flow_table(dev, flow_attr);
1899         if (IS_ERR(ft_prio)) {
1900                 err = PTR_ERR(ft_prio);
1901                 goto unlock;
1902         }
1903
1904         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1905         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1906
1907         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1908                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
1909                         handler = create_dont_trap_rule(dev, ft_prio,
1910                                                         flow_attr, dst);
1911                 } else {
1912                         handler = create_flow_rule(dev, ft_prio, flow_attr,
1913                                                    dst);
1914                 }
1915         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1916                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1917                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1918                                                 dst);
1919         } else {
1920                 err = -EINVAL;
1921                 goto destroy_ft;
1922         }
1923
1924         if (IS_ERR(handler)) {
1925                 err = PTR_ERR(handler);
1926                 handler = NULL;
1927                 goto destroy_ft;
1928         }
1929
1930         ft_prio->refcount++;
1931         mutex_unlock(&dev->flow_db.lock);
1932         kfree(dst);
1933
1934         return &handler->ibflow;
1935
1936 destroy_ft:
1937         put_flow_table(dev, ft_prio, false);
1938 unlock:
1939         mutex_unlock(&dev->flow_db.lock);
1940         kfree(dst);
1941         kfree(handler);
1942         return ERR_PTR(err);
1943 }
1944
1945 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1946 {
1947         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1948         int err;
1949
1950         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1951         if (err)
1952                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1953                              ibqp->qp_num, gid->raw);
1954
1955         return err;
1956 }
1957
1958 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1959 {
1960         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1961         int err;
1962
1963         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1964         if (err)
1965                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1966                              ibqp->qp_num, gid->raw);
1967
1968         return err;
1969 }
1970
1971 static int init_node_data(struct mlx5_ib_dev *dev)
1972 {
1973         int err;
1974
1975         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1976         if (err)
1977                 return err;
1978
1979         dev->mdev->rev_id = dev->mdev->pdev->revision;
1980
1981         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1982 }
1983
1984 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1985                              char *buf)
1986 {
1987         struct mlx5_ib_dev *dev =
1988                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1989
1990         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1991 }
1992
1993 static ssize_t show_reg_pages(struct device *device,
1994                               struct device_attribute *attr, char *buf)
1995 {
1996         struct mlx5_ib_dev *dev =
1997                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1998
1999         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2000 }
2001
2002 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2003                         char *buf)
2004 {
2005         struct mlx5_ib_dev *dev =
2006                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2007         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2008 }
2009
2010 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2011                         char *buf)
2012 {
2013         struct mlx5_ib_dev *dev =
2014                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2015         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2016 }
2017
2018 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2019                           char *buf)
2020 {
2021         struct mlx5_ib_dev *dev =
2022                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2023         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2024                        dev->mdev->board_id);
2025 }
2026
2027 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2028 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2029 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2030 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2031 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2032
2033 static struct device_attribute *mlx5_class_attributes[] = {
2034         &dev_attr_hw_rev,
2035         &dev_attr_hca_type,
2036         &dev_attr_board_id,
2037         &dev_attr_fw_pages,
2038         &dev_attr_reg_pages,
2039 };
2040
2041 static void pkey_change_handler(struct work_struct *work)
2042 {
2043         struct mlx5_ib_port_resources *ports =
2044                 container_of(work, struct mlx5_ib_port_resources,
2045                              pkey_change_work);
2046
2047         mutex_lock(&ports->devr->mutex);
2048         mlx5_ib_gsi_pkey_change(ports->gsi);
2049         mutex_unlock(&ports->devr->mutex);
2050 }
2051
2052 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2053 {
2054         struct mlx5_ib_qp *mqp;
2055         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2056         struct mlx5_core_cq *mcq;
2057         struct list_head cq_armed_list;
2058         unsigned long flags_qp;
2059         unsigned long flags_cq;
2060         unsigned long flags;
2061
2062         INIT_LIST_HEAD(&cq_armed_list);
2063
2064         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2065         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2066         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2067                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2068                 if (mqp->sq.tail != mqp->sq.head) {
2069                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2070                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2071                         if (send_mcq->mcq.comp &&
2072                             mqp->ibqp.send_cq->comp_handler) {
2073                                 if (!send_mcq->mcq.reset_notify_added) {
2074                                         send_mcq->mcq.reset_notify_added = 1;
2075                                         list_add_tail(&send_mcq->mcq.reset_notify,
2076                                                       &cq_armed_list);
2077                                 }
2078                         }
2079                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2080                 }
2081                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2082                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2083                 /* no handling is needed for SRQ */
2084                 if (!mqp->ibqp.srq) {
2085                         if (mqp->rq.tail != mqp->rq.head) {
2086                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2087                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2088                                 if (recv_mcq->mcq.comp &&
2089                                     mqp->ibqp.recv_cq->comp_handler) {
2090                                         if (!recv_mcq->mcq.reset_notify_added) {
2091                                                 recv_mcq->mcq.reset_notify_added = 1;
2092                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2093                                                               &cq_armed_list);
2094                                         }
2095                                 }
2096                                 spin_unlock_irqrestore(&recv_mcq->lock,
2097                                                        flags_cq);
2098                         }
2099                 }
2100                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2101         }
2102         /*At that point all inflight post send were put to be executed as of we
2103          * lock/unlock above locks Now need to arm all involved CQs.
2104          */
2105         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2106                 mcq->comp(mcq);
2107         }
2108         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2109 }
2110
2111 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2112                           enum mlx5_dev_event event, unsigned long param)
2113 {
2114         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2115         struct ib_event ibev;
2116
2117         u8 port = 0;
2118
2119         switch (event) {
2120         case MLX5_DEV_EVENT_SYS_ERROR:
2121                 ibdev->ib_active = false;
2122                 ibev.event = IB_EVENT_DEVICE_FATAL;
2123                 mlx5_ib_handle_internal_error(ibdev);
2124                 break;
2125
2126         case MLX5_DEV_EVENT_PORT_UP:
2127                 ibev.event = IB_EVENT_PORT_ACTIVE;
2128                 port = (u8)param;
2129                 break;
2130
2131         case MLX5_DEV_EVENT_PORT_DOWN:
2132         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2133                 ibev.event = IB_EVENT_PORT_ERR;
2134                 port = (u8)param;
2135                 break;
2136
2137         case MLX5_DEV_EVENT_LID_CHANGE:
2138                 ibev.event = IB_EVENT_LID_CHANGE;
2139                 port = (u8)param;
2140                 break;
2141
2142         case MLX5_DEV_EVENT_PKEY_CHANGE:
2143                 ibev.event = IB_EVENT_PKEY_CHANGE;
2144                 port = (u8)param;
2145
2146                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2147                 break;
2148
2149         case MLX5_DEV_EVENT_GUID_CHANGE:
2150                 ibev.event = IB_EVENT_GID_CHANGE;
2151                 port = (u8)param;
2152                 break;
2153
2154         case MLX5_DEV_EVENT_CLIENT_REREG:
2155                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2156                 port = (u8)param;
2157                 break;
2158         }
2159
2160         ibev.device           = &ibdev->ib_dev;
2161         ibev.element.port_num = port;
2162
2163         if (port < 1 || port > ibdev->num_ports) {
2164                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2165                 return;
2166         }
2167
2168         if (ibdev->ib_active)
2169                 ib_dispatch_event(&ibev);
2170 }
2171
2172 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2173 {
2174         int port;
2175
2176         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2177                 mlx5_query_ext_port_caps(dev, port);
2178 }
2179
2180 static int get_port_caps(struct mlx5_ib_dev *dev)
2181 {
2182         struct ib_device_attr *dprops = NULL;
2183         struct ib_port_attr *pprops = NULL;
2184         int err = -ENOMEM;
2185         int port;
2186         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2187
2188         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2189         if (!pprops)
2190                 goto out;
2191
2192         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2193         if (!dprops)
2194                 goto out;
2195
2196         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2197         if (err) {
2198                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2199                 goto out;
2200         }
2201
2202         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2203                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2204                 if (err) {
2205                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2206                                      port, err);
2207                         break;
2208                 }
2209                 dev->mdev->port_caps[port - 1].pkey_table_len =
2210                                                 dprops->max_pkeys;
2211                 dev->mdev->port_caps[port - 1].gid_table_len =
2212                                                 pprops->gid_tbl_len;
2213                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2214                             dprops->max_pkeys, pprops->gid_tbl_len);
2215         }
2216
2217 out:
2218         kfree(pprops);
2219         kfree(dprops);
2220
2221         return err;
2222 }
2223
2224 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2225 {
2226         int err;
2227
2228         err = mlx5_mr_cache_cleanup(dev);
2229         if (err)
2230                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2231
2232         mlx5_ib_destroy_qp(dev->umrc.qp);
2233         ib_free_cq(dev->umrc.cq);
2234         ib_dealloc_pd(dev->umrc.pd);
2235 }
2236
2237 enum {
2238         MAX_UMR_WR = 128,
2239 };
2240
2241 static int create_umr_res(struct mlx5_ib_dev *dev)
2242 {
2243         struct ib_qp_init_attr *init_attr = NULL;
2244         struct ib_qp_attr *attr = NULL;
2245         struct ib_pd *pd;
2246         struct ib_cq *cq;
2247         struct ib_qp *qp;
2248         int ret;
2249
2250         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2251         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2252         if (!attr || !init_attr) {
2253                 ret = -ENOMEM;
2254                 goto error_0;
2255         }
2256
2257         pd = ib_alloc_pd(&dev->ib_dev, 0);
2258         if (IS_ERR(pd)) {
2259                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2260                 ret = PTR_ERR(pd);
2261                 goto error_0;
2262         }
2263
2264         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2265         if (IS_ERR(cq)) {
2266                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2267                 ret = PTR_ERR(cq);
2268                 goto error_2;
2269         }
2270
2271         init_attr->send_cq = cq;
2272         init_attr->recv_cq = cq;
2273         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2274         init_attr->cap.max_send_wr = MAX_UMR_WR;
2275         init_attr->cap.max_send_sge = 1;
2276         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2277         init_attr->port_num = 1;
2278         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2279         if (IS_ERR(qp)) {
2280                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2281                 ret = PTR_ERR(qp);
2282                 goto error_3;
2283         }
2284         qp->device     = &dev->ib_dev;
2285         qp->real_qp    = qp;
2286         qp->uobject    = NULL;
2287         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2288
2289         attr->qp_state = IB_QPS_INIT;
2290         attr->port_num = 1;
2291         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2292                                 IB_QP_PORT, NULL);
2293         if (ret) {
2294                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2295                 goto error_4;
2296         }
2297
2298         memset(attr, 0, sizeof(*attr));
2299         attr->qp_state = IB_QPS_RTR;
2300         attr->path_mtu = IB_MTU_256;
2301
2302         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2303         if (ret) {
2304                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2305                 goto error_4;
2306         }
2307
2308         memset(attr, 0, sizeof(*attr));
2309         attr->qp_state = IB_QPS_RTS;
2310         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2311         if (ret) {
2312                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2313                 goto error_4;
2314         }
2315
2316         dev->umrc.qp = qp;
2317         dev->umrc.cq = cq;
2318         dev->umrc.pd = pd;
2319
2320         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2321         ret = mlx5_mr_cache_init(dev);
2322         if (ret) {
2323                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2324                 goto error_4;
2325         }
2326
2327         kfree(attr);
2328         kfree(init_attr);
2329
2330         return 0;
2331
2332 error_4:
2333         mlx5_ib_destroy_qp(qp);
2334
2335 error_3:
2336         ib_free_cq(cq);
2337
2338 error_2:
2339         ib_dealloc_pd(pd);
2340
2341 error_0:
2342         kfree(attr);
2343         kfree(init_attr);
2344         return ret;
2345 }
2346
2347 static int create_dev_resources(struct mlx5_ib_resources *devr)
2348 {
2349         struct ib_srq_init_attr attr;
2350         struct mlx5_ib_dev *dev;
2351         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2352         int port;
2353         int ret = 0;
2354
2355         dev = container_of(devr, struct mlx5_ib_dev, devr);
2356
2357         mutex_init(&devr->mutex);
2358
2359         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2360         if (IS_ERR(devr->p0)) {
2361                 ret = PTR_ERR(devr->p0);
2362                 goto error0;
2363         }
2364         devr->p0->device  = &dev->ib_dev;
2365         devr->p0->uobject = NULL;
2366         atomic_set(&devr->p0->usecnt, 0);
2367
2368         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2369         if (IS_ERR(devr->c0)) {
2370                 ret = PTR_ERR(devr->c0);
2371                 goto error1;
2372         }
2373         devr->c0->device        = &dev->ib_dev;
2374         devr->c0->uobject       = NULL;
2375         devr->c0->comp_handler  = NULL;
2376         devr->c0->event_handler = NULL;
2377         devr->c0->cq_context    = NULL;
2378         atomic_set(&devr->c0->usecnt, 0);
2379
2380         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2381         if (IS_ERR(devr->x0)) {
2382                 ret = PTR_ERR(devr->x0);
2383                 goto error2;
2384         }
2385         devr->x0->device = &dev->ib_dev;
2386         devr->x0->inode = NULL;
2387         atomic_set(&devr->x0->usecnt, 0);
2388         mutex_init(&devr->x0->tgt_qp_mutex);
2389         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2390
2391         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2392         if (IS_ERR(devr->x1)) {
2393                 ret = PTR_ERR(devr->x1);
2394                 goto error3;
2395         }
2396         devr->x1->device = &dev->ib_dev;
2397         devr->x1->inode = NULL;
2398         atomic_set(&devr->x1->usecnt, 0);
2399         mutex_init(&devr->x1->tgt_qp_mutex);
2400         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2401
2402         memset(&attr, 0, sizeof(attr));
2403         attr.attr.max_sge = 1;
2404         attr.attr.max_wr = 1;
2405         attr.srq_type = IB_SRQT_XRC;
2406         attr.ext.xrc.cq = devr->c0;
2407         attr.ext.xrc.xrcd = devr->x0;
2408
2409         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2410         if (IS_ERR(devr->s0)) {
2411                 ret = PTR_ERR(devr->s0);
2412                 goto error4;
2413         }
2414         devr->s0->device        = &dev->ib_dev;
2415         devr->s0->pd            = devr->p0;
2416         devr->s0->uobject       = NULL;
2417         devr->s0->event_handler = NULL;
2418         devr->s0->srq_context   = NULL;
2419         devr->s0->srq_type      = IB_SRQT_XRC;
2420         devr->s0->ext.xrc.xrcd  = devr->x0;
2421         devr->s0->ext.xrc.cq    = devr->c0;
2422         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2423         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2424         atomic_inc(&devr->p0->usecnt);
2425         atomic_set(&devr->s0->usecnt, 0);
2426
2427         memset(&attr, 0, sizeof(attr));
2428         attr.attr.max_sge = 1;
2429         attr.attr.max_wr = 1;
2430         attr.srq_type = IB_SRQT_BASIC;
2431         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2432         if (IS_ERR(devr->s1)) {
2433                 ret = PTR_ERR(devr->s1);
2434                 goto error5;
2435         }
2436         devr->s1->device        = &dev->ib_dev;
2437         devr->s1->pd            = devr->p0;
2438         devr->s1->uobject       = NULL;
2439         devr->s1->event_handler = NULL;
2440         devr->s1->srq_context   = NULL;
2441         devr->s1->srq_type      = IB_SRQT_BASIC;
2442         devr->s1->ext.xrc.cq    = devr->c0;
2443         atomic_inc(&devr->p0->usecnt);
2444         atomic_set(&devr->s0->usecnt, 0);
2445
2446         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2447                 INIT_WORK(&devr->ports[port].pkey_change_work,
2448                           pkey_change_handler);
2449                 devr->ports[port].devr = devr;
2450         }
2451
2452         return 0;
2453
2454 error5:
2455         mlx5_ib_destroy_srq(devr->s0);
2456 error4:
2457         mlx5_ib_dealloc_xrcd(devr->x1);
2458 error3:
2459         mlx5_ib_dealloc_xrcd(devr->x0);
2460 error2:
2461         mlx5_ib_destroy_cq(devr->c0);
2462 error1:
2463         mlx5_ib_dealloc_pd(devr->p0);
2464 error0:
2465         return ret;
2466 }
2467
2468 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2469 {
2470         struct mlx5_ib_dev *dev =
2471                 container_of(devr, struct mlx5_ib_dev, devr);
2472         int port;
2473
2474         mlx5_ib_destroy_srq(devr->s1);
2475         mlx5_ib_destroy_srq(devr->s0);
2476         mlx5_ib_dealloc_xrcd(devr->x0);
2477         mlx5_ib_dealloc_xrcd(devr->x1);
2478         mlx5_ib_destroy_cq(devr->c0);
2479         mlx5_ib_dealloc_pd(devr->p0);
2480
2481         /* Make sure no change P_Key work items are still executing */
2482         for (port = 0; port < dev->num_ports; ++port)
2483                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2484 }
2485
2486 static u32 get_core_cap_flags(struct ib_device *ibdev)
2487 {
2488         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2489         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2490         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2491         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2492         u32 ret = 0;
2493
2494         if (ll == IB_LINK_LAYER_INFINIBAND)
2495                 return RDMA_CORE_PORT_IBA_IB;
2496
2497         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2498                 return 0;
2499
2500         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2501                 return 0;
2502
2503         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2504                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2505
2506         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2507                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2508
2509         return ret;
2510 }
2511
2512 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2513                                struct ib_port_immutable *immutable)
2514 {
2515         struct ib_port_attr attr;
2516         int err;
2517
2518         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2519         if (err)
2520                 return err;
2521
2522         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2523         immutable->gid_tbl_len = attr.gid_tbl_len;
2524         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2525         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2526
2527         return 0;
2528 }
2529
2530 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2531                            size_t str_len)
2532 {
2533         struct mlx5_ib_dev *dev =
2534                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2535         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2536                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2537 }
2538
2539 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2540 {
2541         int err;
2542
2543         dev->roce.nb.notifier_call = mlx5_netdev_event;
2544         err = register_netdevice_notifier(&dev->roce.nb);
2545         if (err)
2546                 return err;
2547
2548         err = mlx5_nic_vport_enable_roce(dev->mdev);
2549         if (err)
2550                 goto err_unregister_netdevice_notifier;
2551
2552         return 0;
2553
2554 err_unregister_netdevice_notifier:
2555         unregister_netdevice_notifier(&dev->roce.nb);
2556         return err;
2557 }
2558
2559 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2560 {
2561         mlx5_nic_vport_disable_roce(dev->mdev);
2562         unregister_netdevice_notifier(&dev->roce.nb);
2563 }
2564
2565 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2566 {
2567         unsigned int i;
2568
2569         for (i = 0; i < dev->num_ports; i++)
2570                 mlx5_core_dealloc_q_counter(dev->mdev,
2571                                             dev->port[i].q_cnt_id);
2572 }
2573
2574 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2575 {
2576         int i;
2577         int ret;
2578
2579         for (i = 0; i < dev->num_ports; i++) {
2580                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2581                                                 &dev->port[i].q_cnt_id);
2582                 if (ret) {
2583                         mlx5_ib_warn(dev,
2584                                      "couldn't allocate queue counter for port %d, err %d\n",
2585                                      i + 1, ret);
2586                         goto dealloc_counters;
2587                 }
2588         }
2589
2590         return 0;
2591
2592 dealloc_counters:
2593         while (--i >= 0)
2594                 mlx5_core_dealloc_q_counter(dev->mdev,
2595                                             dev->port[i].q_cnt_id);
2596
2597         return ret;
2598 }
2599
2600 static const char * const names[] = {
2601         "rx_write_requests",
2602         "rx_read_requests",
2603         "rx_atomic_requests",
2604         "out_of_buffer",
2605         "out_of_sequence",
2606         "duplicate_request",
2607         "rnr_nak_retry_err",
2608         "packet_seq_err",
2609         "implied_nak_seq_err",
2610         "local_ack_timeout_err",
2611 };
2612
2613 static const size_t stats_offsets[] = {
2614         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2615         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2616         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2617         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2618         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2619         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2620         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2621         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2622         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2623         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2624 };
2625
2626 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2627                                                     u8 port_num)
2628 {
2629         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2630
2631         /* We support only per port stats */
2632         if (port_num == 0)
2633                 return NULL;
2634
2635         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2636                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2637 }
2638
2639 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2640                                 struct rdma_hw_stats *stats,
2641                                 u8 port, int index)
2642 {
2643         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2644         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2645         void *out;
2646         __be32 val;
2647         int ret;
2648         int i;
2649
2650         if (!port || !stats)
2651                 return -ENOSYS;
2652
2653         out = mlx5_vzalloc(outlen);
2654         if (!out)
2655                 return -ENOMEM;
2656
2657         ret = mlx5_core_query_q_counter(dev->mdev,
2658                                         dev->port[port - 1].q_cnt_id, 0,
2659                                         out, outlen);
2660         if (ret)
2661                 goto free;
2662
2663         for (i = 0; i < ARRAY_SIZE(names); i++) {
2664                 val = *(__be32 *)(out + stats_offsets[i]);
2665                 stats->value[i] = (u64)be32_to_cpu(val);
2666         }
2667 free:
2668         kvfree(out);
2669         return ARRAY_SIZE(names);
2670 }
2671
2672 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2673 {
2674         struct mlx5_ib_dev *dev;
2675         enum rdma_link_layer ll;
2676         int port_type_cap;
2677         int err;
2678         int i;
2679
2680         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2681         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2682
2683         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2684                 return NULL;
2685
2686         printk_once(KERN_INFO "%s", mlx5_version);
2687
2688         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2689         if (!dev)
2690                 return NULL;
2691
2692         dev->mdev = mdev;
2693
2694         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2695                             GFP_KERNEL);
2696         if (!dev->port)
2697                 goto err_dealloc;
2698
2699         rwlock_init(&dev->roce.netdev_lock);
2700         err = get_port_caps(dev);
2701         if (err)
2702                 goto err_free_port;
2703
2704         if (mlx5_use_mad_ifc(dev))
2705                 get_ext_port_caps(dev);
2706
2707         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2708
2709         strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2710         dev->ib_dev.owner               = THIS_MODULE;
2711         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2712         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2713         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2714         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2715         dev->ib_dev.num_comp_vectors    =
2716                 dev->mdev->priv.eq_table.num_comp_vectors;
2717         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2718
2719         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2720         dev->ib_dev.uverbs_cmd_mask     =
2721                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2722                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2723                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2724                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2725                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2726                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2727                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2728                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2729                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2730                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2731                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2732                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2733                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2734                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2735                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2736                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2737                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2738                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2739                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2740                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2741                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2742                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2743                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2744                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2745         dev->ib_dev.uverbs_ex_cmd_mask =
2746                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2747                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2748                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2749
2750         dev->ib_dev.query_device        = mlx5_ib_query_device;
2751         dev->ib_dev.query_port          = mlx5_ib_query_port;
2752         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
2753         if (ll == IB_LINK_LAYER_ETHERNET)
2754                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
2755         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
2756         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
2757         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
2758         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
2759         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
2760         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
2761         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
2762         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
2763         dev->ib_dev.mmap                = mlx5_ib_mmap;
2764         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
2765         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
2766         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
2767         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
2768         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
2769         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
2770         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
2771         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
2772         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
2773         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
2774         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
2775         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
2776         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
2777         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
2778         dev->ib_dev.post_send           = mlx5_ib_post_send;
2779         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
2780         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
2781         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
2782         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
2783         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
2784         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
2785         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
2786         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
2787         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
2788         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
2789         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
2790         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
2791         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
2792         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
2793         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
2794         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
2795         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
2796         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
2797         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
2798         if (mlx5_core_is_pf(mdev)) {
2799                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
2800                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
2801                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
2802                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
2803         }
2804
2805         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2806
2807         mlx5_ib_internal_fill_odp_caps(dev);
2808
2809         if (MLX5_CAP_GEN(mdev, imaicl)) {
2810                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
2811                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
2812                 dev->ib_dev.uverbs_cmd_mask |=
2813                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
2814                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2815         }
2816
2817         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2818             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2819                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
2820                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
2821         }
2822
2823         if (MLX5_CAP_GEN(mdev, xrc)) {
2824                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2825                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2826                 dev->ib_dev.uverbs_cmd_mask |=
2827                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2828                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2829         }
2830
2831         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2832             IB_LINK_LAYER_ETHERNET) {
2833                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2834                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2835                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
2836                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
2837                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
2838                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2839                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
2840                 dev->ib_dev.uverbs_ex_cmd_mask |=
2841                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2842                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2843                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2844                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2845                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2846                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2847                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2848         }
2849         err = init_node_data(dev);
2850         if (err)
2851                 goto err_dealloc;
2852
2853         mutex_init(&dev->flow_db.lock);
2854         mutex_init(&dev->cap_mask_mutex);
2855         INIT_LIST_HEAD(&dev->qp_list);
2856         spin_lock_init(&dev->reset_flow_resource_lock);
2857
2858         if (ll == IB_LINK_LAYER_ETHERNET) {
2859                 err = mlx5_enable_roce(dev);
2860                 if (err)
2861                         goto err_dealloc;
2862         }
2863
2864         err = create_dev_resources(&dev->devr);
2865         if (err)
2866                 goto err_disable_roce;
2867
2868         err = mlx5_ib_odp_init_one(dev);
2869         if (err)
2870                 goto err_rsrc;
2871
2872         err = mlx5_ib_alloc_q_counters(dev);
2873         if (err)
2874                 goto err_odp;
2875
2876         err = ib_register_device(&dev->ib_dev, NULL);
2877         if (err)
2878                 goto err_q_cnt;
2879
2880         err = create_umr_res(dev);
2881         if (err)
2882                 goto err_dev;
2883
2884         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2885                 err = device_create_file(&dev->ib_dev.dev,
2886                                          mlx5_class_attributes[i]);
2887                 if (err)
2888                         goto err_umrc;
2889         }
2890
2891         dev->ib_active = true;
2892
2893         return dev;
2894
2895 err_umrc:
2896         destroy_umrc_res(dev);
2897
2898 err_dev:
2899         ib_unregister_device(&dev->ib_dev);
2900
2901 err_q_cnt:
2902         mlx5_ib_dealloc_q_counters(dev);
2903
2904 err_odp:
2905         mlx5_ib_odp_remove_one(dev);
2906
2907 err_rsrc:
2908         destroy_dev_resources(&dev->devr);
2909
2910 err_disable_roce:
2911         if (ll == IB_LINK_LAYER_ETHERNET)
2912                 mlx5_disable_roce(dev);
2913
2914 err_free_port:
2915         kfree(dev->port);
2916
2917 err_dealloc:
2918         ib_dealloc_device((struct ib_device *)dev);
2919
2920         return NULL;
2921 }
2922
2923 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
2924 {
2925         struct mlx5_ib_dev *dev = context;
2926         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
2927
2928         ib_unregister_device(&dev->ib_dev);
2929         mlx5_ib_dealloc_q_counters(dev);
2930         destroy_umrc_res(dev);
2931         mlx5_ib_odp_remove_one(dev);
2932         destroy_dev_resources(&dev->devr);
2933         if (ll == IB_LINK_LAYER_ETHERNET)
2934                 mlx5_disable_roce(dev);
2935         kfree(dev->port);
2936         ib_dealloc_device(&dev->ib_dev);
2937 }
2938
2939 static struct mlx5_interface mlx5_ib_interface = {
2940         .add            = mlx5_ib_add,
2941         .remove         = mlx5_ib_remove,
2942         .event          = mlx5_ib_event,
2943         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
2944 };
2945
2946 static int __init mlx5_ib_init(void)
2947 {
2948         int err;
2949
2950         if (deprecated_prof_sel != 2)
2951                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2952
2953         err = mlx5_ib_odp_init();
2954         if (err)
2955                 return err;
2956
2957         err = mlx5_register_interface(&mlx5_ib_interface);
2958         if (err)
2959                 goto clean_odp;
2960
2961         return err;
2962
2963 clean_odp:
2964         mlx5_ib_odp_cleanup();
2965         return err;
2966 }
2967
2968 static void __exit mlx5_ib_cleanup(void)
2969 {
2970         mlx5_unregister_interface(&mlx5_ib_interface);
2971         mlx5_ib_odp_cleanup();
2972 }
2973
2974 module_init(mlx5_ib_init);
2975 module_exit(mlx5_ib_cleanup);