drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <rdma/ib_user_verbs.h>
  46 #include <rdma/ib_addr.h>
  47 #include <rdma/ib_cache.h>
  48 #include <linux/mlx5/port.h>
  49 #include <linux/mlx5/vport.h>
  50 #include <rdma/ib_smi.h>
  51 #include <rdma/ib_umem.h>
  52 #include <linux/in.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/mlx5/fs.h>
  55 #include "user.h"
  56 #include "mlx5_ib.h"
  57
  58 #define DRIVER_NAME "mlx5_ib"
  59 #define DRIVER_VERSION "2.2-1"
  60 #define DRIVER_RELDATE  "Feb 2014"
  61
  62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_VERSION(DRIVER_VERSION);
  66
  67 static int deprecated_prof_sel = 2;
  68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int mlx5_netdev_event(struct notifier_block *this,
 102                              unsigned long event, void *ptr)
 103 {
 104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 106                                                  roce.nb);
 107
 108         if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
 109                 return NOTIFY_DONE;
 110
 111         write_lock(&ibdev->roce.netdev_lock);
 112         if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 113                 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
 114         write_unlock(&ibdev->roce.netdev_lock);
 115
 116         return NOTIFY_DONE;
 117 }
 118
 119 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 120                                              u8 port_num)
 121 {
 122         struct mlx5_ib_dev *ibdev = to_mdev(device);
 123         struct net_device *ndev;
 124
 125         /* Ensure ndev does not disappear before we invoke dev_hold()
 126          */
 127         read_lock(&ibdev->roce.netdev_lock);
 128         ndev = ibdev->roce.netdev;
 129         if (ndev)
 130                 dev_hold(ndev);
 131         read_unlock(&ibdev->roce.netdev_lock);
 132
 133         return ndev;
 134 }
 135
 136 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 137                                 struct ib_port_attr *props)
 138 {
 139         struct mlx5_ib_dev *dev = to_mdev(device);
 140         struct net_device *ndev;
 141         enum ib_mtu ndev_ib_mtu;
 142         u16 qkey_viol_cntr;
 143
 144         memset(props, 0, sizeof(*props));
 145
 146         props->port_cap_flags  |= IB_PORT_CM_SUP;
 147         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 148
 149         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 150                                                 roce_address_table_size);
 151         props->max_mtu          = IB_MTU_4096;
 152         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 153         props->pkey_tbl_len     = 1;
 154         props->state            = IB_PORT_DOWN;
 155         props->phys_state       = 3;
 156
 157         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 158         props->qkey_viol_cntr = qkey_viol_cntr;
 159
 160         ndev = mlx5_ib_get_netdev(device, port_num);
 161         if (!ndev)
 162                 return 0;
 163
 164         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 165                 props->state      = IB_PORT_ACTIVE;
 166                 props->phys_state = 5;
 167         }
 168
 169         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 170
 171         dev_put(ndev);
 172
 173         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 174
 175         props->active_width     = IB_WIDTH_4X;  /* TODO */
 176         props->active_speed     = IB_SPEED_QDR; /* TODO */
 177
 178         return 0;
 179 }
 180
 181 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 182                                      const struct ib_gid_attr *attr,
 183                                      void *mlx5_addr)
 184 {
 185 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 186         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 187                                                source_l3_address);
 188         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 189                                                source_mac_47_32);
 190
 191         if (!gid)
 192                 return;
 193
 194         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 195
 196         if (is_vlan_dev(attr->ndev)) {
 197                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 198                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 199         }
 200
 201         switch (attr->gid_type) {
 202         case IB_GID_TYPE_IB:
 203                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 204                 break;
 205         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 206                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 207                 break;
 208
 209         default:
 210                 WARN_ON(true);
 211         }
 212
 213         if (attr->gid_type != IB_GID_TYPE_IB) {
 214                 if (ipv6_addr_v4mapped((void *)gid))
 215                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 216                                     MLX5_ROCE_L3_TYPE_IPV4);
 217                 else
 218                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 219                                     MLX5_ROCE_L3_TYPE_IPV6);
 220         }
 221
 222         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 223             !ipv6_addr_v4mapped((void *)gid))
 224                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 225         else
 226                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 227 }
 228
 229 static int set_roce_addr(struct ib_device *device, u8 port_num,
 230                          unsigned int index,
 231                          const union ib_gid *gid,
 232                          const struct ib_gid_attr *attr)
 233 {
 234         struct mlx5_ib_dev *dev = to_mdev(device);
 235         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)];
 236         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
 237         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 238         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 239
 240         if (ll != IB_LINK_LAYER_ETHERNET)
 241                 return -EINVAL;
 242
 243         memset(in, 0, sizeof(in));
 244
 245         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 246
 247         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 248         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 249
 250         memset(out, 0, sizeof(out));
 251         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 252 }
 253
 254 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 255                            unsigned int index, const union ib_gid *gid,
 256                            const struct ib_gid_attr *attr,
 257                            __always_unused void **context)
 258 {
 259         return set_roce_addr(device, port_num, index, gid, attr);
 260 }
 261
 262 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 263                            unsigned int index, __always_unused void **context)
 264 {
 265         return set_roce_addr(device, port_num, index, NULL, NULL);
 266 }
 267
 268 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 269                                int index)
 270 {
 271         struct ib_gid_attr attr;
 272         union ib_gid gid;
 273
 274         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 275                 return 0;
 276
 277         if (!attr.ndev)
 278                 return 0;
 279
 280         dev_put(attr.ndev);
 281
 282         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 283                 return 0;
 284
 285         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 286 }
 287
 288 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 289 {
 290         return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 291 }
 292
 293 enum {
 294         MLX5_VPORT_ACCESS_METHOD_MAD,
 295         MLX5_VPORT_ACCESS_METHOD_HCA,
 296         MLX5_VPORT_ACCESS_METHOD_NIC,
 297 };
 298
 299 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 300 {
 301         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 302                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 303
 304         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 305             IB_LINK_LAYER_ETHERNET)
 306                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 307
 308         return MLX5_VPORT_ACCESS_METHOD_HCA;
 309 }
 310
 311 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 312                             struct ib_device_attr *props)
 313 {
 314         u8 tmp;
 315         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 316         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 317         u8 atomic_req_8B_endianness_mode =
 318                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 319
 320         /* Check if HW supports 8 bytes standard atomic operations and capable
 321          * of host endianness respond
 322          */
 323         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 324         if (((atomic_operations & tmp) == tmp) &&
 325             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 326             (atomic_req_8B_endianness_mode)) {
 327                 props->atomic_cap = IB_ATOMIC_HCA;
 328         } else {
 329                 props->atomic_cap = IB_ATOMIC_NONE;
 330         }
 331 }
 332
 333 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 334                                         __be64 *sys_image_guid)
 335 {
 336         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 337         struct mlx5_core_dev *mdev = dev->mdev;
 338         u64 tmp;
 339         int err;
 340
 341         switch (mlx5_get_vport_access_method(ibdev)) {
 342         case MLX5_VPORT_ACCESS_METHOD_MAD:
 343                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 344                                                             sys_image_guid);
 345
 346         case MLX5_VPORT_ACCESS_METHOD_HCA:
 347                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 348                 break;
 349
 350         case MLX5_VPORT_ACCESS_METHOD_NIC:
 351                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 352                 break;
 353
 354         default:
 355                 return -EINVAL;
 356         }
 357
 358         if (!err)
 359                 *sys_image_guid = cpu_to_be64(tmp);
 360
 361         return err;
 362
 363 }
 364
 365 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 366                                 u16 *max_pkeys)
 367 {
 368         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 369         struct mlx5_core_dev *mdev = dev->mdev;
 370
 371         switch (mlx5_get_vport_access_method(ibdev)) {
 372         case MLX5_VPORT_ACCESS_METHOD_MAD:
 373                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 374
 375         case MLX5_VPORT_ACCESS_METHOD_HCA:
 376         case MLX5_VPORT_ACCESS_METHOD_NIC:
 377                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 378                                                 pkey_table_size));
 379                 return 0;
 380
 381         default:
 382                 return -EINVAL;
 383         }
 384 }
 385
 386 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 387                                 u32 *vendor_id)
 388 {
 389         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 390
 391         switch (mlx5_get_vport_access_method(ibdev)) {
 392         case MLX5_VPORT_ACCESS_METHOD_MAD:
 393                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 394
 395         case MLX5_VPORT_ACCESS_METHOD_HCA:
 396         case MLX5_VPORT_ACCESS_METHOD_NIC:
 397                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 398
 399         default:
 400                 return -EINVAL;
 401         }
 402 }
 403
 404 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 405                                 __be64 *node_guid)
 406 {
 407         u64 tmp;
 408         int err;
 409
 410         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 411         case MLX5_VPORT_ACCESS_METHOD_MAD:
 412                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 413
 414         case MLX5_VPORT_ACCESS_METHOD_HCA:
 415                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 416                 break;
 417
 418         case MLX5_VPORT_ACCESS_METHOD_NIC:
 419                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 420                 break;
 421
 422         default:
 423                 return -EINVAL;
 424         }
 425
 426         if (!err)
 427                 *node_guid = cpu_to_be64(tmp);
 428
 429         return err;
 430 }
 431
 432 struct mlx5_reg_node_desc {
 433         u8      desc[64];
 434 };
 435
 436 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 437 {
 438         struct mlx5_reg_node_desc in;
 439
 440         if (mlx5_use_mad_ifc(dev))
 441                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 442
 443         memset(&in, 0, sizeof(in));
 444
 445         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 446                                     sizeof(struct mlx5_reg_node_desc),
 447                                     MLX5_REG_NODE_DESC, 0, 0);
 448 }
 449
 450 static int mlx5_ib_query_device(struct ib_device *ibdev,
 451                                 struct ib_device_attr *props,
 452                                 struct ib_udata *uhw)
 453 {
 454         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 455         struct mlx5_core_dev *mdev = dev->mdev;
 456         int err = -ENOMEM;
 457         int max_rq_sg;
 458         int max_sq_sg;
 459         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 460
 461         if (uhw->inlen || uhw->outlen)
 462                 return -EINVAL;
 463
 464         memset(props, 0, sizeof(*props));
 465         err = mlx5_query_system_image_guid(ibdev,
 466                                            &props->sys_image_guid);
 467         if (err)
 468                 return err;
 469
 470         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 471         if (err)
 472                 return err;
 473
 474         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 475         if (err)
 476                 return err;
 477
 478         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 479                 (fw_rev_min(dev->mdev) << 16) |
 480                 fw_rev_sub(dev->mdev);
 481         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 482                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 483                 IB_DEVICE_SYS_IMAGE_GUID                |
 484                 IB_DEVICE_RC_RNR_NAK_GEN;
 485
 486         if (MLX5_CAP_GEN(mdev, pkv))
 487                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 488         if (MLX5_CAP_GEN(mdev, qkv))
 489                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 490         if (MLX5_CAP_GEN(mdev, apm))
 491                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 492         if (MLX5_CAP_GEN(mdev, xrc))
 493                 props->device_cap_flags |= IB_DEVICE_XRC;
 494         if (MLX5_CAP_GEN(mdev, imaicl)) {
 495                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 496                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 497                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 498                 /* We support 'Gappy' memory registration too */
 499                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 500         }
 501         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 502         if (MLX5_CAP_GEN(mdev, sho)) {
 503                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 504                 /* At this stage no support for signature handover */
 505                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 506                                       IB_PROT_T10DIF_TYPE_2 |
 507                                       IB_PROT_T10DIF_TYPE_3;
 508                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 509                                        IB_GUARD_T10DIF_CSUM;
 510         }
 511         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 512                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 513
 514         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 515             (MLX5_CAP_ETH(dev->mdev, csum_cap)))
 516                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 517
 518         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 519                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 520                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 521         }
 522
 523         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 524             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 525                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 526
 527         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 528                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 529
 530         props->vendor_part_id      = mdev->pdev->device;
 531         props->hw_ver              = mdev->pdev->revision;
 532
 533         props->max_mr_size         = ~0ull;
 534         props->page_size_cap       = ~(min_page_size - 1);
 535         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 536         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 537         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 538                      sizeof(struct mlx5_wqe_data_seg);
 539         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 540                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 541                      sizeof(struct mlx5_wqe_data_seg);
 542         props->max_sge = min(max_rq_sg, max_sq_sg);
 543         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 544         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 545         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 546         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 547         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 548         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 549         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 550         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 551         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 552         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 553         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 554         props->max_srq_sge         = max_rq_sg - 1;
 555         props->max_fast_reg_page_list_len =
 556                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 557         get_atomic_caps(dev, props);
 558         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 559         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 560         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 561         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 562                                            props->max_mcast_grp;
 563         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 564         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 565         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 566
 567 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 568         if (MLX5_CAP_GEN(mdev, pg))
 569                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 570         props->odp_caps = dev->odp_caps;
 571 #endif
 572
 573         if (MLX5_CAP_GEN(mdev, cd))
 574                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 575
 576         if (!mlx5_core_is_pf(mdev))
 577                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 578
 579         return 0;
 580 }
 581
 582 enum mlx5_ib_width {
 583         MLX5_IB_WIDTH_1X        = 1 << 0,
 584         MLX5_IB_WIDTH_2X        = 1 << 1,
 585         MLX5_IB_WIDTH_4X        = 1 << 2,
 586         MLX5_IB_WIDTH_8X        = 1 << 3,
 587         MLX5_IB_WIDTH_12X       = 1 << 4
 588 };
 589
 590 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 591                                   u8 *ib_width)
 592 {
 593         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 594         int err = 0;
 595
 596         if (active_width & MLX5_IB_WIDTH_1X) {
 597                 *ib_width = IB_WIDTH_1X;
 598         } else if (active_width & MLX5_IB_WIDTH_2X) {
 599                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 600                             (int)active_width);
 601                 err = -EINVAL;
 602         } else if (active_width & MLX5_IB_WIDTH_4X) {
 603                 *ib_width = IB_WIDTH_4X;
 604         } else if (active_width & MLX5_IB_WIDTH_8X) {
 605                 *ib_width = IB_WIDTH_8X;
 606         } else if (active_width & MLX5_IB_WIDTH_12X) {
 607                 *ib_width = IB_WIDTH_12X;
 608         } else {
 609                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 610                             (int)active_width);
 611                 err = -EINVAL;
 612         }
 613
 614         return err;
 615 }
 616
 617 static int mlx5_mtu_to_ib_mtu(int mtu)
 618 {
 619         switch (mtu) {
 620         case 256: return 1;
 621         case 512: return 2;
 622         case 1024: return 3;
 623         case 2048: return 4;
 624         case 4096: return 5;
 625         default:
 626                 pr_warn("invalid mtu\n");
 627                 return -1;
 628         }
 629 }
 630
 631 enum ib_max_vl_num {
 632         __IB_MAX_VL_0           = 1,
 633         __IB_MAX_VL_0_1         = 2,
 634         __IB_MAX_VL_0_3         = 3,
 635         __IB_MAX_VL_0_7         = 4,
 636         __IB_MAX_VL_0_14        = 5,
 637 };
 638
 639 enum mlx5_vl_hw_cap {
 640         MLX5_VL_HW_0    = 1,
 641         MLX5_VL_HW_0_1  = 2,
 642         MLX5_VL_HW_0_2  = 3,
 643         MLX5_VL_HW_0_3  = 4,
 644         MLX5_VL_HW_0_4  = 5,
 645         MLX5_VL_HW_0_5  = 6,
 646         MLX5_VL_HW_0_6  = 7,
 647         MLX5_VL_HW_0_7  = 8,
 648         MLX5_VL_HW_0_14 = 15
 649 };
 650
 651 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 652                                 u8 *max_vl_num)
 653 {
 654         switch (vl_hw_cap) {
 655         case MLX5_VL_HW_0:
 656                 *max_vl_num = __IB_MAX_VL_0;
 657                 break;
 658         case MLX5_VL_HW_0_1:
 659                 *max_vl_num = __IB_MAX_VL_0_1;
 660                 break;
 661         case MLX5_VL_HW_0_3:
 662                 *max_vl_num = __IB_MAX_VL_0_3;
 663                 break;
 664         case MLX5_VL_HW_0_7:
 665                 *max_vl_num = __IB_MAX_VL_0_7;
 666                 break;
 667         case MLX5_VL_HW_0_14:
 668                 *max_vl_num = __IB_MAX_VL_0_14;
 669                 break;
 670
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         return 0;
 676 }
 677
 678 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 679                                struct ib_port_attr *props)
 680 {
 681         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 682         struct mlx5_core_dev *mdev = dev->mdev;
 683         struct mlx5_hca_vport_context *rep;
 684         u16 max_mtu;
 685         u16 oper_mtu;
 686         int err;
 687         u8 ib_link_width_oper;
 688         u8 vl_hw_cap;
 689
 690         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 691         if (!rep) {
 692                 err = -ENOMEM;
 693                 goto out;
 694         }
 695
 696         memset(props, 0, sizeof(*props));
 697
 698         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 699         if (err)
 700                 goto out;
 701
 702         props->lid              = rep->lid;
 703         props->lmc              = rep->lmc;
 704         props->sm_lid           = rep->sm_lid;
 705         props->sm_sl            = rep->sm_sl;
 706         props->state            = rep->vport_state;
 707         props->phys_state       = rep->port_physical_state;
 708         props->port_cap_flags   = rep->cap_mask1;
 709         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 710         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 711         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 712         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 713         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 714         props->subnet_timeout   = rep->subnet_timeout;
 715         props->init_type_reply  = rep->init_type_reply;
 716         props->grh_required     = rep->grh_required;
 717
 718         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 719         if (err)
 720                 goto out;
 721
 722         err = translate_active_width(ibdev, ib_link_width_oper,
 723                                      &props->active_width);
 724         if (err)
 725                 goto out;
 726         err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
 727                                          port);
 728         if (err)
 729                 goto out;
 730
 731         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 732
 733         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 734
 735         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 736
 737         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 738
 739         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 740         if (err)
 741                 goto out;
 742
 743         err = translate_max_vl_num(ibdev, vl_hw_cap,
 744                                    &props->max_vl_num);
 745 out:
 746         kfree(rep);
 747         return err;
 748 }
 749
 750 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 751                        struct ib_port_attr *props)
 752 {
 753         switch (mlx5_get_vport_access_method(ibdev)) {
 754         case MLX5_VPORT_ACCESS_METHOD_MAD:
 755                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 756
 757         case MLX5_VPORT_ACCESS_METHOD_HCA:
 758                 return mlx5_query_hca_port(ibdev, port, props);
 759
 760         case MLX5_VPORT_ACCESS_METHOD_NIC:
 761                 return mlx5_query_port_roce(ibdev, port, props);
 762
 763         default:
 764                 return -EINVAL;
 765         }
 766 }
 767
 768 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 769                              union ib_gid *gid)
 770 {
 771         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 772         struct mlx5_core_dev *mdev = dev->mdev;
 773
 774         switch (mlx5_get_vport_access_method(ibdev)) {
 775         case MLX5_VPORT_ACCESS_METHOD_MAD:
 776                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 777
 778         case MLX5_VPORT_ACCESS_METHOD_HCA:
 779                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 780
 781         default:
 782                 return -EINVAL;
 783         }
 784
 785 }
 786
 787 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 788                               u16 *pkey)
 789 {
 790         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 791         struct mlx5_core_dev *mdev = dev->mdev;
 792
 793         switch (mlx5_get_vport_access_method(ibdev)) {
 794         case MLX5_VPORT_ACCESS_METHOD_MAD:
 795                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 796
 797         case MLX5_VPORT_ACCESS_METHOD_HCA:
 798         case MLX5_VPORT_ACCESS_METHOD_NIC:
 799                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 800                                                  pkey);
 801         default:
 802                 return -EINVAL;
 803         }
 804 }
 805
 806 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 807                                  struct ib_device_modify *props)
 808 {
 809         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 810         struct mlx5_reg_node_desc in;
 811         struct mlx5_reg_node_desc out;
 812         int err;
 813
 814         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 815                 return -EOPNOTSUPP;
 816
 817         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 818                 return 0;
 819
 820         /*
 821          * If possible, pass node desc to FW, so it can generate
 822          * a 144 trap.  If cmd fails, just ignore.
 823          */
 824         memcpy(&in, props->node_desc, 64);
 825         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 826                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 827         if (err)
 828                 return err;
 829
 830         memcpy(ibdev->node_desc, props->node_desc, 64);
 831
 832         return err;
 833 }
 834
 835 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 836                                struct ib_port_modify *props)
 837 {
 838         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 839         struct ib_port_attr attr;
 840         u32 tmp;
 841         int err;
 842
 843         mutex_lock(&dev->cap_mask_mutex);
 844
 845         err = mlx5_ib_query_port(ibdev, port, &attr);
 846         if (err)
 847                 goto out;
 848
 849         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 850                 ~props->clr_port_cap_mask;
 851
 852         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 853
 854 out:
 855         mutex_unlock(&dev->cap_mask_mutex);
 856         return err;
 857 }
 858
 859 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 860                                                   struct ib_udata *udata)
 861 {
 862         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 863         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 864         struct mlx5_ib_alloc_ucontext_resp resp = {};
 865         struct mlx5_ib_ucontext *context;
 866         struct mlx5_uuar_info *uuari;
 867         struct mlx5_uar *uars;
 868         int gross_uuars;
 869         int num_uars;
 870         int ver;
 871         int uuarn;
 872         int err;
 873         int i;
 874         size_t reqlen;
 875         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 876                                      max_cqe_version);
 877
 878         if (!dev->ib_active)
 879                 return ERR_PTR(-EAGAIN);
 880
 881         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 882                 return ERR_PTR(-EINVAL);
 883
 884         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 885         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 886                 ver = 0;
 887         else if (reqlen >= min_req_v2)
 888                 ver = 2;
 889         else
 890                 return ERR_PTR(-EINVAL);
 891
 892         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 893         if (err)
 894                 return ERR_PTR(err);
 895
 896         if (req.flags)
 897                 return ERR_PTR(-EINVAL);
 898
 899         if (req.total_num_uuars > MLX5_MAX_UUARS)
 900                 return ERR_PTR(-ENOMEM);
 901
 902         if (req.total_num_uuars == 0)
 903                 return ERR_PTR(-EINVAL);
 904
 905         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 906                 return ERR_PTR(-EOPNOTSUPP);
 907
 908         if (reqlen > sizeof(req) &&
 909             !ib_is_udata_cleared(udata, sizeof(req),
 910                                  reqlen - sizeof(req)))
 911                 return ERR_PTR(-EOPNOTSUPP);
 912
 913         req.total_num_uuars = ALIGN(req.total_num_uuars,
 914                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
 915         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
 916                 return ERR_PTR(-EINVAL);
 917
 918         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
 919         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
 920         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
 921         resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
 922         resp.cache_line_size = L1_CACHE_BYTES;
 923         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
 924         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
 925         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 926         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
 927         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
 928         resp.cqe_version = min_t(__u8,
 929                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
 930                                  req.max_cqe_version);
 931         resp.response_length = min(offsetof(typeof(resp), response_length) +
 932                                    sizeof(resp.response_length), udata->outlen);
 933
 934         context = kzalloc(sizeof(*context), GFP_KERNEL);
 935         if (!context)
 936                 return ERR_PTR(-ENOMEM);
 937
 938         uuari = &context->uuari;
 939         mutex_init(&uuari->lock);
 940         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
 941         if (!uars) {
 942                 err = -ENOMEM;
 943                 goto out_ctx;
 944         }
 945
 946         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
 947                                 sizeof(*uuari->bitmap),
 948                                 GFP_KERNEL);
 949         if (!uuari->bitmap) {
 950                 err = -ENOMEM;
 951                 goto out_uar_ctx;
 952         }
 953         /*
 954          * clear all fast path uuars
 955          */
 956         for (i = 0; i < gross_uuars; i++) {
 957                 uuarn = i & 3;
 958                 if (uuarn == 2 || uuarn == 3)
 959                         set_bit(i, uuari->bitmap);
 960         }
 961
 962         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
 963         if (!uuari->count) {
 964                 err = -ENOMEM;
 965                 goto out_bitmap;
 966         }
 967
 968         for (i = 0; i < num_uars; i++) {
 969                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
 970                 if (err)
 971                         goto out_count;
 972         }
 973
 974 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 975         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
 976 #endif
 977
 978         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
 979                 err = mlx5_core_alloc_transport_domain(dev->mdev,
 980                                                        &context->tdn);
 981                 if (err)
 982                         goto out_uars;
 983         }
 984
 985         INIT_LIST_HEAD(&context->db_page_list);
 986         mutex_init(&context->db_page_mutex);
 987
 988         resp.tot_uuars = req.total_num_uuars;
 989         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
 990
 991         if (field_avail(typeof(resp), cqe_version, udata->outlen))
 992                 resp.response_length += sizeof(resp.cqe_version);
 993
 994         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
 995                 resp.comp_mask |=
 996                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
 997                 resp.hca_core_clock_offset =
 998                         offsetof(struct mlx5_init_seg, internal_timer_h) %
 999                         PAGE_SIZE;
1000                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1001                                         sizeof(resp.reserved2) +
1002                                         sizeof(resp.reserved3);
1003         }
1004
1005         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1006         if (err)
1007                 goto out_td;
1008
1009         uuari->ver = ver;
1010         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1011         uuari->uars = uars;
1012         uuari->num_uars = num_uars;
1013         context->cqe_version = resp.cqe_version;
1014
1015         return &context->ibucontext;
1016
1017 out_td:
1018         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1019                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1020
1021 out_uars:
1022         for (i--; i >= 0; i--)
1023                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1024 out_count:
1025         kfree(uuari->count);
1026
1027 out_bitmap:
1028         kfree(uuari->bitmap);
1029
1030 out_uar_ctx:
1031         kfree(uars);
1032
1033 out_ctx:
1034         kfree(context);
1035         return ERR_PTR(err);
1036 }
1037
1038 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1039 {
1040         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1041         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1042         struct mlx5_uuar_info *uuari = &context->uuari;
1043         int i;
1044
1045         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1046                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1047
1048         for (i = 0; i < uuari->num_uars; i++) {
1049                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1050                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1051         }
1052
1053         kfree(uuari->count);
1054         kfree(uuari->bitmap);
1055         kfree(uuari->uars);
1056         kfree(context);
1057
1058         return 0;
1059 }
1060
1061 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1062 {
1063         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1064 }
1065
1066 static int get_command(unsigned long offset)
1067 {
1068         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1069 }
1070
1071 static int get_arg(unsigned long offset)
1072 {
1073         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1074 }
1075
1076 static int get_index(unsigned long offset)
1077 {
1078         return get_arg(offset);
1079 }
1080
1081 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1082 {
1083         switch (cmd) {
1084         case MLX5_IB_MMAP_WC_PAGE:
1085                 return "WC";
1086         case MLX5_IB_MMAP_REGULAR_PAGE:
1087                 return "best effort WC";
1088         case MLX5_IB_MMAP_NC_PAGE:
1089                 return "NC";
1090         default:
1091                 return NULL;
1092         }
1093 }
1094
1095 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1096                     struct vm_area_struct *vma, struct mlx5_uuar_info *uuari)
1097 {
1098         int err;
1099         unsigned long idx;
1100         phys_addr_t pfn, pa;
1101         pgprot_t prot;
1102
1103         switch (cmd) {
1104         case MLX5_IB_MMAP_WC_PAGE:
1105 /* Some architectures don't support WC memory */
1106 #if defined(CONFIG_X86)
1107                 if (!pat_enabled())
1108                         return -EPERM;
1109 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1110                         return -EPERM;
1111 #endif
1112         /* fall through */
1113         case MLX5_IB_MMAP_REGULAR_PAGE:
1114                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1115                 prot = pgprot_writecombine(vma->vm_page_prot);
1116                 break;
1117         case MLX5_IB_MMAP_NC_PAGE:
1118                 prot = pgprot_noncached(vma->vm_page_prot);
1119                 break;
1120         default:
1121                 return -EINVAL;
1122         }
1123
1124         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1125                 return -EINVAL;
1126
1127         idx = get_index(vma->vm_pgoff);
1128         if (idx >= uuari->num_uars)
1129                 return -EINVAL;
1130
1131         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1132         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1133
1134         vma->vm_page_prot = prot;
1135         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1136                                  PAGE_SIZE, vma->vm_page_prot);
1137         if (err) {
1138                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1139                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1140                 return -EAGAIN;
1141         }
1142
1143         pa = pfn << PAGE_SHIFT;
1144         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1145                     vma->vm_start, &pa);
1146
1147         return 0;
1148 }
1149
1150 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1151 {
1152         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1153         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1154         struct mlx5_uuar_info *uuari = &context->uuari;
1155         unsigned long command;
1156         phys_addr_t pfn;
1157
1158         command = get_command(vma->vm_pgoff);
1159         switch (command) {
1160         case MLX5_IB_MMAP_WC_PAGE:
1161         case MLX5_IB_MMAP_NC_PAGE:
1162         case MLX5_IB_MMAP_REGULAR_PAGE:
1163                 return uar_mmap(dev, command, vma, uuari);
1164
1165         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1166                 return -ENOSYS;
1167
1168         case MLX5_IB_MMAP_CORE_CLOCK:
1169                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1170                         return -EINVAL;
1171
1172                 if (vma->vm_flags & VM_WRITE)
1173                         return -EPERM;
1174
1175                 /* Don't expose to user-space information it shouldn't have */
1176                 if (PAGE_SIZE > 4096)
1177                         return -EOPNOTSUPP;
1178
1179                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1180                 pfn = (dev->mdev->iseg_base +
1181                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1182                         PAGE_SHIFT;
1183                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1184                                        PAGE_SIZE, vma->vm_page_prot))
1185                         return -EAGAIN;
1186
1187                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1188                             vma->vm_start,
1189                             (unsigned long long)pfn << PAGE_SHIFT);
1190                 break;
1191
1192         default:
1193                 return -EINVAL;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1200                                       struct ib_ucontext *context,
1201                                       struct ib_udata *udata)
1202 {
1203         struct mlx5_ib_alloc_pd_resp resp;
1204         struct mlx5_ib_pd *pd;
1205         int err;
1206
1207         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1208         if (!pd)
1209                 return ERR_PTR(-ENOMEM);
1210
1211         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1212         if (err) {
1213                 kfree(pd);
1214                 return ERR_PTR(err);
1215         }
1216
1217         if (context) {
1218                 resp.pdn = pd->pdn;
1219                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1220                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1221                         kfree(pd);
1222                         return ERR_PTR(-EFAULT);
1223                 }
1224         }
1225
1226         return &pd->ibpd;
1227 }
1228
1229 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1230 {
1231         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1232         struct mlx5_ib_pd *mpd = to_mpd(pd);
1233
1234         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1235         kfree(mpd);
1236
1237         return 0;
1238 }
1239
1240 static bool outer_header_zero(u32 *match_criteria)
1241 {
1242         int size = MLX5_ST_SZ_BYTES(fte_match_param);
1243         char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1244                                              outer_headers);
1245
1246         return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1247                                                   outer_headers_c + 1,
1248                                                   size - 1);
1249 }
1250
1251 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1252                            union ib_flow_spec *ib_spec)
1253 {
1254         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1255                                              outer_headers);
1256         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1257                                              outer_headers);
1258         switch (ib_spec->type) {
1259         case IB_FLOW_SPEC_ETH:
1260                 if (ib_spec->size != sizeof(ib_spec->eth))
1261                         return -EINVAL;
1262
1263                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1264                                              dmac_47_16),
1265                                 ib_spec->eth.mask.dst_mac);
1266                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1267                                              dmac_47_16),
1268                                 ib_spec->eth.val.dst_mac);
1269
1270                 if (ib_spec->eth.mask.vlan_tag) {
1271                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1272                                  vlan_tag, 1);
1273                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1274                                  vlan_tag, 1);
1275
1276                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1277                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1278                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1279                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1280
1281                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1282                                  first_cfi,
1283                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1284                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1285                                  first_cfi,
1286                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1287
1288                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1289                                  first_prio,
1290                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1291                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1292                                  first_prio,
1293                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1294                 }
1295                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1296                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1297                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1298                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1299                 break;
1300         case IB_FLOW_SPEC_IPV4:
1301                 if (ib_spec->size != sizeof(ib_spec->ipv4))
1302                         return -EINVAL;
1303
1304                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1305                          ethertype, 0xffff);
1306                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1307                          ethertype, ETH_P_IP);
1308
1309                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1310                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1311                        &ib_spec->ipv4.mask.src_ip,
1312                        sizeof(ib_spec->ipv4.mask.src_ip));
1313                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1314                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1315                        &ib_spec->ipv4.val.src_ip,
1316                        sizeof(ib_spec->ipv4.val.src_ip));
1317                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1318                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1319                        &ib_spec->ipv4.mask.dst_ip,
1320                        sizeof(ib_spec->ipv4.mask.dst_ip));
1321                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1322                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1323                        &ib_spec->ipv4.val.dst_ip,
1324                        sizeof(ib_spec->ipv4.val.dst_ip));
1325                 break;
1326         case IB_FLOW_SPEC_TCP:
1327                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1328                         return -EINVAL;
1329
1330                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1331                          0xff);
1332                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1333                          IPPROTO_TCP);
1334
1335                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1336                          ntohs(ib_spec->tcp_udp.mask.src_port));
1337                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1338                          ntohs(ib_spec->tcp_udp.val.src_port));
1339
1340                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1341                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1342                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1343                          ntohs(ib_spec->tcp_udp.val.dst_port));
1344                 break;
1345         case IB_FLOW_SPEC_UDP:
1346                 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1347                         return -EINVAL;
1348
1349                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1350                          0xff);
1351                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1352                          IPPROTO_UDP);
1353
1354                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1355                          ntohs(ib_spec->tcp_udp.mask.src_port));
1356                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1357                          ntohs(ib_spec->tcp_udp.val.src_port));
1358
1359                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1360                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1361                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1362                          ntohs(ib_spec->tcp_udp.val.dst_port));
1363                 break;
1364         default:
1365                 return -EINVAL;
1366         }
1367
1368         return 0;
1369 }
1370
1371 /* If a flow could catch both multicast and unicast packets,
1372  * it won't fall into the multicast flow steering table and this rule
1373  * could steal other multicast packets.
1374  */
1375 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1376 {
1377         struct ib_flow_spec_eth *eth_spec;
1378
1379         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1380             ib_attr->size < sizeof(struct ib_flow_attr) +
1381             sizeof(struct ib_flow_spec_eth) ||
1382             ib_attr->num_of_specs < 1)
1383                 return false;
1384
1385         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1386         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1387             eth_spec->size != sizeof(*eth_spec))
1388                 return false;
1389
1390         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1391                is_multicast_ether_addr(eth_spec->val.dst_mac);
1392 }
1393
1394 static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1395 {
1396         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1397         bool has_ipv4_spec = false;
1398         bool eth_type_ipv4 = true;
1399         unsigned int spec_index;
1400
1401         /* Validate that ethertype is correct */
1402         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1403                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1404                     ib_spec->eth.mask.ether_type) {
1405                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1406                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1407                                 eth_type_ipv4 = false;
1408                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1409                         has_ipv4_spec = true;
1410                 }
1411                 ib_spec = (void *)ib_spec + ib_spec->size;
1412         }
1413         return !has_ipv4_spec || eth_type_ipv4;
1414 }
1415
1416 static void put_flow_table(struct mlx5_ib_dev *dev,
1417                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1418 {
1419         prio->refcount -= !!ft_added;
1420         if (!prio->refcount) {
1421                 mlx5_destroy_flow_table(prio->flow_table);
1422                 prio->flow_table = NULL;
1423         }
1424 }
1425
1426 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1427 {
1428         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1429         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1430                                                           struct mlx5_ib_flow_handler,
1431                                                           ibflow);
1432         struct mlx5_ib_flow_handler *iter, *tmp;
1433
1434         mutex_lock(&dev->flow_db.lock);
1435
1436         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1437                 mlx5_del_flow_rule(iter->rule);
1438                 list_del(&iter->list);
1439                 kfree(iter);
1440         }
1441
1442         mlx5_del_flow_rule(handler->rule);
1443         put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1444         mutex_unlock(&dev->flow_db.lock);
1445
1446         kfree(handler);
1447
1448         return 0;
1449 }
1450
1451 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1452 {
1453         priority *= 2;
1454         if (!dont_trap)
1455                 priority++;
1456         return priority;
1457 }
1458
1459 #define MLX5_FS_MAX_TYPES        10
1460 #define MLX5_FS_MAX_ENTRIES      32000UL
1461 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1462                                                 struct ib_flow_attr *flow_attr)
1463 {
1464         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1465         struct mlx5_flow_namespace *ns = NULL;
1466         struct mlx5_ib_flow_prio *prio;
1467         struct mlx5_flow_table *ft;
1468         int num_entries;
1469         int num_groups;
1470         int priority;
1471         int err = 0;
1472
1473         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1474                 if (flow_is_multicast_only(flow_attr) &&
1475                     !dont_trap)
1476                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1477                 else
1478                         priority = ib_prio_to_core_prio(flow_attr->priority,
1479                                                         dont_trap);
1480                 ns = mlx5_get_flow_namespace(dev->mdev,
1481                                              MLX5_FLOW_NAMESPACE_BYPASS);
1482                 num_entries = MLX5_FS_MAX_ENTRIES;
1483                 num_groups = MLX5_FS_MAX_TYPES;
1484                 prio = &dev->flow_db.prios[priority];
1485         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1486                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1487                 ns = mlx5_get_flow_namespace(dev->mdev,
1488                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1489                 build_leftovers_ft_param(&priority,
1490                                          &num_entries,
1491                                          &num_groups);
1492                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1493         }
1494
1495         if (!ns)
1496                 return ERR_PTR(-ENOTSUPP);
1497
1498         ft = prio->flow_table;
1499         if (!ft) {
1500                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1501                                                          num_entries,
1502                                                          num_groups,
1503                                                          0);
1504
1505                 if (!IS_ERR(ft)) {
1506                         prio->refcount = 0;
1507                         prio->flow_table = ft;
1508                 } else {
1509                         err = PTR_ERR(ft);
1510                 }
1511         }
1512
1513         return err ? ERR_PTR(err) : prio;
1514 }
1515
1516 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1517                                                      struct mlx5_ib_flow_prio *ft_prio,
1518                                                      struct ib_flow_attr *flow_attr,
1519                                                      struct mlx5_flow_destination *dst)
1520 {
1521         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1522         struct mlx5_ib_flow_handler *handler;
1523         void *ib_flow = flow_attr + 1;
1524         u8 match_criteria_enable = 0;
1525         unsigned int spec_index;
1526         u32 *match_c;
1527         u32 *match_v;
1528         u32 action;
1529         int err = 0;
1530
1531         if (!is_valid_attr(flow_attr))
1532                 return ERR_PTR(-EINVAL);
1533
1534         match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1535         match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1536         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1537         if (!handler || !match_c || !match_v) {
1538                 err = -ENOMEM;
1539                 goto free;
1540         }
1541
1542         INIT_LIST_HEAD(&handler->list);
1543
1544         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1545                 err = parse_flow_attr(match_c, match_v, ib_flow);
1546                 if (err < 0)
1547                         goto free;
1548
1549                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1550         }
1551
1552         /* Outer header support only */
1553         match_criteria_enable = (!outer_header_zero(match_c)) << 0;
1554         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1555                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1556         handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1557                                            match_c, match_v,
1558                                            action,
1559                                            MLX5_FS_DEFAULT_FLOW_TAG,
1560                                            dst);
1561
1562         if (IS_ERR(handler->rule)) {
1563                 err = PTR_ERR(handler->rule);
1564                 goto free;
1565         }
1566
1567         handler->prio = ft_prio - dev->flow_db.prios;
1568
1569         ft_prio->flow_table = ft;
1570 free:
1571         if (err)
1572                 kfree(handler);
1573         kfree(match_c);
1574         kfree(match_v);
1575         return err ? ERR_PTR(err) : handler;
1576 }
1577
1578 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1579                                                           struct mlx5_ib_flow_prio *ft_prio,
1580                                                           struct ib_flow_attr *flow_attr,
1581                                                           struct mlx5_flow_destination *dst)
1582 {
1583         struct mlx5_ib_flow_handler *handler_dst = NULL;
1584         struct mlx5_ib_flow_handler *handler = NULL;
1585
1586         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1587         if (!IS_ERR(handler)) {
1588                 handler_dst = create_flow_rule(dev, ft_prio,
1589                                                flow_attr, dst);
1590                 if (IS_ERR(handler_dst)) {
1591                         mlx5_del_flow_rule(handler->rule);
1592                         kfree(handler);
1593                         handler = handler_dst;
1594                 } else {
1595                         list_add(&handler_dst->list, &handler->list);
1596                 }
1597         }
1598
1599         return handler;
1600 }
1601 enum {
1602         LEFTOVERS_MC,
1603         LEFTOVERS_UC,
1604 };
1605
1606 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1607                                                           struct mlx5_ib_flow_prio *ft_prio,
1608                                                           struct ib_flow_attr *flow_attr,
1609                                                           struct mlx5_flow_destination *dst)
1610 {
1611         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1612         struct mlx5_ib_flow_handler *handler = NULL;
1613
1614         static struct {
1615                 struct ib_flow_attr     flow_attr;
1616                 struct ib_flow_spec_eth eth_flow;
1617         } leftovers_specs[] = {
1618                 [LEFTOVERS_MC] = {
1619                         .flow_attr = {
1620                                 .num_of_specs = 1,
1621                                 .size = sizeof(leftovers_specs[0])
1622                         },
1623                         .eth_flow = {
1624                                 .type = IB_FLOW_SPEC_ETH,
1625                                 .size = sizeof(struct ib_flow_spec_eth),
1626                                 .mask = {.dst_mac = {0x1} },
1627                                 .val =  {.dst_mac = {0x1} }
1628                         }
1629                 },
1630                 [LEFTOVERS_UC] = {
1631                         .flow_attr = {
1632                                 .num_of_specs = 1,
1633                                 .size = sizeof(leftovers_specs[0])
1634                         },
1635                         .eth_flow = {
1636                                 .type = IB_FLOW_SPEC_ETH,
1637                                 .size = sizeof(struct ib_flow_spec_eth),
1638                                 .mask = {.dst_mac = {0x1} },
1639                                 .val = {.dst_mac = {} }
1640                         }
1641                 }
1642         };
1643
1644         handler = create_flow_rule(dev, ft_prio,
1645                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1646                                    dst);
1647         if (!IS_ERR(handler) &&
1648             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1649                 handler_ucast = create_flow_rule(dev, ft_prio,
1650                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1651                                                  dst);
1652                 if (IS_ERR(handler_ucast)) {
1653                         kfree(handler);
1654                         handler = handler_ucast;
1655                 } else {
1656                         list_add(&handler_ucast->list, &handler->list);
1657                 }
1658         }
1659
1660         return handler;
1661 }
1662
1663 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1664                                            struct ib_flow_attr *flow_attr,
1665                                            int domain)
1666 {
1667         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1668         struct mlx5_ib_flow_handler *handler = NULL;
1669         struct mlx5_flow_destination *dst = NULL;
1670         struct mlx5_ib_flow_prio *ft_prio;
1671         int err;
1672
1673         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1674                 return ERR_PTR(-ENOSPC);
1675
1676         if (domain != IB_FLOW_DOMAIN_USER ||
1677             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1678             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
1679                 return ERR_PTR(-EINVAL);
1680
1681         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1682         if (!dst)
1683                 return ERR_PTR(-ENOMEM);
1684
1685         mutex_lock(&dev->flow_db.lock);
1686
1687         ft_prio = get_flow_table(dev, flow_attr);
1688         if (IS_ERR(ft_prio)) {
1689                 err = PTR_ERR(ft_prio);
1690                 goto unlock;
1691         }
1692
1693         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1694         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1695
1696         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1697                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
1698                         handler = create_dont_trap_rule(dev, ft_prio,
1699                                                         flow_attr, dst);
1700                 } else {
1701                         handler = create_flow_rule(dev, ft_prio, flow_attr,
1702                                                    dst);
1703                 }
1704         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1705                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1706                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1707                                                 dst);
1708         } else {
1709                 err = -EINVAL;
1710                 goto destroy_ft;
1711         }
1712
1713         if (IS_ERR(handler)) {
1714                 err = PTR_ERR(handler);
1715                 handler = NULL;
1716                 goto destroy_ft;
1717         }
1718
1719         ft_prio->refcount++;
1720         mutex_unlock(&dev->flow_db.lock);
1721         kfree(dst);
1722
1723         return &handler->ibflow;
1724
1725 destroy_ft:
1726         put_flow_table(dev, ft_prio, false);
1727 unlock:
1728         mutex_unlock(&dev->flow_db.lock);
1729         kfree(dst);
1730         kfree(handler);
1731         return ERR_PTR(err);
1732 }
1733
1734 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1735 {
1736         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1737         int err;
1738
1739         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1740         if (err)
1741                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1742                              ibqp->qp_num, gid->raw);
1743
1744         return err;
1745 }
1746
1747 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1748 {
1749         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1750         int err;
1751
1752         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1753         if (err)
1754                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1755                              ibqp->qp_num, gid->raw);
1756
1757         return err;
1758 }
1759
1760 static int init_node_data(struct mlx5_ib_dev *dev)
1761 {
1762         int err;
1763
1764         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1765         if (err)
1766                 return err;
1767
1768         dev->mdev->rev_id = dev->mdev->pdev->revision;
1769
1770         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1771 }
1772
1773 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1774                              char *buf)
1775 {
1776         struct mlx5_ib_dev *dev =
1777                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1778
1779         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1780 }
1781
1782 static ssize_t show_reg_pages(struct device *device,
1783                               struct device_attribute *attr, char *buf)
1784 {
1785         struct mlx5_ib_dev *dev =
1786                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1787
1788         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
1789 }
1790
1791 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1792                         char *buf)
1793 {
1794         struct mlx5_ib_dev *dev =
1795                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1796         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
1797 }
1798
1799 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1800                            char *buf)
1801 {
1802         struct mlx5_ib_dev *dev =
1803                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1804         return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1805                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
1806 }
1807
1808 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1809                         char *buf)
1810 {
1811         struct mlx5_ib_dev *dev =
1812                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1813         return sprintf(buf, "%x\n", dev->mdev->rev_id);
1814 }
1815
1816 static ssize_t show_board(struct device *device, struct device_attribute *attr,
1817                           char *buf)
1818 {
1819         struct mlx5_ib_dev *dev =
1820                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1821         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
1822                        dev->mdev->board_id);
1823 }
1824
1825 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
1826 static DEVICE_ATTR(fw_ver,   S_IRUGO, show_fw_ver, NULL);
1827 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
1828 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
1829 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1830 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1831
1832 static struct device_attribute *mlx5_class_attributes[] = {
1833         &dev_attr_hw_rev,
1834         &dev_attr_fw_ver,
1835         &dev_attr_hca_type,
1836         &dev_attr_board_id,
1837         &dev_attr_fw_pages,
1838         &dev_attr_reg_pages,
1839 };
1840
1841 static void pkey_change_handler(struct work_struct *work)
1842 {
1843         struct mlx5_ib_port_resources *ports =
1844                 container_of(work, struct mlx5_ib_port_resources,
1845                              pkey_change_work);
1846
1847         mutex_lock(&ports->devr->mutex);
1848         mlx5_ib_gsi_pkey_change(ports->gsi);
1849         mutex_unlock(&ports->devr->mutex);
1850 }
1851
1852 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
1853                           enum mlx5_dev_event event, unsigned long param)
1854 {
1855         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
1856         struct ib_event ibev;
1857
1858         u8 port = 0;
1859
1860         switch (event) {
1861         case MLX5_DEV_EVENT_SYS_ERROR:
1862                 ibdev->ib_active = false;
1863                 ibev.event = IB_EVENT_DEVICE_FATAL;
1864                 break;
1865
1866         case MLX5_DEV_EVENT_PORT_UP:
1867                 ibev.event = IB_EVENT_PORT_ACTIVE;
1868                 port = (u8)param;
1869                 break;
1870
1871         case MLX5_DEV_EVENT_PORT_DOWN:
1872         case MLX5_DEV_EVENT_PORT_INITIALIZED:
1873                 ibev.event = IB_EVENT_PORT_ERR;
1874                 port = (u8)param;
1875                 break;
1876
1877         case MLX5_DEV_EVENT_LID_CHANGE:
1878                 ibev.event = IB_EVENT_LID_CHANGE;
1879                 port = (u8)param;
1880                 break;
1881
1882         case MLX5_DEV_EVENT_PKEY_CHANGE:
1883                 ibev.event = IB_EVENT_PKEY_CHANGE;
1884                 port = (u8)param;
1885
1886                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
1887                 break;
1888
1889         case MLX5_DEV_EVENT_GUID_CHANGE:
1890                 ibev.event = IB_EVENT_GID_CHANGE;
1891                 port = (u8)param;
1892                 break;
1893
1894         case MLX5_DEV_EVENT_CLIENT_REREG:
1895                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1896                 port = (u8)param;
1897                 break;
1898         }
1899
1900         ibev.device           = &ibdev->ib_dev;
1901         ibev.element.port_num = port;
1902
1903         if (port < 1 || port > ibdev->num_ports) {
1904                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1905                 return;
1906         }
1907
1908         if (ibdev->ib_active)
1909                 ib_dispatch_event(&ibev);
1910 }
1911
1912 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1913 {
1914         int port;
1915
1916         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
1917                 mlx5_query_ext_port_caps(dev, port);
1918 }
1919
1920 static int get_port_caps(struct mlx5_ib_dev *dev)
1921 {
1922         struct ib_device_attr *dprops = NULL;
1923         struct ib_port_attr *pprops = NULL;
1924         int err = -ENOMEM;
1925         int port;
1926         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
1927
1928         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1929         if (!pprops)
1930                 goto out;
1931
1932         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1933         if (!dprops)
1934                 goto out;
1935
1936         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
1937         if (err) {
1938                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1939                 goto out;
1940         }
1941
1942         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
1943                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1944                 if (err) {
1945                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
1946                                      port, err);
1947                         break;
1948                 }
1949                 dev->mdev->port_caps[port - 1].pkey_table_len =
1950                                                 dprops->max_pkeys;
1951                 dev->mdev->port_caps[port - 1].gid_table_len =
1952                                                 pprops->gid_tbl_len;
1953                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1954                             dprops->max_pkeys, pprops->gid_tbl_len);
1955         }
1956
1957 out:
1958         kfree(pprops);
1959         kfree(dprops);
1960
1961         return err;
1962 }
1963
1964 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1965 {
1966         int err;
1967
1968         err = mlx5_mr_cache_cleanup(dev);
1969         if (err)
1970                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1971
1972         mlx5_ib_destroy_qp(dev->umrc.qp);
1973         ib_free_cq(dev->umrc.cq);
1974         ib_dealloc_pd(dev->umrc.pd);
1975 }
1976
1977 enum {
1978         MAX_UMR_WR = 128,
1979 };
1980
1981 static int create_umr_res(struct mlx5_ib_dev *dev)
1982 {
1983         struct ib_qp_init_attr *init_attr = NULL;
1984         struct ib_qp_attr *attr = NULL;
1985         struct ib_pd *pd;
1986         struct ib_cq *cq;
1987         struct ib_qp *qp;
1988         int ret;
1989
1990         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1991         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1992         if (!attr || !init_attr) {
1993                 ret = -ENOMEM;
1994                 goto error_0;
1995         }
1996
1997         pd = ib_alloc_pd(&dev->ib_dev);
1998         if (IS_ERR(pd)) {
1999                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2000                 ret = PTR_ERR(pd);
2001                 goto error_0;
2002         }
2003
2004         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2005         if (IS_ERR(cq)) {
2006                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2007                 ret = PTR_ERR(cq);
2008                 goto error_2;
2009         }
2010
2011         init_attr->send_cq = cq;
2012         init_attr->recv_cq = cq;
2013         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2014         init_attr->cap.max_send_wr = MAX_UMR_WR;
2015         init_attr->cap.max_send_sge = 1;
2016         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2017         init_attr->port_num = 1;
2018         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2019         if (IS_ERR(qp)) {
2020                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2021                 ret = PTR_ERR(qp);
2022                 goto error_3;
2023         }
2024         qp->device     = &dev->ib_dev;
2025         qp->real_qp    = qp;
2026         qp->uobject    = NULL;
2027         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2028
2029         attr->qp_state = IB_QPS_INIT;
2030         attr->port_num = 1;
2031         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2032                                 IB_QP_PORT, NULL);
2033         if (ret) {
2034                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2035                 goto error_4;
2036         }
2037
2038         memset(attr, 0, sizeof(*attr));
2039         attr->qp_state = IB_QPS_RTR;
2040         attr->path_mtu = IB_MTU_256;
2041
2042         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2043         if (ret) {
2044                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2045                 goto error_4;
2046         }
2047
2048         memset(attr, 0, sizeof(*attr));
2049         attr->qp_state = IB_QPS_RTS;
2050         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2051         if (ret) {
2052                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2053                 goto error_4;
2054         }
2055
2056         dev->umrc.qp = qp;
2057         dev->umrc.cq = cq;
2058         dev->umrc.pd = pd;
2059
2060         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2061         ret = mlx5_mr_cache_init(dev);
2062         if (ret) {
2063                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2064                 goto error_4;
2065         }
2066
2067         kfree(attr);
2068         kfree(init_attr);
2069
2070         return 0;
2071
2072 error_4:
2073         mlx5_ib_destroy_qp(qp);
2074
2075 error_3:
2076         ib_free_cq(cq);
2077
2078 error_2:
2079         ib_dealloc_pd(pd);
2080
2081 error_0:
2082         kfree(attr);
2083         kfree(init_attr);
2084         return ret;
2085 }
2086
2087 static int create_dev_resources(struct mlx5_ib_resources *devr)
2088 {
2089         struct ib_srq_init_attr attr;
2090         struct mlx5_ib_dev *dev;
2091         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2092         int port;
2093         int ret = 0;
2094
2095         dev = container_of(devr, struct mlx5_ib_dev, devr);
2096
2097         mutex_init(&devr->mutex);
2098
2099         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2100         if (IS_ERR(devr->p0)) {
2101                 ret = PTR_ERR(devr->p0);
2102                 goto error0;
2103         }
2104         devr->p0->device  = &dev->ib_dev;
2105         devr->p0->uobject = NULL;
2106         atomic_set(&devr->p0->usecnt, 0);
2107
2108         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2109         if (IS_ERR(devr->c0)) {
2110                 ret = PTR_ERR(devr->c0);
2111                 goto error1;
2112         }
2113         devr->c0->device        = &dev->ib_dev;
2114         devr->c0->uobject       = NULL;
2115         devr->c0->comp_handler  = NULL;
2116         devr->c0->event_handler = NULL;
2117         devr->c0->cq_context    = NULL;
2118         atomic_set(&devr->c0->usecnt, 0);
2119
2120         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2121         if (IS_ERR(devr->x0)) {
2122                 ret = PTR_ERR(devr->x0);
2123                 goto error2;
2124         }
2125         devr->x0->device = &dev->ib_dev;
2126         devr->x0->inode = NULL;
2127         atomic_set(&devr->x0->usecnt, 0);
2128         mutex_init(&devr->x0->tgt_qp_mutex);
2129         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2130
2131         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2132         if (IS_ERR(devr->x1)) {
2133                 ret = PTR_ERR(devr->x1);
2134                 goto error3;
2135         }
2136         devr->x1->device = &dev->ib_dev;
2137         devr->x1->inode = NULL;
2138         atomic_set(&devr->x1->usecnt, 0);
2139         mutex_init(&devr->x1->tgt_qp_mutex);
2140         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2141
2142         memset(&attr, 0, sizeof(attr));
2143         attr.attr.max_sge = 1;
2144         attr.attr.max_wr = 1;
2145         attr.srq_type = IB_SRQT_XRC;
2146         attr.ext.xrc.cq = devr->c0;
2147         attr.ext.xrc.xrcd = devr->x0;
2148
2149         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2150         if (IS_ERR(devr->s0)) {
2151                 ret = PTR_ERR(devr->s0);
2152                 goto error4;
2153         }
2154         devr->s0->device        = &dev->ib_dev;
2155         devr->s0->pd            = devr->p0;
2156         devr->s0->uobject       = NULL;
2157         devr->s0->event_handler = NULL;
2158         devr->s0->srq_context   = NULL;
2159         devr->s0->srq_type      = IB_SRQT_XRC;
2160         devr->s0->ext.xrc.xrcd  = devr->x0;
2161         devr->s0->ext.xrc.cq    = devr->c0;
2162         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2163         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2164         atomic_inc(&devr->p0->usecnt);
2165         atomic_set(&devr->s0->usecnt, 0);
2166
2167         memset(&attr, 0, sizeof(attr));
2168         attr.attr.max_sge = 1;
2169         attr.attr.max_wr = 1;
2170         attr.srq_type = IB_SRQT_BASIC;
2171         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2172         if (IS_ERR(devr->s1)) {
2173                 ret = PTR_ERR(devr->s1);
2174                 goto error5;
2175         }
2176         devr->s1->device        = &dev->ib_dev;
2177         devr->s1->pd            = devr->p0;
2178         devr->s1->uobject       = NULL;
2179         devr->s1->event_handler = NULL;
2180         devr->s1->srq_context   = NULL;
2181         devr->s1->srq_type      = IB_SRQT_BASIC;
2182         devr->s1->ext.xrc.cq    = devr->c0;
2183         atomic_inc(&devr->p0->usecnt);
2184         atomic_set(&devr->s0->usecnt, 0);
2185
2186         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2187                 INIT_WORK(&devr->ports[port].pkey_change_work,
2188                           pkey_change_handler);
2189                 devr->ports[port].devr = devr;
2190         }
2191
2192         return 0;
2193
2194 error5:
2195         mlx5_ib_destroy_srq(devr->s0);
2196 error4:
2197         mlx5_ib_dealloc_xrcd(devr->x1);
2198 error3:
2199         mlx5_ib_dealloc_xrcd(devr->x0);
2200 error2:
2201         mlx5_ib_destroy_cq(devr->c0);
2202 error1:
2203         mlx5_ib_dealloc_pd(devr->p0);
2204 error0:
2205         return ret;
2206 }
2207
2208 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2209 {
2210         struct mlx5_ib_dev *dev =
2211                 container_of(devr, struct mlx5_ib_dev, devr);
2212         int port;
2213
2214         mlx5_ib_destroy_srq(devr->s1);
2215         mlx5_ib_destroy_srq(devr->s0);
2216         mlx5_ib_dealloc_xrcd(devr->x0);
2217         mlx5_ib_dealloc_xrcd(devr->x1);
2218         mlx5_ib_destroy_cq(devr->c0);
2219         mlx5_ib_dealloc_pd(devr->p0);
2220
2221         /* Make sure no change P_Key work items are still executing */
2222         for (port = 0; port < dev->num_ports; ++port)
2223                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2224 }
2225
2226 static u32 get_core_cap_flags(struct ib_device *ibdev)
2227 {
2228         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2229         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2230         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2231         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2232         u32 ret = 0;
2233
2234         if (ll == IB_LINK_LAYER_INFINIBAND)
2235                 return RDMA_CORE_PORT_IBA_IB;
2236
2237         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2238                 return 0;
2239
2240         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2241                 return 0;
2242
2243         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2244                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2245
2246         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2247                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2248
2249         return ret;
2250 }
2251
2252 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2253                                struct ib_port_immutable *immutable)
2254 {
2255         struct ib_port_attr attr;
2256         int err;
2257
2258         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2259         if (err)
2260                 return err;
2261
2262         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2263         immutable->gid_tbl_len = attr.gid_tbl_len;
2264         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2265         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2266
2267         return 0;
2268 }
2269
2270 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2271 {
2272         int err;
2273
2274         dev->roce.nb.notifier_call = mlx5_netdev_event;
2275         err = register_netdevice_notifier(&dev->roce.nb);
2276         if (err)
2277                 return err;
2278
2279         err = mlx5_nic_vport_enable_roce(dev->mdev);
2280         if (err)
2281                 goto err_unregister_netdevice_notifier;
2282
2283         return 0;
2284
2285 err_unregister_netdevice_notifier:
2286         unregister_netdevice_notifier(&dev->roce.nb);
2287         return err;
2288 }
2289
2290 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2291 {
2292         mlx5_nic_vport_disable_roce(dev->mdev);
2293         unregister_netdevice_notifier(&dev->roce.nb);
2294 }
2295
2296 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2297 {
2298         struct mlx5_ib_dev *dev;
2299         enum rdma_link_layer ll;
2300         int port_type_cap;
2301         int err;
2302         int i;
2303
2304         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2305         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2306
2307         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2308                 return NULL;
2309
2310         printk_once(KERN_INFO "%s", mlx5_version);
2311
2312         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2313         if (!dev)
2314                 return NULL;
2315
2316         dev->mdev = mdev;
2317
2318         rwlock_init(&dev->roce.netdev_lock);
2319         err = get_port_caps(dev);
2320         if (err)
2321                 goto err_dealloc;
2322
2323         if (mlx5_use_mad_ifc(dev))
2324                 get_ext_port_caps(dev);
2325
2326         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2327
2328         strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2329         dev->ib_dev.owner               = THIS_MODULE;
2330         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2331         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2332         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2333         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2334         dev->ib_dev.num_comp_vectors    =
2335                 dev->mdev->priv.eq_table.num_comp_vectors;
2336         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2337
2338         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2339         dev->ib_dev.uverbs_cmd_mask     =
2340                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2341                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2342                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2343                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2344                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2345                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2346                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2347                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2348                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2349                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2350                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2351                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2352                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2353                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2354                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2355                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2356                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2357                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2358                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2359                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2360                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2361                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2362                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2363                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2364         dev->ib_dev.uverbs_ex_cmd_mask =
2365                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2366                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2367                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2368
2369         dev->ib_dev.query_device        = mlx5_ib_query_device;
2370         dev->ib_dev.query_port          = mlx5_ib_query_port;
2371         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
2372         if (ll == IB_LINK_LAYER_ETHERNET)
2373                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
2374         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
2375         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
2376         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
2377         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
2378         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
2379         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
2380         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
2381         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
2382         dev->ib_dev.mmap                = mlx5_ib_mmap;
2383         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
2384         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
2385         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
2386         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
2387         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
2388         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
2389         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
2390         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
2391         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
2392         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
2393         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
2394         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
2395         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
2396         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
2397         dev->ib_dev.post_send           = mlx5_ib_post_send;
2398         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
2399         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
2400         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
2401         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
2402         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
2403         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
2404         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
2405         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
2406         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
2407         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
2408         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
2409         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
2410         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
2411         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
2412         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
2413         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
2414         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
2415         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
2416         if (mlx5_core_is_pf(mdev)) {
2417                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
2418                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
2419                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
2420                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
2421         }
2422
2423         mlx5_ib_internal_fill_odp_caps(dev);
2424
2425         if (MLX5_CAP_GEN(mdev, imaicl)) {
2426                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
2427                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
2428                 dev->ib_dev.uverbs_cmd_mask |=
2429                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
2430                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2431         }
2432
2433         if (MLX5_CAP_GEN(mdev, xrc)) {
2434                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2435                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2436                 dev->ib_dev.uverbs_cmd_mask |=
2437                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2438                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2439         }
2440
2441         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2442             IB_LINK_LAYER_ETHERNET) {
2443                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2444                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2445                 dev->ib_dev.uverbs_ex_cmd_mask |=
2446                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2447                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2448         }
2449         err = init_node_data(dev);
2450         if (err)
2451                 goto err_dealloc;
2452
2453         mutex_init(&dev->flow_db.lock);
2454         mutex_init(&dev->cap_mask_mutex);
2455
2456         if (ll == IB_LINK_LAYER_ETHERNET) {
2457                 err = mlx5_enable_roce(dev);
2458                 if (err)
2459                         goto err_dealloc;
2460         }
2461
2462         err = create_dev_resources(&dev->devr);
2463         if (err)
2464                 goto err_disable_roce;
2465
2466         err = mlx5_ib_odp_init_one(dev);
2467         if (err)
2468                 goto err_rsrc;
2469
2470         err = ib_register_device(&dev->ib_dev, NULL);
2471         if (err)
2472                 goto err_odp;
2473
2474         err = create_umr_res(dev);
2475         if (err)
2476                 goto err_dev;
2477
2478         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2479                 err = device_create_file(&dev->ib_dev.dev,
2480                                          mlx5_class_attributes[i]);
2481                 if (err)
2482                         goto err_umrc;
2483         }
2484
2485         dev->ib_active = true;
2486
2487         return dev;
2488
2489 err_umrc:
2490         destroy_umrc_res(dev);
2491
2492 err_dev:
2493         ib_unregister_device(&dev->ib_dev);
2494
2495 err_odp:
2496         mlx5_ib_odp_remove_one(dev);
2497
2498 err_rsrc:
2499         destroy_dev_resources(&dev->devr);
2500
2501 err_disable_roce:
2502         if (ll == IB_LINK_LAYER_ETHERNET)
2503                 mlx5_disable_roce(dev);
2504
2505 err_dealloc:
2506         ib_dealloc_device((struct ib_device *)dev);
2507
2508         return NULL;
2509 }
2510
2511 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
2512 {
2513         struct mlx5_ib_dev *dev = context;
2514         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
2515
2516         ib_unregister_device(&dev->ib_dev);
2517         destroy_umrc_res(dev);
2518         mlx5_ib_odp_remove_one(dev);
2519         destroy_dev_resources(&dev->devr);
2520         if (ll == IB_LINK_LAYER_ETHERNET)
2521                 mlx5_disable_roce(dev);
2522         ib_dealloc_device(&dev->ib_dev);
2523 }
2524
2525 static struct mlx5_interface mlx5_ib_interface = {
2526         .add            = mlx5_ib_add,
2527         .remove         = mlx5_ib_remove,
2528         .event          = mlx5_ib_event,
2529         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
2530 };
2531
2532 static int __init mlx5_ib_init(void)
2533 {
2534         int err;
2535
2536         if (deprecated_prof_sel != 2)
2537                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2538
2539         err = mlx5_ib_odp_init();
2540         if (err)
2541                 return err;
2542
2543         err = mlx5_register_interface(&mlx5_ib_interface);
2544         if (err)
2545                 goto clean_odp;
2546
2547         return err;
2548
2549 clean_odp:
2550         mlx5_ib_odp_cleanup();
2551         return err;
2552 }
2553
2554 static void __exit mlx5_ib_cleanup(void)
2555 {
2556         mlx5_unregister_interface(&mlx5_ib_interface);
2557         mlx5_ib_odp_cleanup();
2558 }
2559
2560 module_init(mlx5_ib_init);
2561 module_exit(mlx5_ib_cleanup);