drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_addr.h>
  48 #include <rdma/ib_cache.h>
  49 #include <linux/mlx5/port.h>
  50 #include <linux/mlx5/vport.h>
  51 #include <linux/list.h>
  52 #include <rdma/ib_smi.h>
  53 #include <rdma/ib_umem.h>
  54 #include <linux/in.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/mlx5/fs.h>
  57 #include "mlx5_ib.h"
  58
  59 #define DRIVER_NAME "mlx5_ib"
  60 #define DRIVER_VERSION "2.2-1"
  61 #define DRIVER_RELDATE  "Feb 2014"
  62
  63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  65 MODULE_LICENSE("Dual BSD/GPL");
  66 MODULE_VERSION(DRIVER_VERSION);
  67
  68 static int deprecated_prof_sel = 2;
  69 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  70 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  71
  72 static char mlx5_version[] =
  73         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  74         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  75
  76 enum {
  77         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  78 };
  79
  80 static enum rdma_link_layer
  81 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  82 {
  83         switch (port_type_cap) {
  84         case MLX5_CAP_PORT_TYPE_IB:
  85                 return IB_LINK_LAYER_INFINIBAND;
  86         case MLX5_CAP_PORT_TYPE_ETH:
  87                 return IB_LINK_LAYER_ETHERNET;
  88         default:
  89                 return IB_LINK_LAYER_UNSPECIFIED;
  90         }
  91 }
  92
  93 static enum rdma_link_layer
  94 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  95 {
  96         struct mlx5_ib_dev *dev = to_mdev(device);
  97         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  98
  99         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 100 }
 101
 102 static int mlx5_netdev_event(struct notifier_block *this,
 103                              unsigned long event, void *ptr)
 104 {
 105         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 106         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 107                                                  roce.nb);
 108
 109         switch (event) {
 110         case NETDEV_REGISTER:
 111         case NETDEV_UNREGISTER:
 112                 write_lock(&ibdev->roce.netdev_lock);
 113                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 114                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 115                                              NULL : ndev;
 116                 write_unlock(&ibdev->roce.netdev_lock);
 117                 break;
 118
 119         case NETDEV_UP:
 120         case NETDEV_DOWN: {
 121                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 122                 struct net_device *upper = NULL;
 123
 124                 if (lag_ndev) {
 125                         upper = netdev_master_upper_dev_get(lag_ndev);
 126                         dev_put(lag_ndev);
 127                 }
 128
 129                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 130                     && ibdev->ib_active) {
 131                         struct ib_event ibev = {0};
 132
 133                         ibev.device = &ibdev->ib_dev;
 134                         ibev.event = (event == NETDEV_UP) ?
 135                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 136                         ibev.element.port_num = 1;
 137                         ib_dispatch_event(&ibev);
 138                 }
 139                 break;
 140         }
 141
 142         default:
 143                 break;
 144         }
 145
 146         return NOTIFY_DONE;
 147 }
 148
 149 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 150                                              u8 port_num)
 151 {
 152         struct mlx5_ib_dev *ibdev = to_mdev(device);
 153         struct net_device *ndev;
 154
 155         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 156         if (ndev)
 157                 return ndev;
 158
 159         /* Ensure ndev does not disappear before we invoke dev_hold()
 160          */
 161         read_lock(&ibdev->roce.netdev_lock);
 162         ndev = ibdev->roce.netdev;
 163         if (ndev)
 164                 dev_hold(ndev);
 165         read_unlock(&ibdev->roce.netdev_lock);
 166
 167         return ndev;
 168 }
 169
 170 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 171                                 struct ib_port_attr *props)
 172 {
 173         struct mlx5_ib_dev *dev = to_mdev(device);
 174         struct net_device *ndev, *upper;
 175         enum ib_mtu ndev_ib_mtu;
 176         u16 qkey_viol_cntr;
 177
 178         memset(props, 0, sizeof(*props));
 179
 180         props->port_cap_flags  |= IB_PORT_CM_SUP;
 181         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 182
 183         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 184                                                 roce_address_table_size);
 185         props->max_mtu          = IB_MTU_4096;
 186         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 187         props->pkey_tbl_len     = 1;
 188         props->state            = IB_PORT_DOWN;
 189         props->phys_state       = 3;
 190
 191         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 192         props->qkey_viol_cntr = qkey_viol_cntr;
 193
 194         ndev = mlx5_ib_get_netdev(device, port_num);
 195         if (!ndev)
 196                 return 0;
 197
 198         if (mlx5_lag_is_active(dev->mdev)) {
 199                 rcu_read_lock();
 200                 upper = netdev_master_upper_dev_get_rcu(ndev);
 201                 if (upper) {
 202                         dev_put(ndev);
 203                         ndev = upper;
 204                         dev_hold(ndev);
 205                 }
 206                 rcu_read_unlock();
 207         }
 208
 209         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 210                 props->state      = IB_PORT_ACTIVE;
 211                 props->phys_state = 5;
 212         }
 213
 214         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 215
 216         dev_put(ndev);
 217
 218         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 219
 220         props->active_width     = IB_WIDTH_4X;  /* TODO */
 221         props->active_speed     = IB_SPEED_QDR; /* TODO */
 222
 223         return 0;
 224 }
 225
 226 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 227                                      const struct ib_gid_attr *attr,
 228                                      void *mlx5_addr)
 229 {
 230 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 231         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 232                                                source_l3_address);
 233         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 234                                                source_mac_47_32);
 235
 236         if (!gid)
 237                 return;
 238
 239         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 240
 241         if (is_vlan_dev(attr->ndev)) {
 242                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 243                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 244         }
 245
 246         switch (attr->gid_type) {
 247         case IB_GID_TYPE_IB:
 248                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 249                 break;
 250         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 251                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 252                 break;
 253
 254         default:
 255                 WARN_ON(true);
 256         }
 257
 258         if (attr->gid_type != IB_GID_TYPE_IB) {
 259                 if (ipv6_addr_v4mapped((void *)gid))
 260                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 261                                     MLX5_ROCE_L3_TYPE_IPV4);
 262                 else
 263                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 264                                     MLX5_ROCE_L3_TYPE_IPV6);
 265         }
 266
 267         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 268             !ipv6_addr_v4mapped((void *)gid))
 269                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 270         else
 271                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 272 }
 273
 274 static int set_roce_addr(struct ib_device *device, u8 port_num,
 275                          unsigned int index,
 276                          const union ib_gid *gid,
 277                          const struct ib_gid_attr *attr)
 278 {
 279         struct mlx5_ib_dev *dev = to_mdev(device);
 280         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 281         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 282         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 283         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 284
 285         if (ll != IB_LINK_LAYER_ETHERNET)
 286                 return -EINVAL;
 287
 288         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 289
 290         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 291         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 292         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 293 }
 294
 295 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 296                            unsigned int index, const union ib_gid *gid,
 297                            const struct ib_gid_attr *attr,
 298                            __always_unused void **context)
 299 {
 300         return set_roce_addr(device, port_num, index, gid, attr);
 301 }
 302
 303 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 304                            unsigned int index, __always_unused void **context)
 305 {
 306         return set_roce_addr(device, port_num, index, NULL, NULL);
 307 }
 308
 309 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 310                                int index)
 311 {
 312         struct ib_gid_attr attr;
 313         union ib_gid gid;
 314
 315         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 316                 return 0;
 317
 318         if (!attr.ndev)
 319                 return 0;
 320
 321         dev_put(attr.ndev);
 322
 323         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 324                 return 0;
 325
 326         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 327 }
 328
 329 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 330 {
 331         return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 332 }
 333
 334 enum {
 335         MLX5_VPORT_ACCESS_METHOD_MAD,
 336         MLX5_VPORT_ACCESS_METHOD_HCA,
 337         MLX5_VPORT_ACCESS_METHOD_NIC,
 338 };
 339
 340 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 341 {
 342         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 343                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 344
 345         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 346             IB_LINK_LAYER_ETHERNET)
 347                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 348
 349         return MLX5_VPORT_ACCESS_METHOD_HCA;
 350 }
 351
 352 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 353                             struct ib_device_attr *props)
 354 {
 355         u8 tmp;
 356         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 357         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 358         u8 atomic_req_8B_endianness_mode =
 359                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 360
 361         /* Check if HW supports 8 bytes standard atomic operations and capable
 362          * of host endianness respond
 363          */
 364         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 365         if (((atomic_operations & tmp) == tmp) &&
 366             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 367             (atomic_req_8B_endianness_mode)) {
 368                 props->atomic_cap = IB_ATOMIC_HCA;
 369         } else {
 370                 props->atomic_cap = IB_ATOMIC_NONE;
 371         }
 372 }
 373
 374 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 375                                         __be64 *sys_image_guid)
 376 {
 377         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 378         struct mlx5_core_dev *mdev = dev->mdev;
 379         u64 tmp;
 380         int err;
 381
 382         switch (mlx5_get_vport_access_method(ibdev)) {
 383         case MLX5_VPORT_ACCESS_METHOD_MAD:
 384                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 385                                                             sys_image_guid);
 386
 387         case MLX5_VPORT_ACCESS_METHOD_HCA:
 388                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 389                 break;
 390
 391         case MLX5_VPORT_ACCESS_METHOD_NIC:
 392                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 393                 break;
 394
 395         default:
 396                 return -EINVAL;
 397         }
 398
 399         if (!err)
 400                 *sys_image_guid = cpu_to_be64(tmp);
 401
 402         return err;
 403
 404 }
 405
 406 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 407                                 u16 *max_pkeys)
 408 {
 409         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 410         struct mlx5_core_dev *mdev = dev->mdev;
 411
 412         switch (mlx5_get_vport_access_method(ibdev)) {
 413         case MLX5_VPORT_ACCESS_METHOD_MAD:
 414                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 415
 416         case MLX5_VPORT_ACCESS_METHOD_HCA:
 417         case MLX5_VPORT_ACCESS_METHOD_NIC:
 418                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 419                                                 pkey_table_size));
 420                 return 0;
 421
 422         default:
 423                 return -EINVAL;
 424         }
 425 }
 426
 427 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 428                                 u32 *vendor_id)
 429 {
 430         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 431
 432         switch (mlx5_get_vport_access_method(ibdev)) {
 433         case MLX5_VPORT_ACCESS_METHOD_MAD:
 434                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 435
 436         case MLX5_VPORT_ACCESS_METHOD_HCA:
 437         case MLX5_VPORT_ACCESS_METHOD_NIC:
 438                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 439
 440         default:
 441                 return -EINVAL;
 442         }
 443 }
 444
 445 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 446                                 __be64 *node_guid)
 447 {
 448         u64 tmp;
 449         int err;
 450
 451         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 452         case MLX5_VPORT_ACCESS_METHOD_MAD:
 453                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 454
 455         case MLX5_VPORT_ACCESS_METHOD_HCA:
 456                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 457                 break;
 458
 459         case MLX5_VPORT_ACCESS_METHOD_NIC:
 460                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 461                 break;
 462
 463         default:
 464                 return -EINVAL;
 465         }
 466
 467         if (!err)
 468                 *node_guid = cpu_to_be64(tmp);
 469
 470         return err;
 471 }
 472
 473 struct mlx5_reg_node_desc {
 474         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 475 };
 476
 477 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 478 {
 479         struct mlx5_reg_node_desc in;
 480
 481         if (mlx5_use_mad_ifc(dev))
 482                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 483
 484         memset(&in, 0, sizeof(in));
 485
 486         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 487                                     sizeof(struct mlx5_reg_node_desc),
 488                                     MLX5_REG_NODE_DESC, 0, 0);
 489 }
 490
 491 static int mlx5_ib_query_device(struct ib_device *ibdev,
 492                                 struct ib_device_attr *props,
 493                                 struct ib_udata *uhw)
 494 {
 495         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 496         struct mlx5_core_dev *mdev = dev->mdev;
 497         int err = -ENOMEM;
 498         int max_rq_sg;
 499         int max_sq_sg;
 500         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 501         struct mlx5_ib_query_device_resp resp = {};
 502         size_t resp_len;
 503         u64 max_tso;
 504
 505         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 506         if (uhw->outlen && uhw->outlen < resp_len)
 507                 return -EINVAL;
 508         else
 509                 resp.response_length = resp_len;
 510
 511         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 512                 return -EINVAL;
 513
 514         memset(props, 0, sizeof(*props));
 515         err = mlx5_query_system_image_guid(ibdev,
 516                                            &props->sys_image_guid);
 517         if (err)
 518                 return err;
 519
 520         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 521         if (err)
 522                 return err;
 523
 524         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 525         if (err)
 526                 return err;
 527
 528         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 529                 (fw_rev_min(dev->mdev) << 16) |
 530                 fw_rev_sub(dev->mdev);
 531         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 532                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 533                 IB_DEVICE_SYS_IMAGE_GUID                |
 534                 IB_DEVICE_RC_RNR_NAK_GEN;
 535
 536         if (MLX5_CAP_GEN(mdev, pkv))
 537                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 538         if (MLX5_CAP_GEN(mdev, qkv))
 539                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 540         if (MLX5_CAP_GEN(mdev, apm))
 541                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 542         if (MLX5_CAP_GEN(mdev, xrc))
 543                 props->device_cap_flags |= IB_DEVICE_XRC;
 544         if (MLX5_CAP_GEN(mdev, imaicl)) {
 545                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 546                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 547                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 548                 /* We support 'Gappy' memory registration too */
 549                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 550         }
 551         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 552         if (MLX5_CAP_GEN(mdev, sho)) {
 553                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 554                 /* At this stage no support for signature handover */
 555                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 556                                       IB_PROT_T10DIF_TYPE_2 |
 557                                       IB_PROT_T10DIF_TYPE_3;
 558                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 559                                        IB_GUARD_T10DIF_CSUM;
 560         }
 561         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 562                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 563
 564         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 565                 if (MLX5_CAP_ETH(mdev, csum_cap))
 566                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 567
 568                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 569                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 570                         if (max_tso) {
 571                                 resp.tso_caps.max_tso = 1 << max_tso;
 572                                 resp.tso_caps.supported_qpts |=
 573                                         1 << IB_QPT_RAW_PACKET;
 574                                 resp.response_length += sizeof(resp.tso_caps);
 575                         }
 576                 }
 577
 578                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 579                         resp.rss_caps.rx_hash_function =
 580                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 581                         resp.rss_caps.rx_hash_fields_mask =
 582                                                 MLX5_RX_HASH_SRC_IPV4 |
 583                                                 MLX5_RX_HASH_DST_IPV4 |
 584                                                 MLX5_RX_HASH_SRC_IPV6 |
 585                                                 MLX5_RX_HASH_DST_IPV6 |
 586                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 587                                                 MLX5_RX_HASH_DST_PORT_TCP |
 588                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 589                                                 MLX5_RX_HASH_DST_PORT_UDP;
 590                         resp.response_length += sizeof(resp.rss_caps);
 591                 }
 592         } else {
 593                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 594                         resp.response_length += sizeof(resp.tso_caps);
 595                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 596                         resp.response_length += sizeof(resp.rss_caps);
 597         }
 598
 599         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 600                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 601                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 602         }
 603
 604         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 605             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 606                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 607
 608         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 609                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 610
 611         props->vendor_part_id      = mdev->pdev->device;
 612         props->hw_ver              = mdev->pdev->revision;
 613
 614         props->max_mr_size         = ~0ull;
 615         props->page_size_cap       = ~(min_page_size - 1);
 616         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 617         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 618         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 619                      sizeof(struct mlx5_wqe_data_seg);
 620         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 621                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 622                      sizeof(struct mlx5_wqe_data_seg);
 623         props->max_sge = min(max_rq_sg, max_sq_sg);
 624         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 625         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 626         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 627         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 628         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 629         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 630         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 631         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 632         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 633         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 634         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 635         props->max_srq_sge         = max_rq_sg - 1;
 636         props->max_fast_reg_page_list_len =
 637                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 638         get_atomic_caps(dev, props);
 639         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 640         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 641         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 642         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 643                                            props->max_mcast_grp;
 644         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 645         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 646         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 647
 648 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 649         if (MLX5_CAP_GEN(mdev, pg))
 650                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 651         props->odp_caps = dev->odp_caps;
 652 #endif
 653
 654         if (MLX5_CAP_GEN(mdev, cd))
 655                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 656
 657         if (!mlx5_core_is_pf(mdev))
 658                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 659
 660         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 661             IB_LINK_LAYER_ETHERNET) {
 662                 props->rss_caps.max_rwq_indirection_tables =
 663                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 664                 props->rss_caps.max_rwq_indirection_table_size =
 665                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 666                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 667                 props->max_wq_type_rq =
 668                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 669         }
 670
 671         if (uhw->outlen) {
 672                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 673
 674                 if (err)
 675                         return err;
 676         }
 677
 678         return 0;
 679 }
 680
 681 enum mlx5_ib_width {
 682         MLX5_IB_WIDTH_1X        = 1 << 0,
 683         MLX5_IB_WIDTH_2X        = 1 << 1,
 684         MLX5_IB_WIDTH_4X        = 1 << 2,
 685         MLX5_IB_WIDTH_8X        = 1 << 3,
 686         MLX5_IB_WIDTH_12X       = 1 << 4
 687 };
 688
 689 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 690                                   u8 *ib_width)
 691 {
 692         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 693         int err = 0;
 694
 695         if (active_width & MLX5_IB_WIDTH_1X) {
 696                 *ib_width = IB_WIDTH_1X;
 697         } else if (active_width & MLX5_IB_WIDTH_2X) {
 698                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 699                             (int)active_width);
 700                 err = -EINVAL;
 701         } else if (active_width & MLX5_IB_WIDTH_4X) {
 702                 *ib_width = IB_WIDTH_4X;
 703         } else if (active_width & MLX5_IB_WIDTH_8X) {
 704                 *ib_width = IB_WIDTH_8X;
 705         } else if (active_width & MLX5_IB_WIDTH_12X) {
 706                 *ib_width = IB_WIDTH_12X;
 707         } else {
 708                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 709                             (int)active_width);
 710                 err = -EINVAL;
 711         }
 712
 713         return err;
 714 }
 715
 716 static int mlx5_mtu_to_ib_mtu(int mtu)
 717 {
 718         switch (mtu) {
 719         case 256: return 1;
 720         case 512: return 2;
 721         case 1024: return 3;
 722         case 2048: return 4;
 723         case 4096: return 5;
 724         default:
 725                 pr_warn("invalid mtu\n");
 726                 return -1;
 727         }
 728 }
 729
 730 enum ib_max_vl_num {
 731         __IB_MAX_VL_0           = 1,
 732         __IB_MAX_VL_0_1         = 2,
 733         __IB_MAX_VL_0_3         = 3,
 734         __IB_MAX_VL_0_7         = 4,
 735         __IB_MAX_VL_0_14        = 5,
 736 };
 737
 738 enum mlx5_vl_hw_cap {
 739         MLX5_VL_HW_0    = 1,
 740         MLX5_VL_HW_0_1  = 2,
 741         MLX5_VL_HW_0_2  = 3,
 742         MLX5_VL_HW_0_3  = 4,
 743         MLX5_VL_HW_0_4  = 5,
 744         MLX5_VL_HW_0_5  = 6,
 745         MLX5_VL_HW_0_6  = 7,
 746         MLX5_VL_HW_0_7  = 8,
 747         MLX5_VL_HW_0_14 = 15
 748 };
 749
 750 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 751                                 u8 *max_vl_num)
 752 {
 753         switch (vl_hw_cap) {
 754         case MLX5_VL_HW_0:
 755                 *max_vl_num = __IB_MAX_VL_0;
 756                 break;
 757         case MLX5_VL_HW_0_1:
 758                 *max_vl_num = __IB_MAX_VL_0_1;
 759                 break;
 760         case MLX5_VL_HW_0_3:
 761                 *max_vl_num = __IB_MAX_VL_0_3;
 762                 break;
 763         case MLX5_VL_HW_0_7:
 764                 *max_vl_num = __IB_MAX_VL_0_7;
 765                 break;
 766         case MLX5_VL_HW_0_14:
 767                 *max_vl_num = __IB_MAX_VL_0_14;
 768                 break;
 769
 770         default:
 771                 return -EINVAL;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 778                                struct ib_port_attr *props)
 779 {
 780         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 781         struct mlx5_core_dev *mdev = dev->mdev;
 782         struct mlx5_hca_vport_context *rep;
 783         u16 max_mtu;
 784         u16 oper_mtu;
 785         int err;
 786         u8 ib_link_width_oper;
 787         u8 vl_hw_cap;
 788
 789         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 790         if (!rep) {
 791                 err = -ENOMEM;
 792                 goto out;
 793         }
 794
 795         memset(props, 0, sizeof(*props));
 796
 797         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 798         if (err)
 799                 goto out;
 800
 801         props->lid              = rep->lid;
 802         props->lmc              = rep->lmc;
 803         props->sm_lid           = rep->sm_lid;
 804         props->sm_sl            = rep->sm_sl;
 805         props->state            = rep->vport_state;
 806         props->phys_state       = rep->port_physical_state;
 807         props->port_cap_flags   = rep->cap_mask1;
 808         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 809         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 810         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 811         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 812         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 813         props->subnet_timeout   = rep->subnet_timeout;
 814         props->init_type_reply  = rep->init_type_reply;
 815         props->grh_required     = rep->grh_required;
 816
 817         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 818         if (err)
 819                 goto out;
 820
 821         err = translate_active_width(ibdev, ib_link_width_oper,
 822                                      &props->active_width);
 823         if (err)
 824                 goto out;
 825         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 826         if (err)
 827                 goto out;
 828
 829         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 830
 831         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 832
 833         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 834
 835         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 836
 837         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 838         if (err)
 839                 goto out;
 840
 841         err = translate_max_vl_num(ibdev, vl_hw_cap,
 842                                    &props->max_vl_num);
 843 out:
 844         kfree(rep);
 845         return err;
 846 }
 847
 848 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 849                        struct ib_port_attr *props)
 850 {
 851         switch (mlx5_get_vport_access_method(ibdev)) {
 852         case MLX5_VPORT_ACCESS_METHOD_MAD:
 853                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 854
 855         case MLX5_VPORT_ACCESS_METHOD_HCA:
 856                 return mlx5_query_hca_port(ibdev, port, props);
 857
 858         case MLX5_VPORT_ACCESS_METHOD_NIC:
 859                 return mlx5_query_port_roce(ibdev, port, props);
 860
 861         default:
 862                 return -EINVAL;
 863         }
 864 }
 865
 866 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 867                              union ib_gid *gid)
 868 {
 869         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 870         struct mlx5_core_dev *mdev = dev->mdev;
 871
 872         switch (mlx5_get_vport_access_method(ibdev)) {
 873         case MLX5_VPORT_ACCESS_METHOD_MAD:
 874                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 875
 876         case MLX5_VPORT_ACCESS_METHOD_HCA:
 877                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 878
 879         default:
 880                 return -EINVAL;
 881         }
 882
 883 }
 884
 885 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 886                               u16 *pkey)
 887 {
 888         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 889         struct mlx5_core_dev *mdev = dev->mdev;
 890
 891         switch (mlx5_get_vport_access_method(ibdev)) {
 892         case MLX5_VPORT_ACCESS_METHOD_MAD:
 893                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 894
 895         case MLX5_VPORT_ACCESS_METHOD_HCA:
 896         case MLX5_VPORT_ACCESS_METHOD_NIC:
 897                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 898                                                  pkey);
 899         default:
 900                 return -EINVAL;
 901         }
 902 }
 903
 904 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 905                                  struct ib_device_modify *props)
 906 {
 907         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 908         struct mlx5_reg_node_desc in;
 909         struct mlx5_reg_node_desc out;
 910         int err;
 911
 912         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 913                 return -EOPNOTSUPP;
 914
 915         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 916                 return 0;
 917
 918         /*
 919          * If possible, pass node desc to FW, so it can generate
 920          * a 144 trap.  If cmd fails, just ignore.
 921          */
 922         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 923         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 924                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 925         if (err)
 926                 return err;
 927
 928         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 929
 930         return err;
 931 }
 932
 933 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 934                                struct ib_port_modify *props)
 935 {
 936         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 937         struct ib_port_attr attr;
 938         u32 tmp;
 939         int err;
 940
 941         mutex_lock(&dev->cap_mask_mutex);
 942
 943         err = mlx5_ib_query_port(ibdev, port, &attr);
 944         if (err)
 945                 goto out;
 946
 947         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 948                 ~props->clr_port_cap_mask;
 949
 950         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 951
 952 out:
 953         mutex_unlock(&dev->cap_mask_mutex);
 954         return err;
 955 }
 956
 957 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 958                                                   struct ib_udata *udata)
 959 {
 960         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 961         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 962         struct mlx5_ib_alloc_ucontext_resp resp = {};
 963         struct mlx5_ib_ucontext *context;
 964         struct mlx5_uuar_info *uuari;
 965         struct mlx5_uar *uars;
 966         int gross_uuars;
 967         int num_uars;
 968         int ver;
 969         int uuarn;
 970         int err;
 971         int i;
 972         size_t reqlen;
 973         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 974                                      max_cqe_version);
 975
 976         if (!dev->ib_active)
 977                 return ERR_PTR(-EAGAIN);
 978
 979         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 980                 return ERR_PTR(-EINVAL);
 981
 982         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 983         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 984                 ver = 0;
 985         else if (reqlen >= min_req_v2)
 986                 ver = 2;
 987         else
 988                 return ERR_PTR(-EINVAL);
 989
 990         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 991         if (err)
 992                 return ERR_PTR(err);
 993
 994         if (req.flags)
 995                 return ERR_PTR(-EINVAL);
 996
 997         if (req.total_num_uuars > MLX5_MAX_UUARS)
 998                 return ERR_PTR(-ENOMEM);
 999
1000         if (req.total_num_uuars == 0)
1001                 return ERR_PTR(-EINVAL);
1002
1003         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1004                 return ERR_PTR(-EOPNOTSUPP);
1005
1006         if (reqlen > sizeof(req) &&
1007             !ib_is_udata_cleared(udata, sizeof(req),
1008                                  reqlen - sizeof(req)))
1009                 return ERR_PTR(-EOPNOTSUPP);
1010
1011         req.total_num_uuars = ALIGN(req.total_num_uuars,
1012                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1013         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1014                 return ERR_PTR(-EINVAL);
1015
1016         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1017         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1018         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1019         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1020                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1021         resp.cache_line_size = L1_CACHE_BYTES;
1022         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1023         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1024         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1025         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1026         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1027         resp.cqe_version = min_t(__u8,
1028                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1029                                  req.max_cqe_version);
1030         resp.response_length = min(offsetof(typeof(resp), response_length) +
1031                                    sizeof(resp.response_length), udata->outlen);
1032
1033         context = kzalloc(sizeof(*context), GFP_KERNEL);
1034         if (!context)
1035                 return ERR_PTR(-ENOMEM);
1036
1037         uuari = &context->uuari;
1038         mutex_init(&uuari->lock);
1039         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1040         if (!uars) {
1041                 err = -ENOMEM;
1042                 goto out_ctx;
1043         }
1044
1045         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1046                                 sizeof(*uuari->bitmap),
1047                                 GFP_KERNEL);
1048         if (!uuari->bitmap) {
1049                 err = -ENOMEM;
1050                 goto out_uar_ctx;
1051         }
1052         /*
1053          * clear all fast path uuars
1054          */
1055         for (i = 0; i < gross_uuars; i++) {
1056                 uuarn = i & 3;
1057                 if (uuarn == 2 || uuarn == 3)
1058                         set_bit(i, uuari->bitmap);
1059         }
1060
1061         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1062         if (!uuari->count) {
1063                 err = -ENOMEM;
1064                 goto out_bitmap;
1065         }
1066
1067         for (i = 0; i < num_uars; i++) {
1068                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1069                 if (err)
1070                         goto out_count;
1071         }
1072
1073 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1074         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1075 #endif
1076
1077         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1078                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1079                                                        &context->tdn);
1080                 if (err)
1081                         goto out_uars;
1082         }
1083
1084         INIT_LIST_HEAD(&context->vma_private_list);
1085         INIT_LIST_HEAD(&context->db_page_list);
1086         mutex_init(&context->db_page_mutex);
1087
1088         resp.tot_uuars = req.total_num_uuars;
1089         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1090
1091         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1092                 resp.response_length += sizeof(resp.cqe_version);
1093
1094         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1095                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1096                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1097         }
1098
1099         /*
1100          * We don't want to expose information from the PCI bar that is located
1101          * after 4096 bytes, so if the arch only supports larger pages, let's
1102          * pretend we don't support reading the HCA's core clock. This is also
1103          * forced by mmap function.
1104          */
1105         if (PAGE_SIZE <= 4096 &&
1106             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1107                 resp.comp_mask |=
1108                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1109                 resp.hca_core_clock_offset =
1110                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1111                         PAGE_SIZE;
1112                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1113                                         sizeof(resp.reserved2);
1114         }
1115
1116         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1117         if (err)
1118                 goto out_td;
1119
1120         uuari->ver = ver;
1121         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1122         uuari->uars = uars;
1123         uuari->num_uars = num_uars;
1124         context->cqe_version = resp.cqe_version;
1125
1126         return &context->ibucontext;
1127
1128 out_td:
1129         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1130                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1131
1132 out_uars:
1133         for (i--; i >= 0; i--)
1134                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1135 out_count:
1136         kfree(uuari->count);
1137
1138 out_bitmap:
1139         kfree(uuari->bitmap);
1140
1141 out_uar_ctx:
1142         kfree(uars);
1143
1144 out_ctx:
1145         kfree(context);
1146         return ERR_PTR(err);
1147 }
1148
1149 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1150 {
1151         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1152         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1153         struct mlx5_uuar_info *uuari = &context->uuari;
1154         int i;
1155
1156         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1157                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1158
1159         for (i = 0; i < uuari->num_uars; i++) {
1160                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1161                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1162         }
1163
1164         kfree(uuari->count);
1165         kfree(uuari->bitmap);
1166         kfree(uuari->uars);
1167         kfree(context);
1168
1169         return 0;
1170 }
1171
1172 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1173 {
1174         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1175 }
1176
1177 static int get_command(unsigned long offset)
1178 {
1179         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1180 }
1181
1182 static int get_arg(unsigned long offset)
1183 {
1184         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1185 }
1186
1187 static int get_index(unsigned long offset)
1188 {
1189         return get_arg(offset);
1190 }
1191
1192 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1193 {
1194         /* vma_open is called when a new VMA is created on top of our VMA.  This
1195          * is done through either mremap flow or split_vma (usually due to
1196          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1197          * as this VMA is strongly hardware related.  Therefore we set the
1198          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1199          * calling us again and trying to do incorrect actions.  We assume that
1200          * the original VMA size is exactly a single page, and therefore all
1201          * "splitting" operation will not happen to it.
1202          */
1203         area->vm_ops = NULL;
1204 }
1205
1206 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1207 {
1208         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1209
1210         /* It's guaranteed that all VMAs opened on a FD are closed before the
1211          * file itself is closed, therefore no sync is needed with the regular
1212          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1213          * However need a sync with accessing the vma as part of
1214          * mlx5_ib_disassociate_ucontext.
1215          * The close operation is usually called under mm->mmap_sem except when
1216          * process is exiting.
1217          * The exiting case is handled explicitly as part of
1218          * mlx5_ib_disassociate_ucontext.
1219          */
1220         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1221
1222         /* setting the vma context pointer to null in the mlx5_ib driver's
1223          * private data, to protect a race condition in
1224          * mlx5_ib_disassociate_ucontext().
1225          */
1226         mlx5_ib_vma_priv_data->vma = NULL;
1227         list_del(&mlx5_ib_vma_priv_data->list);
1228         kfree(mlx5_ib_vma_priv_data);
1229 }
1230
1231 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1232         .open = mlx5_ib_vma_open,
1233         .close = mlx5_ib_vma_close
1234 };
1235
1236 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1237                                 struct mlx5_ib_ucontext *ctx)
1238 {
1239         struct mlx5_ib_vma_private_data *vma_prv;
1240         struct list_head *vma_head = &ctx->vma_private_list;
1241
1242         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1243         if (!vma_prv)
1244                 return -ENOMEM;
1245
1246         vma_prv->vma = vma;
1247         vma->vm_private_data = vma_prv;
1248         vma->vm_ops =  &mlx5_ib_vm_ops;
1249
1250         list_add(&vma_prv->list, vma_head);
1251
1252         return 0;
1253 }
1254
1255 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1256 {
1257         int ret;
1258         struct vm_area_struct *vma;
1259         struct mlx5_ib_vma_private_data *vma_private, *n;
1260         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1261         struct task_struct *owning_process  = NULL;
1262         struct mm_struct   *owning_mm       = NULL;
1263
1264         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1265         if (!owning_process)
1266                 return;
1267
1268         owning_mm = get_task_mm(owning_process);
1269         if (!owning_mm) {
1270                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1271                 while (1) {
1272                         put_task_struct(owning_process);
1273                         usleep_range(1000, 2000);
1274                         owning_process = get_pid_task(ibcontext->tgid,
1275                                                       PIDTYPE_PID);
1276                         if (!owning_process ||
1277                             owning_process->state == TASK_DEAD) {
1278                                 pr_info("disassociate ucontext done, task was terminated\n");
1279                                 /* in case task was dead need to release the
1280                                  * task struct.
1281                                  */
1282                                 if (owning_process)
1283                                         put_task_struct(owning_process);
1284                                 return;
1285                         }
1286                 }
1287         }
1288
1289         /* need to protect from a race on closing the vma as part of
1290          * mlx5_ib_vma_close.
1291          */
1292         down_read(&owning_mm->mmap_sem);
1293         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1294                                  list) {
1295                 vma = vma_private->vma;
1296                 ret = zap_vma_ptes(vma, vma->vm_start,
1297                                    PAGE_SIZE);
1298                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1299                 /* context going to be destroyed, should
1300                  * not access ops any more.
1301                  */
1302                 vma->vm_ops = NULL;
1303                 list_del(&vma_private->list);
1304                 kfree(vma_private);
1305         }
1306         up_read(&owning_mm->mmap_sem);
1307         mmput(owning_mm);
1308         put_task_struct(owning_process);
1309 }
1310
1311 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1312 {
1313         switch (cmd) {
1314         case MLX5_IB_MMAP_WC_PAGE:
1315                 return "WC";
1316         case MLX5_IB_MMAP_REGULAR_PAGE:
1317                 return "best effort WC";
1318         case MLX5_IB_MMAP_NC_PAGE:
1319                 return "NC";
1320         default:
1321                 return NULL;
1322         }
1323 }
1324
1325 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1326                     struct vm_area_struct *vma,
1327                     struct mlx5_ib_ucontext *context)
1328 {
1329         struct mlx5_uuar_info *uuari = &context->uuari;
1330         int err;
1331         unsigned long idx;
1332         phys_addr_t pfn, pa;
1333         pgprot_t prot;
1334
1335         switch (cmd) {
1336         case MLX5_IB_MMAP_WC_PAGE:
1337 /* Some architectures don't support WC memory */
1338 #if defined(CONFIG_X86)
1339                 if (!pat_enabled())
1340                         return -EPERM;
1341 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1342                         return -EPERM;
1343 #endif
1344         /* fall through */
1345         case MLX5_IB_MMAP_REGULAR_PAGE:
1346                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1347                 prot = pgprot_writecombine(vma->vm_page_prot);
1348                 break;
1349         case MLX5_IB_MMAP_NC_PAGE:
1350                 prot = pgprot_noncached(vma->vm_page_prot);
1351                 break;
1352         default:
1353                 return -EINVAL;
1354         }
1355
1356         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1357                 return -EINVAL;
1358
1359         idx = get_index(vma->vm_pgoff);
1360         if (idx >= uuari->num_uars)
1361                 return -EINVAL;
1362
1363         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1364         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1365
1366         vma->vm_page_prot = prot;
1367         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1368                                  PAGE_SIZE, vma->vm_page_prot);
1369         if (err) {
1370                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1371                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1372                 return -EAGAIN;
1373         }
1374
1375         pa = pfn << PAGE_SHIFT;
1376         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1377                     vma->vm_start, &pa);
1378
1379         return mlx5_ib_set_vma_data(vma, context);
1380 }
1381
1382 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1383 {
1384         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1385         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1386         unsigned long command;
1387         phys_addr_t pfn;
1388
1389         command = get_command(vma->vm_pgoff);
1390         switch (command) {
1391         case MLX5_IB_MMAP_WC_PAGE:
1392         case MLX5_IB_MMAP_NC_PAGE:
1393         case MLX5_IB_MMAP_REGULAR_PAGE:
1394                 return uar_mmap(dev, command, vma, context);
1395
1396         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1397                 return -ENOSYS;
1398
1399         case MLX5_IB_MMAP_CORE_CLOCK:
1400                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1401                         return -EINVAL;
1402
1403                 if (vma->vm_flags & VM_WRITE)
1404                         return -EPERM;
1405
1406                 /* Don't expose to user-space information it shouldn't have */
1407                 if (PAGE_SIZE > 4096)
1408                         return -EOPNOTSUPP;
1409
1410                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1411                 pfn = (dev->mdev->iseg_base +
1412                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1413                         PAGE_SHIFT;
1414                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1415                                        PAGE_SIZE, vma->vm_page_prot))
1416                         return -EAGAIN;
1417
1418                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1419                             vma->vm_start,
1420                             (unsigned long long)pfn << PAGE_SHIFT);
1421                 break;
1422
1423         default:
1424                 return -EINVAL;
1425         }
1426
1427         return 0;
1428 }
1429
1430 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1431                                       struct ib_ucontext *context,
1432                                       struct ib_udata *udata)
1433 {
1434         struct mlx5_ib_alloc_pd_resp resp;
1435         struct mlx5_ib_pd *pd;
1436         int err;
1437
1438         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1439         if (!pd)
1440                 return ERR_PTR(-ENOMEM);
1441
1442         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1443         if (err) {
1444                 kfree(pd);
1445                 return ERR_PTR(err);
1446         }
1447
1448         if (context) {
1449                 resp.pdn = pd->pdn;
1450                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1451                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1452                         kfree(pd);
1453                         return ERR_PTR(-EFAULT);
1454                 }
1455         }
1456
1457         return &pd->ibpd;
1458 }
1459
1460 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1461 {
1462         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1463         struct mlx5_ib_pd *mpd = to_mpd(pd);
1464
1465         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1466         kfree(mpd);
1467
1468         return 0;
1469 }
1470
1471 enum {
1472         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1473         MATCH_CRITERIA_ENABLE_MISC_BIT,
1474         MATCH_CRITERIA_ENABLE_INNER_BIT
1475 };
1476
1477 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1478         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1479                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1480
1481 static u8 get_match_criteria_enable(u32 *match_criteria)
1482 {
1483         u8 match_criteria_enable;
1484
1485         match_criteria_enable =
1486                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1487                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1488         match_criteria_enable |=
1489                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1490                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1491         match_criteria_enable |=
1492                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1493                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1494
1495         return match_criteria_enable;
1496 }
1497
1498 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1499 {
1500         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1501         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1502 }
1503
1504 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1505 {
1506         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1507         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1508         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1509         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1510 }
1511
1512 #define LAST_ETH_FIELD vlan_tag
1513 #define LAST_IB_FIELD sl
1514 #define LAST_IPV4_FIELD tos
1515 #define LAST_IPV6_FIELD traffic_class
1516 #define LAST_TCP_UDP_FIELD src_port
1517
1518 /* Field is the last supported field */
1519 #define FIELDS_NOT_SUPPORTED(filter, field)\
1520         memchr_inv((void *)&filter.field  +\
1521                    sizeof(filter.field), 0,\
1522                    sizeof(filter) -\
1523                    offsetof(typeof(filter), field) -\
1524                    sizeof(filter.field))
1525
1526 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1527                            const union ib_flow_spec *ib_spec)
1528 {
1529         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1530                                              outer_headers);
1531         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1532                                              outer_headers);
1533         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1534                                            misc_parameters);
1535         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1536                                            misc_parameters);
1537
1538         switch (ib_spec->type) {
1539         case IB_FLOW_SPEC_ETH:
1540                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1541                         return -ENOTSUPP;
1542
1543                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1544                                              dmac_47_16),
1545                                 ib_spec->eth.mask.dst_mac);
1546                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1547                                              dmac_47_16),
1548                                 ib_spec->eth.val.dst_mac);
1549
1550                 if (ib_spec->eth.mask.vlan_tag) {
1551                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1552                                  vlan_tag, 1);
1553                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1554                                  vlan_tag, 1);
1555
1556                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1557                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1558                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1559                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1560
1561                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1562                                  first_cfi,
1563                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1564                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1565                                  first_cfi,
1566                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1567
1568                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1569                                  first_prio,
1570                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1571                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1572                                  first_prio,
1573                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1574                 }
1575                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1576                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1577                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1578                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1579                 break;
1580         case IB_FLOW_SPEC_IPV4:
1581                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1582                         return -ENOTSUPP;
1583
1584                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1585                          ethertype, 0xffff);
1586                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1587                          ethertype, ETH_P_IP);
1588
1589                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1590                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1591                        &ib_spec->ipv4.mask.src_ip,
1592                        sizeof(ib_spec->ipv4.mask.src_ip));
1593                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1594                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1595                        &ib_spec->ipv4.val.src_ip,
1596                        sizeof(ib_spec->ipv4.val.src_ip));
1597                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1598                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1599                        &ib_spec->ipv4.mask.dst_ip,
1600                        sizeof(ib_spec->ipv4.mask.dst_ip));
1601                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1602                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1603                        &ib_spec->ipv4.val.dst_ip,
1604                        sizeof(ib_spec->ipv4.val.dst_ip));
1605
1606                 set_tos(outer_headers_c, outer_headers_v,
1607                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1608
1609                 set_proto(outer_headers_c, outer_headers_v,
1610                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1611                 break;
1612         case IB_FLOW_SPEC_IPV6:
1613                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1614                         return -ENOTSUPP;
1615
1616                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1617                          ethertype, 0xffff);
1618                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1619                          ethertype, ETH_P_IPV6);
1620
1621                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1622                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1623                        &ib_spec->ipv6.mask.src_ip,
1624                        sizeof(ib_spec->ipv6.mask.src_ip));
1625                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1626                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1627                        &ib_spec->ipv6.val.src_ip,
1628                        sizeof(ib_spec->ipv6.val.src_ip));
1629                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1630                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1631                        &ib_spec->ipv6.mask.dst_ip,
1632                        sizeof(ib_spec->ipv6.mask.dst_ip));
1633                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1634                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1635                        &ib_spec->ipv6.val.dst_ip,
1636                        sizeof(ib_spec->ipv6.val.dst_ip));
1637
1638                 set_tos(outer_headers_c, outer_headers_v,
1639                         ib_spec->ipv6.mask.traffic_class,
1640                         ib_spec->ipv6.val.traffic_class);
1641
1642                 set_proto(outer_headers_c, outer_headers_v,
1643                           ib_spec->ipv6.mask.next_hdr,
1644                           ib_spec->ipv6.val.next_hdr);
1645
1646                 MLX5_SET(fte_match_set_misc, misc_params_c,
1647                          outer_ipv6_flow_label,
1648                          ntohl(ib_spec->ipv6.mask.flow_label));
1649                 MLX5_SET(fte_match_set_misc, misc_params_v,
1650                          outer_ipv6_flow_label,
1651                          ntohl(ib_spec->ipv6.val.flow_label));
1652                 break;
1653         case IB_FLOW_SPEC_TCP:
1654                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1655                                          LAST_TCP_UDP_FIELD))
1656                         return -ENOTSUPP;
1657
1658                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1659                          0xff);
1660                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1661                          IPPROTO_TCP);
1662
1663                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1664                          ntohs(ib_spec->tcp_udp.mask.src_port));
1665                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1666                          ntohs(ib_spec->tcp_udp.val.src_port));
1667
1668                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1669                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1670                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1671                          ntohs(ib_spec->tcp_udp.val.dst_port));
1672                 break;
1673         case IB_FLOW_SPEC_UDP:
1674                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1675                                          LAST_TCP_UDP_FIELD))
1676                         return -ENOTSUPP;
1677
1678                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1679                          0xff);
1680                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1681                          IPPROTO_UDP);
1682
1683                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1684                          ntohs(ib_spec->tcp_udp.mask.src_port));
1685                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1686                          ntohs(ib_spec->tcp_udp.val.src_port));
1687
1688                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1689                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1690                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1691                          ntohs(ib_spec->tcp_udp.val.dst_port));
1692                 break;
1693         default:
1694                 return -EINVAL;
1695         }
1696
1697         return 0;
1698 }
1699
1700 /* If a flow could catch both multicast and unicast packets,
1701  * it won't fall into the multicast flow steering table and this rule
1702  * could steal other multicast packets.
1703  */
1704 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1705 {
1706         struct ib_flow_spec_eth *eth_spec;
1707
1708         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1709             ib_attr->size < sizeof(struct ib_flow_attr) +
1710             sizeof(struct ib_flow_spec_eth) ||
1711             ib_attr->num_of_specs < 1)
1712                 return false;
1713
1714         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1715         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1716             eth_spec->size != sizeof(*eth_spec))
1717                 return false;
1718
1719         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1720                is_multicast_ether_addr(eth_spec->val.dst_mac);
1721 }
1722
1723 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1724 {
1725         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1726         bool has_ipv4_spec = false;
1727         bool eth_type_ipv4 = true;
1728         unsigned int spec_index;
1729
1730         /* Validate that ethertype is correct */
1731         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1732                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1733                     ib_spec->eth.mask.ether_type) {
1734                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1735                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1736                                 eth_type_ipv4 = false;
1737                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1738                         has_ipv4_spec = true;
1739                 }
1740                 ib_spec = (void *)ib_spec + ib_spec->size;
1741         }
1742         return !has_ipv4_spec || eth_type_ipv4;
1743 }
1744
1745 static void put_flow_table(struct mlx5_ib_dev *dev,
1746                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1747 {
1748         prio->refcount -= !!ft_added;
1749         if (!prio->refcount) {
1750                 mlx5_destroy_flow_table(prio->flow_table);
1751                 prio->flow_table = NULL;
1752         }
1753 }
1754
1755 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1756 {
1757         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1758         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1759                                                           struct mlx5_ib_flow_handler,
1760                                                           ibflow);
1761         struct mlx5_ib_flow_handler *iter, *tmp;
1762
1763         mutex_lock(&dev->flow_db.lock);
1764
1765         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1766                 mlx5_del_flow_rule(iter->rule);
1767                 put_flow_table(dev, iter->prio, true);
1768                 list_del(&iter->list);
1769                 kfree(iter);
1770         }
1771
1772         mlx5_del_flow_rule(handler->rule);
1773         put_flow_table(dev, handler->prio, true);
1774         mutex_unlock(&dev->flow_db.lock);
1775
1776         kfree(handler);
1777
1778         return 0;
1779 }
1780
1781 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1782 {
1783         priority *= 2;
1784         if (!dont_trap)
1785                 priority++;
1786         return priority;
1787 }
1788
1789 enum flow_table_type {
1790         MLX5_IB_FT_RX,
1791         MLX5_IB_FT_TX
1792 };
1793
1794 #define MLX5_FS_MAX_TYPES        10
1795 #define MLX5_FS_MAX_ENTRIES      32000UL
1796 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1797                                                 struct ib_flow_attr *flow_attr,
1798                                                 enum flow_table_type ft_type)
1799 {
1800         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1801         struct mlx5_flow_namespace *ns = NULL;
1802         struct mlx5_ib_flow_prio *prio;
1803         struct mlx5_flow_table *ft;
1804         int num_entries;
1805         int num_groups;
1806         int priority;
1807         int err = 0;
1808
1809         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1810                 if (flow_is_multicast_only(flow_attr) &&
1811                     !dont_trap)
1812                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1813                 else
1814                         priority = ib_prio_to_core_prio(flow_attr->priority,
1815                                                         dont_trap);
1816                 ns = mlx5_get_flow_namespace(dev->mdev,
1817                                              MLX5_FLOW_NAMESPACE_BYPASS);
1818                 num_entries = MLX5_FS_MAX_ENTRIES;
1819                 num_groups = MLX5_FS_MAX_TYPES;
1820                 prio = &dev->flow_db.prios[priority];
1821         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1822                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1823                 ns = mlx5_get_flow_namespace(dev->mdev,
1824                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1825                 build_leftovers_ft_param(&priority,
1826                                          &num_entries,
1827                                          &num_groups);
1828                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1829         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1830                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1831                                         allow_sniffer_and_nic_rx_shared_tir))
1832                         return ERR_PTR(-ENOTSUPP);
1833
1834                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1835                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1836                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1837
1838                 prio = &dev->flow_db.sniffer[ft_type];
1839                 priority = 0;
1840                 num_entries = 1;
1841                 num_groups = 1;
1842         }
1843
1844         if (!ns)
1845                 return ERR_PTR(-ENOTSUPP);
1846
1847         ft = prio->flow_table;
1848         if (!ft) {
1849                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1850                                                          num_entries,
1851                                                          num_groups,
1852                                                          0);
1853
1854                 if (!IS_ERR(ft)) {
1855                         prio->refcount = 0;
1856                         prio->flow_table = ft;
1857                 } else {
1858                         err = PTR_ERR(ft);
1859                 }
1860         }
1861
1862         return err ? ERR_PTR(err) : prio;
1863 }
1864
1865 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1866                                                      struct mlx5_ib_flow_prio *ft_prio,
1867                                                      const struct ib_flow_attr *flow_attr,
1868                                                      struct mlx5_flow_destination *dst)
1869 {
1870         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1871         struct mlx5_ib_flow_handler *handler;
1872         struct mlx5_flow_spec *spec;
1873         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1874         unsigned int spec_index;
1875         u32 action;
1876         int err = 0;
1877
1878         if (!is_valid_attr(flow_attr))
1879                 return ERR_PTR(-EINVAL);
1880
1881         spec = mlx5_vzalloc(sizeof(*spec));
1882         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1883         if (!handler || !spec) {
1884                 err = -ENOMEM;
1885                 goto free;
1886         }
1887
1888         INIT_LIST_HEAD(&handler->list);
1889
1890         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1891                 err = parse_flow_attr(spec->match_criteria,
1892                                       spec->match_value, ib_flow);
1893                 if (err < 0)
1894                         goto free;
1895
1896                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1897         }
1898
1899         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1900         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1901                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1902         handler->rule = mlx5_add_flow_rule(ft, spec,
1903                                            action,
1904                                            MLX5_FS_DEFAULT_FLOW_TAG,
1905                                            dst);
1906
1907         if (IS_ERR(handler->rule)) {
1908                 err = PTR_ERR(handler->rule);
1909                 goto free;
1910         }
1911
1912         ft_prio->refcount++;
1913         handler->prio = ft_prio;
1914
1915         ft_prio->flow_table = ft;
1916 free:
1917         if (err)
1918                 kfree(handler);
1919         kvfree(spec);
1920         return err ? ERR_PTR(err) : handler;
1921 }
1922
1923 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1924                                                           struct mlx5_ib_flow_prio *ft_prio,
1925                                                           struct ib_flow_attr *flow_attr,
1926                                                           struct mlx5_flow_destination *dst)
1927 {
1928         struct mlx5_ib_flow_handler *handler_dst = NULL;
1929         struct mlx5_ib_flow_handler *handler = NULL;
1930
1931         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1932         if (!IS_ERR(handler)) {
1933                 handler_dst = create_flow_rule(dev, ft_prio,
1934                                                flow_attr, dst);
1935                 if (IS_ERR(handler_dst)) {
1936                         mlx5_del_flow_rule(handler->rule);
1937                         ft_prio->refcount--;
1938                         kfree(handler);
1939                         handler = handler_dst;
1940                 } else {
1941                         list_add(&handler_dst->list, &handler->list);
1942                 }
1943         }
1944
1945         return handler;
1946 }
1947 enum {
1948         LEFTOVERS_MC,
1949         LEFTOVERS_UC,
1950 };
1951
1952 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1953                                                           struct mlx5_ib_flow_prio *ft_prio,
1954                                                           struct ib_flow_attr *flow_attr,
1955                                                           struct mlx5_flow_destination *dst)
1956 {
1957         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1958         struct mlx5_ib_flow_handler *handler = NULL;
1959
1960         static struct {
1961                 struct ib_flow_attr     flow_attr;
1962                 struct ib_flow_spec_eth eth_flow;
1963         } leftovers_specs[] = {
1964                 [LEFTOVERS_MC] = {
1965                         .flow_attr = {
1966                                 .num_of_specs = 1,
1967                                 .size = sizeof(leftovers_specs[0])
1968                         },
1969                         .eth_flow = {
1970                                 .type = IB_FLOW_SPEC_ETH,
1971                                 .size = sizeof(struct ib_flow_spec_eth),
1972                                 .mask = {.dst_mac = {0x1} },
1973                                 .val =  {.dst_mac = {0x1} }
1974                         }
1975                 },
1976                 [LEFTOVERS_UC] = {
1977                         .flow_attr = {
1978                                 .num_of_specs = 1,
1979                                 .size = sizeof(leftovers_specs[0])
1980                         },
1981                         .eth_flow = {
1982                                 .type = IB_FLOW_SPEC_ETH,
1983                                 .size = sizeof(struct ib_flow_spec_eth),
1984                                 .mask = {.dst_mac = {0x1} },
1985                                 .val = {.dst_mac = {} }
1986                         }
1987                 }
1988         };
1989
1990         handler = create_flow_rule(dev, ft_prio,
1991                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1992                                    dst);
1993         if (!IS_ERR(handler) &&
1994             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1995                 handler_ucast = create_flow_rule(dev, ft_prio,
1996                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1997                                                  dst);
1998                 if (IS_ERR(handler_ucast)) {
1999                         mlx5_del_flow_rule(handler->rule);
2000                         ft_prio->refcount--;
2001                         kfree(handler);
2002                         handler = handler_ucast;
2003                 } else {
2004                         list_add(&handler_ucast->list, &handler->list);
2005                 }
2006         }
2007
2008         return handler;
2009 }
2010
2011 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2012                                                         struct mlx5_ib_flow_prio *ft_rx,
2013                                                         struct mlx5_ib_flow_prio *ft_tx,
2014                                                         struct mlx5_flow_destination *dst)
2015 {
2016         struct mlx5_ib_flow_handler *handler_rx;
2017         struct mlx5_ib_flow_handler *handler_tx;
2018         int err;
2019         static const struct ib_flow_attr flow_attr  = {
2020                 .num_of_specs = 0,
2021                 .size = sizeof(flow_attr)
2022         };
2023
2024         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2025         if (IS_ERR(handler_rx)) {
2026                 err = PTR_ERR(handler_rx);
2027                 goto err;
2028         }
2029
2030         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2031         if (IS_ERR(handler_tx)) {
2032                 err = PTR_ERR(handler_tx);
2033                 goto err_tx;
2034         }
2035
2036         list_add(&handler_tx->list, &handler_rx->list);
2037
2038         return handler_rx;
2039
2040 err_tx:
2041         mlx5_del_flow_rule(handler_rx->rule);
2042         ft_rx->refcount--;
2043         kfree(handler_rx);
2044 err:
2045         return ERR_PTR(err);
2046 }
2047
2048 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2049                                            struct ib_flow_attr *flow_attr,
2050                                            int domain)
2051 {
2052         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2053         struct mlx5_ib_flow_handler *handler = NULL;
2054         struct mlx5_flow_destination *dst = NULL;
2055         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2056         struct mlx5_ib_flow_prio *ft_prio;
2057         int err;
2058
2059         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2060                 return ERR_PTR(-ENOSPC);
2061
2062         if (domain != IB_FLOW_DOMAIN_USER ||
2063             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2064             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2065                 return ERR_PTR(-EINVAL);
2066
2067         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2068         if (!dst)
2069                 return ERR_PTR(-ENOMEM);
2070
2071         mutex_lock(&dev->flow_db.lock);
2072
2073         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2074         if (IS_ERR(ft_prio)) {
2075                 err = PTR_ERR(ft_prio);
2076                 goto unlock;
2077         }
2078         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2079                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2080                 if (IS_ERR(ft_prio_tx)) {
2081                         err = PTR_ERR(ft_prio_tx);
2082                         ft_prio_tx = NULL;
2083                         goto destroy_ft;
2084                 }
2085         }
2086
2087         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2088         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
2089
2090         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2091                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2092                         handler = create_dont_trap_rule(dev, ft_prio,
2093                                                         flow_attr, dst);
2094                 } else {
2095                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2096                                                    dst);
2097                 }
2098         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2099                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2100                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2101                                                 dst);
2102         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2103                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2104         } else {
2105                 err = -EINVAL;
2106                 goto destroy_ft;
2107         }
2108
2109         if (IS_ERR(handler)) {
2110                 err = PTR_ERR(handler);
2111                 handler = NULL;
2112                 goto destroy_ft;
2113         }
2114
2115         mutex_unlock(&dev->flow_db.lock);
2116         kfree(dst);
2117
2118         return &handler->ibflow;
2119
2120 destroy_ft:
2121         put_flow_table(dev, ft_prio, false);
2122         if (ft_prio_tx)
2123                 put_flow_table(dev, ft_prio_tx, false);
2124 unlock:
2125         mutex_unlock(&dev->flow_db.lock);
2126         kfree(dst);
2127         kfree(handler);
2128         return ERR_PTR(err);
2129 }
2130
2131 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2132 {
2133         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2134         int err;
2135
2136         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2137         if (err)
2138                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2139                              ibqp->qp_num, gid->raw);
2140
2141         return err;
2142 }
2143
2144 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2145 {
2146         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2147         int err;
2148
2149         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2150         if (err)
2151                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2152                              ibqp->qp_num, gid->raw);
2153
2154         return err;
2155 }
2156
2157 static int init_node_data(struct mlx5_ib_dev *dev)
2158 {
2159         int err;
2160
2161         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2162         if (err)
2163                 return err;
2164
2165         dev->mdev->rev_id = dev->mdev->pdev->revision;
2166
2167         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2168 }
2169
2170 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2171                              char *buf)
2172 {
2173         struct mlx5_ib_dev *dev =
2174                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2175
2176         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2177 }
2178
2179 static ssize_t show_reg_pages(struct device *device,
2180                               struct device_attribute *attr, char *buf)
2181 {
2182         struct mlx5_ib_dev *dev =
2183                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2184
2185         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2186 }
2187
2188 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2189                         char *buf)
2190 {
2191         struct mlx5_ib_dev *dev =
2192                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2193         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2194 }
2195
2196 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2197                         char *buf)
2198 {
2199         struct mlx5_ib_dev *dev =
2200                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2201         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2202 }
2203
2204 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2205                           char *buf)
2206 {
2207         struct mlx5_ib_dev *dev =
2208                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2209         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2210                        dev->mdev->board_id);
2211 }
2212
2213 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2214 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2215 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2216 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2217 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2218
2219 static struct device_attribute *mlx5_class_attributes[] = {
2220         &dev_attr_hw_rev,
2221         &dev_attr_hca_type,
2222         &dev_attr_board_id,
2223         &dev_attr_fw_pages,
2224         &dev_attr_reg_pages,
2225 };
2226
2227 static void pkey_change_handler(struct work_struct *work)
2228 {
2229         struct mlx5_ib_port_resources *ports =
2230                 container_of(work, struct mlx5_ib_port_resources,
2231                              pkey_change_work);
2232
2233         mutex_lock(&ports->devr->mutex);
2234         mlx5_ib_gsi_pkey_change(ports->gsi);
2235         mutex_unlock(&ports->devr->mutex);
2236 }
2237
2238 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2239 {
2240         struct mlx5_ib_qp *mqp;
2241         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2242         struct mlx5_core_cq *mcq;
2243         struct list_head cq_armed_list;
2244         unsigned long flags_qp;
2245         unsigned long flags_cq;
2246         unsigned long flags;
2247
2248         INIT_LIST_HEAD(&cq_armed_list);
2249
2250         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2251         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2252         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2253                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2254                 if (mqp->sq.tail != mqp->sq.head) {
2255                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2256                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2257                         if (send_mcq->mcq.comp &&
2258                             mqp->ibqp.send_cq->comp_handler) {
2259                                 if (!send_mcq->mcq.reset_notify_added) {
2260                                         send_mcq->mcq.reset_notify_added = 1;
2261                                         list_add_tail(&send_mcq->mcq.reset_notify,
2262                                                       &cq_armed_list);
2263                                 }
2264                         }
2265                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2266                 }
2267                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2268                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2269                 /* no handling is needed for SRQ */
2270                 if (!mqp->ibqp.srq) {
2271                         if (mqp->rq.tail != mqp->rq.head) {
2272                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2273                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2274                                 if (recv_mcq->mcq.comp &&
2275                                     mqp->ibqp.recv_cq->comp_handler) {
2276                                         if (!recv_mcq->mcq.reset_notify_added) {
2277                                                 recv_mcq->mcq.reset_notify_added = 1;
2278                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2279                                                               &cq_armed_list);
2280                                         }
2281                                 }
2282                                 spin_unlock_irqrestore(&recv_mcq->lock,
2283                                                        flags_cq);
2284                         }
2285                 }
2286                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2287         }
2288         /*At that point all inflight post send were put to be executed as of we
2289          * lock/unlock above locks Now need to arm all involved CQs.
2290          */
2291         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2292                 mcq->comp(mcq);
2293         }
2294         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2295 }
2296
2297 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2298                           enum mlx5_dev_event event, unsigned long param)
2299 {
2300         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2301         struct ib_event ibev;
2302
2303         u8 port = 0;
2304
2305         switch (event) {
2306         case MLX5_DEV_EVENT_SYS_ERROR:
2307                 ibdev->ib_active = false;
2308                 ibev.event = IB_EVENT_DEVICE_FATAL;
2309                 mlx5_ib_handle_internal_error(ibdev);
2310                 break;
2311
2312         case MLX5_DEV_EVENT_PORT_UP:
2313         case MLX5_DEV_EVENT_PORT_DOWN:
2314         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2315                 port = (u8)param;
2316
2317                 /* In RoCE, port up/down events are handled in
2318                  * mlx5_netdev_event().
2319                  */
2320                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2321                         IB_LINK_LAYER_ETHERNET)
2322                         return;
2323
2324                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2325                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2326                 break;
2327
2328         case MLX5_DEV_EVENT_LID_CHANGE:
2329                 ibev.event = IB_EVENT_LID_CHANGE;
2330                 port = (u8)param;
2331                 break;
2332
2333         case MLX5_DEV_EVENT_PKEY_CHANGE:
2334                 ibev.event = IB_EVENT_PKEY_CHANGE;
2335                 port = (u8)param;
2336
2337                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2338                 break;
2339
2340         case MLX5_DEV_EVENT_GUID_CHANGE:
2341                 ibev.event = IB_EVENT_GID_CHANGE;
2342                 port = (u8)param;
2343                 break;
2344
2345         case MLX5_DEV_EVENT_CLIENT_REREG:
2346                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2347                 port = (u8)param;
2348                 break;
2349         }
2350
2351         ibev.device           = &ibdev->ib_dev;
2352         ibev.element.port_num = port;
2353
2354         if (port < 1 || port > ibdev->num_ports) {
2355                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2356                 return;
2357         }
2358
2359         if (ibdev->ib_active)
2360                 ib_dispatch_event(&ibev);
2361 }
2362
2363 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2364 {
2365         int port;
2366
2367         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2368                 mlx5_query_ext_port_caps(dev, port);
2369 }
2370
2371 static int get_port_caps(struct mlx5_ib_dev *dev)
2372 {
2373         struct ib_device_attr *dprops = NULL;
2374         struct ib_port_attr *pprops = NULL;
2375         int err = -ENOMEM;
2376         int port;
2377         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2378
2379         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2380         if (!pprops)
2381                 goto out;
2382
2383         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2384         if (!dprops)
2385                 goto out;
2386
2387         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2388         if (err) {
2389                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2390                 goto out;
2391         }
2392
2393         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2394                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2395                 if (err) {
2396                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2397                                      port, err);
2398                         break;
2399                 }
2400                 dev->mdev->port_caps[port - 1].pkey_table_len =
2401                                                 dprops->max_pkeys;
2402                 dev->mdev->port_caps[port - 1].gid_table_len =
2403                                                 pprops->gid_tbl_len;
2404                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2405                             dprops->max_pkeys, pprops->gid_tbl_len);
2406         }
2407
2408 out:
2409         kfree(pprops);
2410         kfree(dprops);
2411
2412         return err;
2413 }
2414
2415 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2416 {
2417         int err;
2418
2419         err = mlx5_mr_cache_cleanup(dev);
2420         if (err)
2421                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2422
2423         mlx5_ib_destroy_qp(dev->umrc.qp);
2424         ib_free_cq(dev->umrc.cq);
2425         ib_dealloc_pd(dev->umrc.pd);
2426 }
2427
2428 enum {
2429         MAX_UMR_WR = 128,
2430 };
2431
2432 static int create_umr_res(struct mlx5_ib_dev *dev)
2433 {
2434         struct ib_qp_init_attr *init_attr = NULL;
2435         struct ib_qp_attr *attr = NULL;
2436         struct ib_pd *pd;
2437         struct ib_cq *cq;
2438         struct ib_qp *qp;
2439         int ret;
2440
2441         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2442         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2443         if (!attr || !init_attr) {
2444                 ret = -ENOMEM;
2445                 goto error_0;
2446         }
2447
2448         pd = ib_alloc_pd(&dev->ib_dev, 0);
2449         if (IS_ERR(pd)) {
2450                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2451                 ret = PTR_ERR(pd);
2452                 goto error_0;
2453         }
2454
2455         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2456         if (IS_ERR(cq)) {
2457                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2458                 ret = PTR_ERR(cq);
2459                 goto error_2;
2460         }
2461
2462         init_attr->send_cq = cq;
2463         init_attr->recv_cq = cq;
2464         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2465         init_attr->cap.max_send_wr = MAX_UMR_WR;
2466         init_attr->cap.max_send_sge = 1;
2467         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2468         init_attr->port_num = 1;
2469         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2470         if (IS_ERR(qp)) {
2471                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2472                 ret = PTR_ERR(qp);
2473                 goto error_3;
2474         }
2475         qp->device     = &dev->ib_dev;
2476         qp->real_qp    = qp;
2477         qp->uobject    = NULL;
2478         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2479
2480         attr->qp_state = IB_QPS_INIT;
2481         attr->port_num = 1;
2482         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2483                                 IB_QP_PORT, NULL);
2484         if (ret) {
2485                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2486                 goto error_4;
2487         }
2488
2489         memset(attr, 0, sizeof(*attr));
2490         attr->qp_state = IB_QPS_RTR;
2491         attr->path_mtu = IB_MTU_256;
2492
2493         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2494         if (ret) {
2495                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2496                 goto error_4;
2497         }
2498
2499         memset(attr, 0, sizeof(*attr));
2500         attr->qp_state = IB_QPS_RTS;
2501         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2502         if (ret) {
2503                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2504                 goto error_4;
2505         }
2506
2507         dev->umrc.qp = qp;
2508         dev->umrc.cq = cq;
2509         dev->umrc.pd = pd;
2510
2511         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2512         ret = mlx5_mr_cache_init(dev);
2513         if (ret) {
2514                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2515                 goto error_4;
2516         }
2517
2518         kfree(attr);
2519         kfree(init_attr);
2520
2521         return 0;
2522
2523 error_4:
2524         mlx5_ib_destroy_qp(qp);
2525
2526 error_3:
2527         ib_free_cq(cq);
2528
2529 error_2:
2530         ib_dealloc_pd(pd);
2531
2532 error_0:
2533         kfree(attr);
2534         kfree(init_attr);
2535         return ret;
2536 }
2537
2538 static int create_dev_resources(struct mlx5_ib_resources *devr)
2539 {
2540         struct ib_srq_init_attr attr;
2541         struct mlx5_ib_dev *dev;
2542         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2543         int port;
2544         int ret = 0;
2545
2546         dev = container_of(devr, struct mlx5_ib_dev, devr);
2547
2548         mutex_init(&devr->mutex);
2549
2550         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2551         if (IS_ERR(devr->p0)) {
2552                 ret = PTR_ERR(devr->p0);
2553                 goto error0;
2554         }
2555         devr->p0->device  = &dev->ib_dev;
2556         devr->p0->uobject = NULL;
2557         atomic_set(&devr->p0->usecnt, 0);
2558
2559         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2560         if (IS_ERR(devr->c0)) {
2561                 ret = PTR_ERR(devr->c0);
2562                 goto error1;
2563         }
2564         devr->c0->device        = &dev->ib_dev;
2565         devr->c0->uobject       = NULL;
2566         devr->c0->comp_handler  = NULL;
2567         devr->c0->event_handler = NULL;
2568         devr->c0->cq_context    = NULL;
2569         atomic_set(&devr->c0->usecnt, 0);
2570
2571         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2572         if (IS_ERR(devr->x0)) {
2573                 ret = PTR_ERR(devr->x0);
2574                 goto error2;
2575         }
2576         devr->x0->device = &dev->ib_dev;
2577         devr->x0->inode = NULL;
2578         atomic_set(&devr->x0->usecnt, 0);
2579         mutex_init(&devr->x0->tgt_qp_mutex);
2580         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2581
2582         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2583         if (IS_ERR(devr->x1)) {
2584                 ret = PTR_ERR(devr->x1);
2585                 goto error3;
2586         }
2587         devr->x1->device = &dev->ib_dev;
2588         devr->x1->inode = NULL;
2589         atomic_set(&devr->x1->usecnt, 0);
2590         mutex_init(&devr->x1->tgt_qp_mutex);
2591         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2592
2593         memset(&attr, 0, sizeof(attr));
2594         attr.attr.max_sge = 1;
2595         attr.attr.max_wr = 1;
2596         attr.srq_type = IB_SRQT_XRC;
2597         attr.ext.xrc.cq = devr->c0;
2598         attr.ext.xrc.xrcd = devr->x0;
2599
2600         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2601         if (IS_ERR(devr->s0)) {
2602                 ret = PTR_ERR(devr->s0);
2603                 goto error4;
2604         }
2605         devr->s0->device        = &dev->ib_dev;
2606         devr->s0->pd            = devr->p0;
2607         devr->s0->uobject       = NULL;
2608         devr->s0->event_handler = NULL;
2609         devr->s0->srq_context   = NULL;
2610         devr->s0->srq_type      = IB_SRQT_XRC;
2611         devr->s0->ext.xrc.xrcd  = devr->x0;
2612         devr->s0->ext.xrc.cq    = devr->c0;
2613         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2614         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2615         atomic_inc(&devr->p0->usecnt);
2616         atomic_set(&devr->s0->usecnt, 0);
2617
2618         memset(&attr, 0, sizeof(attr));
2619         attr.attr.max_sge = 1;
2620         attr.attr.max_wr = 1;
2621         attr.srq_type = IB_SRQT_BASIC;
2622         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2623         if (IS_ERR(devr->s1)) {
2624                 ret = PTR_ERR(devr->s1);
2625                 goto error5;
2626         }
2627         devr->s1->device        = &dev->ib_dev;
2628         devr->s1->pd            = devr->p0;
2629         devr->s1->uobject       = NULL;
2630         devr->s1->event_handler = NULL;
2631         devr->s1->srq_context   = NULL;
2632         devr->s1->srq_type      = IB_SRQT_BASIC;
2633         devr->s1->ext.xrc.cq    = devr->c0;
2634         atomic_inc(&devr->p0->usecnt);
2635         atomic_set(&devr->s0->usecnt, 0);
2636
2637         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2638                 INIT_WORK(&devr->ports[port].pkey_change_work,
2639                           pkey_change_handler);
2640                 devr->ports[port].devr = devr;
2641         }
2642
2643         return 0;
2644
2645 error5:
2646         mlx5_ib_destroy_srq(devr->s0);
2647 error4:
2648         mlx5_ib_dealloc_xrcd(devr->x1);
2649 error3:
2650         mlx5_ib_dealloc_xrcd(devr->x0);
2651 error2:
2652         mlx5_ib_destroy_cq(devr->c0);
2653 error1:
2654         mlx5_ib_dealloc_pd(devr->p0);
2655 error0:
2656         return ret;
2657 }
2658
2659 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2660 {
2661         struct mlx5_ib_dev *dev =
2662                 container_of(devr, struct mlx5_ib_dev, devr);
2663         int port;
2664
2665         mlx5_ib_destroy_srq(devr->s1);
2666         mlx5_ib_destroy_srq(devr->s0);
2667         mlx5_ib_dealloc_xrcd(devr->x0);
2668         mlx5_ib_dealloc_xrcd(devr->x1);
2669         mlx5_ib_destroy_cq(devr->c0);
2670         mlx5_ib_dealloc_pd(devr->p0);
2671
2672         /* Make sure no change P_Key work items are still executing */
2673         for (port = 0; port < dev->num_ports; ++port)
2674                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2675 }
2676
2677 static u32 get_core_cap_flags(struct ib_device *ibdev)
2678 {
2679         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2680         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2681         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2682         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2683         u32 ret = 0;
2684
2685         if (ll == IB_LINK_LAYER_INFINIBAND)
2686                 return RDMA_CORE_PORT_IBA_IB;
2687
2688         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2689                 return 0;
2690
2691         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2692                 return 0;
2693
2694         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2695                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2696
2697         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2698                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2699
2700         return ret;
2701 }
2702
2703 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2704                                struct ib_port_immutable *immutable)
2705 {
2706         struct ib_port_attr attr;
2707         int err;
2708
2709         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2710         if (err)
2711                 return err;
2712
2713         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2714         immutable->gid_tbl_len = attr.gid_tbl_len;
2715         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2716         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2717
2718         return 0;
2719 }
2720
2721 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2722                            size_t str_len)
2723 {
2724         struct mlx5_ib_dev *dev =
2725                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2726         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2727                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2728 }
2729
2730 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2731 {
2732         struct mlx5_core_dev *mdev = dev->mdev;
2733         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2734                                                                  MLX5_FLOW_NAMESPACE_LAG);
2735         struct mlx5_flow_table *ft;
2736         int err;
2737
2738         if (!ns || !mlx5_lag_is_active(mdev))
2739                 return 0;
2740
2741         err = mlx5_cmd_create_vport_lag(mdev);
2742         if (err)
2743                 return err;
2744
2745         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2746         if (IS_ERR(ft)) {
2747                 err = PTR_ERR(ft);
2748                 goto err_destroy_vport_lag;
2749         }
2750
2751         dev->flow_db.lag_demux_ft = ft;
2752         return 0;
2753
2754 err_destroy_vport_lag:
2755         mlx5_cmd_destroy_vport_lag(mdev);
2756         return err;
2757 }
2758
2759 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2760 {
2761         struct mlx5_core_dev *mdev = dev->mdev;
2762
2763         if (dev->flow_db.lag_demux_ft) {
2764                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2765                 dev->flow_db.lag_demux_ft = NULL;
2766
2767                 mlx5_cmd_destroy_vport_lag(mdev);
2768         }
2769 }
2770
2771 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2772 {
2773         if (dev->roce.nb.notifier_call) {
2774                 unregister_netdevice_notifier(&dev->roce.nb);
2775                 dev->roce.nb.notifier_call = NULL;
2776         }
2777 }
2778
2779 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2780 {
2781         int err;
2782
2783         dev->roce.nb.notifier_call = mlx5_netdev_event;
2784         err = register_netdevice_notifier(&dev->roce.nb);
2785         if (err) {
2786                 dev->roce.nb.notifier_call = NULL;
2787                 return err;
2788         }
2789
2790         err = mlx5_nic_vport_enable_roce(dev->mdev);
2791         if (err)
2792                 goto err_unregister_netdevice_notifier;
2793
2794         err = mlx5_roce_lag_init(dev);
2795         if (err)
2796                 goto err_disable_roce;
2797
2798         return 0;
2799
2800 err_disable_roce:
2801         mlx5_nic_vport_disable_roce(dev->mdev);
2802
2803 err_unregister_netdevice_notifier:
2804         mlx5_remove_roce_notifier(dev);
2805         return err;
2806 }
2807
2808 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2809 {
2810         mlx5_roce_lag_cleanup(dev);
2811         mlx5_nic_vport_disable_roce(dev->mdev);
2812 }
2813
2814 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2815 {
2816         unsigned int i;
2817
2818         for (i = 0; i < dev->num_ports; i++)
2819                 mlx5_core_dealloc_q_counter(dev->mdev,
2820                                             dev->port[i].q_cnt_id);
2821 }
2822
2823 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2824 {
2825         int i;
2826         int ret;
2827
2828         for (i = 0; i < dev->num_ports; i++) {
2829                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2830                                                 &dev->port[i].q_cnt_id);
2831                 if (ret) {
2832                         mlx5_ib_warn(dev,
2833                                      "couldn't allocate queue counter for port %d, err %d\n",
2834                                      i + 1, ret);
2835                         goto dealloc_counters;
2836                 }
2837         }
2838
2839         return 0;
2840
2841 dealloc_counters:
2842         while (--i >= 0)
2843                 mlx5_core_dealloc_q_counter(dev->mdev,
2844                                             dev->port[i].q_cnt_id);
2845
2846         return ret;
2847 }
2848
2849 static const char * const names[] = {
2850         "rx_write_requests",
2851         "rx_read_requests",
2852         "rx_atomic_requests",
2853         "out_of_buffer",
2854         "out_of_sequence",
2855         "duplicate_request",
2856         "rnr_nak_retry_err",
2857         "packet_seq_err",
2858         "implied_nak_seq_err",
2859         "local_ack_timeout_err",
2860 };
2861
2862 static const size_t stats_offsets[] = {
2863         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2864         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2865         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2866         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2867         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2868         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2869         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2870         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2871         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2872         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2873 };
2874
2875 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2876                                                     u8 port_num)
2877 {
2878         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2879
2880         /* We support only per port stats */
2881         if (port_num == 0)
2882                 return NULL;
2883
2884         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2885                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2886 }
2887
2888 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2889                                 struct rdma_hw_stats *stats,
2890                                 u8 port, int index)
2891 {
2892         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2893         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2894         void *out;
2895         __be32 val;
2896         int ret;
2897         int i;
2898
2899         if (!port || !stats)
2900                 return -ENOSYS;
2901
2902         out = mlx5_vzalloc(outlen);
2903         if (!out)
2904                 return -ENOMEM;
2905
2906         ret = mlx5_core_query_q_counter(dev->mdev,
2907                                         dev->port[port - 1].q_cnt_id, 0,
2908                                         out, outlen);
2909         if (ret)
2910                 goto free;
2911
2912         for (i = 0; i < ARRAY_SIZE(names); i++) {
2913                 val = *(__be32 *)(out + stats_offsets[i]);
2914                 stats->value[i] = (u64)be32_to_cpu(val);
2915         }
2916 free:
2917         kvfree(out);
2918         return ARRAY_SIZE(names);
2919 }
2920
2921 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2922 {
2923         struct mlx5_ib_dev *dev;
2924         enum rdma_link_layer ll;
2925         int port_type_cap;
2926         const char *name;
2927         int err;
2928         int i;
2929
2930         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2931         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2932
2933         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2934                 return NULL;
2935
2936         printk_once(KERN_INFO "%s", mlx5_version);
2937
2938         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2939         if (!dev)
2940                 return NULL;
2941
2942         dev->mdev = mdev;
2943
2944         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2945                             GFP_KERNEL);
2946         if (!dev->port)
2947                 goto err_dealloc;
2948
2949         rwlock_init(&dev->roce.netdev_lock);
2950         err = get_port_caps(dev);
2951         if (err)
2952                 goto err_free_port;
2953
2954         if (mlx5_use_mad_ifc(dev))
2955                 get_ext_port_caps(dev);
2956
2957         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2958
2959         if (!mlx5_lag_is_active(mdev))
2960                 name = "mlx5_%d";
2961         else
2962                 name = "mlx5_bond_%d";
2963
2964         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2965         dev->ib_dev.owner               = THIS_MODULE;
2966         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2967         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2968         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2969         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2970         dev->ib_dev.num_comp_vectors    =
2971                 dev->mdev->priv.eq_table.num_comp_vectors;
2972         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2973
2974         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2975         dev->ib_dev.uverbs_cmd_mask     =
2976                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2977                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2978                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2979                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2980                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2981                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2982                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2983                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2984                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2985                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2986                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2987                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2988                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2989                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2990                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2991                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2992                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2993                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2994                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2995                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2996                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2997                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2998                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2999                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3000         dev->ib_dev.uverbs_ex_cmd_mask =
3001                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3002                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3003                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3004
3005         dev->ib_dev.query_device        = mlx5_ib_query_device;
3006         dev->ib_dev.query_port          = mlx5_ib_query_port;
3007         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3008         if (ll == IB_LINK_LAYER_ETHERNET)
3009                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3010         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3011         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3012         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3013         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3014         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3015         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3016         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3017         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3018         dev->ib_dev.mmap                = mlx5_ib_mmap;
3019         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3020         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3021         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3022         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3023         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3024         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3025         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3026         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3027         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3028         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3029         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3030         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3031         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3032         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3033         dev->ib_dev.post_send           = mlx5_ib_post_send;
3034         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3035         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3036         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3037         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3038         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3039         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3040         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3041         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3042         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3043         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3044         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3045         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3046         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3047         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3048         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3049         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3050         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3051         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3052         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3053         if (mlx5_core_is_pf(mdev)) {
3054                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3055                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3056                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3057                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3058         }
3059
3060         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3061
3062         mlx5_ib_internal_fill_odp_caps(dev);
3063
3064         if (MLX5_CAP_GEN(mdev, imaicl)) {
3065                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3066                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3067                 dev->ib_dev.uverbs_cmd_mask |=
3068                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3069                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3070         }
3071
3072         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3073             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3074                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3075                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3076         }
3077
3078         if (MLX5_CAP_GEN(mdev, xrc)) {
3079                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3080                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3081                 dev->ib_dev.uverbs_cmd_mask |=
3082                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3083                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3084         }
3085
3086         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3087             IB_LINK_LAYER_ETHERNET) {
3088                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3089                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3090                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3091                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3092                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3093                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3094                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3095                 dev->ib_dev.uverbs_ex_cmd_mask |=
3096                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3097                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3098                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3099                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3100                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3101                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3102                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3103         }
3104         err = init_node_data(dev);
3105         if (err)
3106                 goto err_dealloc;
3107
3108         mutex_init(&dev->flow_db.lock);
3109         mutex_init(&dev->cap_mask_mutex);
3110         INIT_LIST_HEAD(&dev->qp_list);
3111         spin_lock_init(&dev->reset_flow_resource_lock);
3112
3113         if (ll == IB_LINK_LAYER_ETHERNET) {
3114                 err = mlx5_enable_roce(dev);
3115                 if (err)
3116                         goto err_dealloc;
3117         }
3118
3119         err = create_dev_resources(&dev->devr);
3120         if (err)
3121                 goto err_disable_roce;
3122
3123         err = mlx5_ib_odp_init_one(dev);
3124         if (err)
3125                 goto err_rsrc;
3126
3127         err = mlx5_ib_alloc_q_counters(dev);
3128         if (err)
3129                 goto err_odp;
3130
3131         err = ib_register_device(&dev->ib_dev, NULL);
3132         if (err)
3133                 goto err_q_cnt;
3134
3135         err = create_umr_res(dev);
3136         if (err)
3137                 goto err_dev;
3138
3139         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3140                 err = device_create_file(&dev->ib_dev.dev,
3141                                          mlx5_class_attributes[i]);
3142                 if (err)
3143                         goto err_umrc;
3144         }
3145
3146         dev->ib_active = true;
3147
3148         return dev;
3149
3150 err_umrc:
3151         destroy_umrc_res(dev);
3152
3153 err_dev:
3154         ib_unregister_device(&dev->ib_dev);
3155
3156 err_q_cnt:
3157         mlx5_ib_dealloc_q_counters(dev);
3158
3159 err_odp:
3160         mlx5_ib_odp_remove_one(dev);
3161
3162 err_rsrc:
3163         destroy_dev_resources(&dev->devr);
3164
3165 err_disable_roce:
3166         if (ll == IB_LINK_LAYER_ETHERNET) {
3167                 mlx5_disable_roce(dev);
3168                 mlx5_remove_roce_notifier(dev);
3169         }
3170
3171 err_free_port:
3172         kfree(dev->port);
3173
3174 err_dealloc:
3175         ib_dealloc_device((struct ib_device *)dev);
3176
3177         return NULL;
3178 }
3179
3180 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3181 {
3182         struct mlx5_ib_dev *dev = context;
3183         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3184
3185         mlx5_remove_roce_notifier(dev);
3186         ib_unregister_device(&dev->ib_dev);
3187         mlx5_ib_dealloc_q_counters(dev);
3188         destroy_umrc_res(dev);
3189         mlx5_ib_odp_remove_one(dev);
3190         destroy_dev_resources(&dev->devr);
3191         if (ll == IB_LINK_LAYER_ETHERNET)
3192                 mlx5_disable_roce(dev);
3193         kfree(dev->port);
3194         ib_dealloc_device(&dev->ib_dev);
3195 }
3196
3197 static struct mlx5_interface mlx5_ib_interface = {
3198         .add            = mlx5_ib_add,
3199         .remove         = mlx5_ib_remove,
3200         .event          = mlx5_ib_event,
3201         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3202 };
3203
3204 static int __init mlx5_ib_init(void)
3205 {
3206         int err;
3207
3208         if (deprecated_prof_sel != 2)
3209                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3210
3211         err = mlx5_ib_odp_init();
3212         if (err)
3213                 return err;
3214
3215         err = mlx5_register_interface(&mlx5_ib_interface);
3216         if (err)
3217                 goto clean_odp;
3218
3219         return err;
3220
3221 clean_odp:
3222         mlx5_ib_odp_cleanup();
3223         return err;
3224 }
3225
3226 static void __exit mlx5_ib_cleanup(void)
3227 {
3228         mlx5_unregister_interface(&mlx5_ib_interface);
3229         mlx5_ib_odp_cleanup();
3230 }
3231
3232 module_init(mlx5_ib_init);
3233 module_exit(mlx5_ib_cleanup);