drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_addr.h>
  48 #include <rdma/ib_cache.h>
  49 #include <linux/mlx5/port.h>
  50 #include <linux/mlx5/vport.h>
  51 #include <linux/list.h>
  52 #include <rdma/ib_smi.h>
  53 #include <rdma/ib_umem.h>
  54 #include <linux/in.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/mlx5/fs.h>
  57 #include "user.h"
  58 #include "mlx5_ib.h"
  59
  60 #define DRIVER_NAME "mlx5_ib"
  61 #define DRIVER_VERSION "2.2-1"
  62 #define DRIVER_RELDATE  "Feb 2014"
  63
  64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  66 MODULE_LICENSE("Dual BSD/GPL");
  67 MODULE_VERSION(DRIVER_VERSION);
  68
  69 static int deprecated_prof_sel = 2;
  70 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  71 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  72
  73 static char mlx5_version[] =
  74         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  75         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  76
  77 enum {
  78         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  79 };
  80
  81 static enum rdma_link_layer
  82 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  83 {
  84         switch (port_type_cap) {
  85         case MLX5_CAP_PORT_TYPE_IB:
  86                 return IB_LINK_LAYER_INFINIBAND;
  87         case MLX5_CAP_PORT_TYPE_ETH:
  88                 return IB_LINK_LAYER_ETHERNET;
  89         default:
  90                 return IB_LINK_LAYER_UNSPECIFIED;
  91         }
  92 }
  93
  94 static enum rdma_link_layer
  95 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  96 {
  97         struct mlx5_ib_dev *dev = to_mdev(device);
  98         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  99
 100         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 101 }
 102
 103 static int mlx5_netdev_event(struct notifier_block *this,
 104                              unsigned long event, void *ptr)
 105 {
 106         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 107         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 108                                                  roce.nb);
 109
 110         switch (event) {
 111         case NETDEV_REGISTER:
 112         case NETDEV_UNREGISTER:
 113                 write_lock(&ibdev->roce.netdev_lock);
 114                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 115                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 116                                              NULL : ndev;
 117                 write_unlock(&ibdev->roce.netdev_lock);
 118                 break;
 119
 120         case NETDEV_UP:
 121         case NETDEV_DOWN:
 122                 if (ndev == ibdev->roce.netdev && ibdev->ib_active) {
 123                         struct ib_event ibev = {0};
 124
 125                         ibev.device = &ibdev->ib_dev;
 126                         ibev.event = (event == NETDEV_UP) ?
 127                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 128                         ibev.element.port_num = 1;
 129                         ib_dispatch_event(&ibev);
 130                 }
 131                 break;
 132
 133         default:
 134                 break;
 135         }
 136
 137         return NOTIFY_DONE;
 138 }
 139
 140 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 141                                              u8 port_num)
 142 {
 143         struct mlx5_ib_dev *ibdev = to_mdev(device);
 144         struct net_device *ndev;
 145
 146         /* Ensure ndev does not disappear before we invoke dev_hold()
 147          */
 148         read_lock(&ibdev->roce.netdev_lock);
 149         ndev = ibdev->roce.netdev;
 150         if (ndev)
 151                 dev_hold(ndev);
 152         read_unlock(&ibdev->roce.netdev_lock);
 153
 154         return ndev;
 155 }
 156
 157 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 158                                 struct ib_port_attr *props)
 159 {
 160         struct mlx5_ib_dev *dev = to_mdev(device);
 161         struct net_device *ndev;
 162         enum ib_mtu ndev_ib_mtu;
 163         u16 qkey_viol_cntr;
 164
 165         memset(props, 0, sizeof(*props));
 166
 167         props->port_cap_flags  |= IB_PORT_CM_SUP;
 168         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 169
 170         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 171                                                 roce_address_table_size);
 172         props->max_mtu          = IB_MTU_4096;
 173         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 174         props->pkey_tbl_len     = 1;
 175         props->state            = IB_PORT_DOWN;
 176         props->phys_state       = 3;
 177
 178         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 179         props->qkey_viol_cntr = qkey_viol_cntr;
 180
 181         ndev = mlx5_ib_get_netdev(device, port_num);
 182         if (!ndev)
 183                 return 0;
 184
 185         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 186                 props->state      = IB_PORT_ACTIVE;
 187                 props->phys_state = 5;
 188         }
 189
 190         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 191
 192         dev_put(ndev);
 193
 194         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 195
 196         props->active_width     = IB_WIDTH_4X;  /* TODO */
 197         props->active_speed     = IB_SPEED_QDR; /* TODO */
 198
 199         return 0;
 200 }
 201
 202 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 203                                      const struct ib_gid_attr *attr,
 204                                      void *mlx5_addr)
 205 {
 206 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 207         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 208                                                source_l3_address);
 209         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 210                                                source_mac_47_32);
 211
 212         if (!gid)
 213                 return;
 214
 215         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 216
 217         if (is_vlan_dev(attr->ndev)) {
 218                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 219                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 220         }
 221
 222         switch (attr->gid_type) {
 223         case IB_GID_TYPE_IB:
 224                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 225                 break;
 226         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 227                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 228                 break;
 229
 230         default:
 231                 WARN_ON(true);
 232         }
 233
 234         if (attr->gid_type != IB_GID_TYPE_IB) {
 235                 if (ipv6_addr_v4mapped((void *)gid))
 236                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 237                                     MLX5_ROCE_L3_TYPE_IPV4);
 238                 else
 239                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 240                                     MLX5_ROCE_L3_TYPE_IPV6);
 241         }
 242
 243         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 244             !ipv6_addr_v4mapped((void *)gid))
 245                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 246         else
 247                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 248 }
 249
 250 static int set_roce_addr(struct ib_device *device, u8 port_num,
 251                          unsigned int index,
 252                          const union ib_gid *gid,
 253                          const struct ib_gid_attr *attr)
 254 {
 255         struct mlx5_ib_dev *dev = to_mdev(device);
 256         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 257         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 258         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 259         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 260
 261         if (ll != IB_LINK_LAYER_ETHERNET)
 262                 return -EINVAL;
 263
 264         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 265
 266         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 267         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 268         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 269 }
 270
 271 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 272                            unsigned int index, const union ib_gid *gid,
 273                            const struct ib_gid_attr *attr,
 274                            __always_unused void **context)
 275 {
 276         return set_roce_addr(device, port_num, index, gid, attr);
 277 }
 278
 279 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 280                            unsigned int index, __always_unused void **context)
 281 {
 282         return set_roce_addr(device, port_num, index, NULL, NULL);
 283 }
 284
 285 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 286                                int index)
 287 {
 288         struct ib_gid_attr attr;
 289         union ib_gid gid;
 290
 291         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 292                 return 0;
 293
 294         if (!attr.ndev)
 295                 return 0;
 296
 297         dev_put(attr.ndev);
 298
 299         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 300                 return 0;
 301
 302         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 303 }
 304
 305 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 306 {
 307         return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 308 }
 309
 310 enum {
 311         MLX5_VPORT_ACCESS_METHOD_MAD,
 312         MLX5_VPORT_ACCESS_METHOD_HCA,
 313         MLX5_VPORT_ACCESS_METHOD_NIC,
 314 };
 315
 316 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 317 {
 318         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 319                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 320
 321         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 322             IB_LINK_LAYER_ETHERNET)
 323                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 324
 325         return MLX5_VPORT_ACCESS_METHOD_HCA;
 326 }
 327
 328 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 329                             struct ib_device_attr *props)
 330 {
 331         u8 tmp;
 332         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 333         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 334         u8 atomic_req_8B_endianness_mode =
 335                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 336
 337         /* Check if HW supports 8 bytes standard atomic operations and capable
 338          * of host endianness respond
 339          */
 340         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 341         if (((atomic_operations & tmp) == tmp) &&
 342             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 343             (atomic_req_8B_endianness_mode)) {
 344                 props->atomic_cap = IB_ATOMIC_HCA;
 345         } else {
 346                 props->atomic_cap = IB_ATOMIC_NONE;
 347         }
 348 }
 349
 350 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 351                                         __be64 *sys_image_guid)
 352 {
 353         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 354         struct mlx5_core_dev *mdev = dev->mdev;
 355         u64 tmp;
 356         int err;
 357
 358         switch (mlx5_get_vport_access_method(ibdev)) {
 359         case MLX5_VPORT_ACCESS_METHOD_MAD:
 360                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 361                                                             sys_image_guid);
 362
 363         case MLX5_VPORT_ACCESS_METHOD_HCA:
 364                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 365                 break;
 366
 367         case MLX5_VPORT_ACCESS_METHOD_NIC:
 368                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 369                 break;
 370
 371         default:
 372                 return -EINVAL;
 373         }
 374
 375         if (!err)
 376                 *sys_image_guid = cpu_to_be64(tmp);
 377
 378         return err;
 379
 380 }
 381
 382 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 383                                 u16 *max_pkeys)
 384 {
 385         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 386         struct mlx5_core_dev *mdev = dev->mdev;
 387
 388         switch (mlx5_get_vport_access_method(ibdev)) {
 389         case MLX5_VPORT_ACCESS_METHOD_MAD:
 390                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 391
 392         case MLX5_VPORT_ACCESS_METHOD_HCA:
 393         case MLX5_VPORT_ACCESS_METHOD_NIC:
 394                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 395                                                 pkey_table_size));
 396                 return 0;
 397
 398         default:
 399                 return -EINVAL;
 400         }
 401 }
 402
 403 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 404                                 u32 *vendor_id)
 405 {
 406         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 407
 408         switch (mlx5_get_vport_access_method(ibdev)) {
 409         case MLX5_VPORT_ACCESS_METHOD_MAD:
 410                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 411
 412         case MLX5_VPORT_ACCESS_METHOD_HCA:
 413         case MLX5_VPORT_ACCESS_METHOD_NIC:
 414                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 415
 416         default:
 417                 return -EINVAL;
 418         }
 419 }
 420
 421 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 422                                 __be64 *node_guid)
 423 {
 424         u64 tmp;
 425         int err;
 426
 427         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 428         case MLX5_VPORT_ACCESS_METHOD_MAD:
 429                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 430
 431         case MLX5_VPORT_ACCESS_METHOD_HCA:
 432                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 433                 break;
 434
 435         case MLX5_VPORT_ACCESS_METHOD_NIC:
 436                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 437                 break;
 438
 439         default:
 440                 return -EINVAL;
 441         }
 442
 443         if (!err)
 444                 *node_guid = cpu_to_be64(tmp);
 445
 446         return err;
 447 }
 448
 449 struct mlx5_reg_node_desc {
 450         u8      desc[64];
 451 };
 452
 453 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 454 {
 455         struct mlx5_reg_node_desc in;
 456
 457         if (mlx5_use_mad_ifc(dev))
 458                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 459
 460         memset(&in, 0, sizeof(in));
 461
 462         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 463                                     sizeof(struct mlx5_reg_node_desc),
 464                                     MLX5_REG_NODE_DESC, 0, 0);
 465 }
 466
 467 static int mlx5_ib_query_device(struct ib_device *ibdev,
 468                                 struct ib_device_attr *props,
 469                                 struct ib_udata *uhw)
 470 {
 471         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 472         struct mlx5_core_dev *mdev = dev->mdev;
 473         int err = -ENOMEM;
 474         int max_rq_sg;
 475         int max_sq_sg;
 476         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 477         struct mlx5_ib_query_device_resp resp = {};
 478         size_t resp_len;
 479         u64 max_tso;
 480
 481         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 482         if (uhw->outlen && uhw->outlen < resp_len)
 483                 return -EINVAL;
 484         else
 485                 resp.response_length = resp_len;
 486
 487         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 488                 return -EINVAL;
 489
 490         memset(props, 0, sizeof(*props));
 491         err = mlx5_query_system_image_guid(ibdev,
 492                                            &props->sys_image_guid);
 493         if (err)
 494                 return err;
 495
 496         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 497         if (err)
 498                 return err;
 499
 500         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 501         if (err)
 502                 return err;
 503
 504         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 505                 (fw_rev_min(dev->mdev) << 16) |
 506                 fw_rev_sub(dev->mdev);
 507         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 508                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 509                 IB_DEVICE_SYS_IMAGE_GUID                |
 510                 IB_DEVICE_RC_RNR_NAK_GEN;
 511
 512         if (MLX5_CAP_GEN(mdev, pkv))
 513                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 514         if (MLX5_CAP_GEN(mdev, qkv))
 515                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 516         if (MLX5_CAP_GEN(mdev, apm))
 517                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 518         if (MLX5_CAP_GEN(mdev, xrc))
 519                 props->device_cap_flags |= IB_DEVICE_XRC;
 520         if (MLX5_CAP_GEN(mdev, imaicl)) {
 521                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 522                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 523                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 524                 /* We support 'Gappy' memory registration too */
 525                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 526         }
 527         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 528         if (MLX5_CAP_GEN(mdev, sho)) {
 529                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 530                 /* At this stage no support for signature handover */
 531                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 532                                       IB_PROT_T10DIF_TYPE_2 |
 533                                       IB_PROT_T10DIF_TYPE_3;
 534                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 535                                        IB_GUARD_T10DIF_CSUM;
 536         }
 537         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 538                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 539
 540         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 541                 if (MLX5_CAP_ETH(mdev, csum_cap))
 542                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 543
 544                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 545                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 546                         if (max_tso) {
 547                                 resp.tso_caps.max_tso = 1 << max_tso;
 548                                 resp.tso_caps.supported_qpts |=
 549                                         1 << IB_QPT_RAW_PACKET;
 550                                 resp.response_length += sizeof(resp.tso_caps);
 551                         }
 552                 }
 553
 554                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 555                         resp.rss_caps.rx_hash_function =
 556                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 557                         resp.rss_caps.rx_hash_fields_mask =
 558                                                 MLX5_RX_HASH_SRC_IPV4 |
 559                                                 MLX5_RX_HASH_DST_IPV4 |
 560                                                 MLX5_RX_HASH_SRC_IPV6 |
 561                                                 MLX5_RX_HASH_DST_IPV6 |
 562                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 563                                                 MLX5_RX_HASH_DST_PORT_TCP |
 564                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 565                                                 MLX5_RX_HASH_DST_PORT_UDP;
 566                         resp.response_length += sizeof(resp.rss_caps);
 567                 }
 568         } else {
 569                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 570                         resp.response_length += sizeof(resp.tso_caps);
 571                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 572                         resp.response_length += sizeof(resp.rss_caps);
 573         }
 574
 575         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 576                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 577                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 578         }
 579
 580         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 581             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 582                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 583
 584         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 585                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 586
 587         props->vendor_part_id      = mdev->pdev->device;
 588         props->hw_ver              = mdev->pdev->revision;
 589
 590         props->max_mr_size         = ~0ull;
 591         props->page_size_cap       = ~(min_page_size - 1);
 592         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 593         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 594         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 595                      sizeof(struct mlx5_wqe_data_seg);
 596         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 597                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 598                      sizeof(struct mlx5_wqe_data_seg);
 599         props->max_sge = min(max_rq_sg, max_sq_sg);
 600         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 601         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 602         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 603         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 604         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 605         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 606         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 607         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 608         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 609         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 610         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 611         props->max_srq_sge         = max_rq_sg - 1;
 612         props->max_fast_reg_page_list_len =
 613                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 614         get_atomic_caps(dev, props);
 615         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 616         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 617         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 618         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 619                                            props->max_mcast_grp;
 620         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 621         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 622         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 623
 624 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 625         if (MLX5_CAP_GEN(mdev, pg))
 626                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 627         props->odp_caps = dev->odp_caps;
 628 #endif
 629
 630         if (MLX5_CAP_GEN(mdev, cd))
 631                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 632
 633         if (!mlx5_core_is_pf(mdev))
 634                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 635
 636         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 637             IB_LINK_LAYER_ETHERNET) {
 638                 props->rss_caps.max_rwq_indirection_tables =
 639                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 640                 props->rss_caps.max_rwq_indirection_table_size =
 641                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 642                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 643                 props->max_wq_type_rq =
 644                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 645         }
 646
 647         if (uhw->outlen) {
 648                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 649
 650                 if (err)
 651                         return err;
 652         }
 653
 654         return 0;
 655 }
 656
 657 enum mlx5_ib_width {
 658         MLX5_IB_WIDTH_1X        = 1 << 0,
 659         MLX5_IB_WIDTH_2X        = 1 << 1,
 660         MLX5_IB_WIDTH_4X        = 1 << 2,
 661         MLX5_IB_WIDTH_8X        = 1 << 3,
 662         MLX5_IB_WIDTH_12X       = 1 << 4
 663 };
 664
 665 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 666                                   u8 *ib_width)
 667 {
 668         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 669         int err = 0;
 670
 671         if (active_width & MLX5_IB_WIDTH_1X) {
 672                 *ib_width = IB_WIDTH_1X;
 673         } else if (active_width & MLX5_IB_WIDTH_2X) {
 674                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 675                             (int)active_width);
 676                 err = -EINVAL;
 677         } else if (active_width & MLX5_IB_WIDTH_4X) {
 678                 *ib_width = IB_WIDTH_4X;
 679         } else if (active_width & MLX5_IB_WIDTH_8X) {
 680                 *ib_width = IB_WIDTH_8X;
 681         } else if (active_width & MLX5_IB_WIDTH_12X) {
 682                 *ib_width = IB_WIDTH_12X;
 683         } else {
 684                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 685                             (int)active_width);
 686                 err = -EINVAL;
 687         }
 688
 689         return err;
 690 }
 691
 692 static int mlx5_mtu_to_ib_mtu(int mtu)
 693 {
 694         switch (mtu) {
 695         case 256: return 1;
 696         case 512: return 2;
 697         case 1024: return 3;
 698         case 2048: return 4;
 699         case 4096: return 5;
 700         default:
 701                 pr_warn("invalid mtu\n");
 702                 return -1;
 703         }
 704 }
 705
 706 enum ib_max_vl_num {
 707         __IB_MAX_VL_0           = 1,
 708         __IB_MAX_VL_0_1         = 2,
 709         __IB_MAX_VL_0_3         = 3,
 710         __IB_MAX_VL_0_7         = 4,
 711         __IB_MAX_VL_0_14        = 5,
 712 };
 713
 714 enum mlx5_vl_hw_cap {
 715         MLX5_VL_HW_0    = 1,
 716         MLX5_VL_HW_0_1  = 2,
 717         MLX5_VL_HW_0_2  = 3,
 718         MLX5_VL_HW_0_3  = 4,
 719         MLX5_VL_HW_0_4  = 5,
 720         MLX5_VL_HW_0_5  = 6,
 721         MLX5_VL_HW_0_6  = 7,
 722         MLX5_VL_HW_0_7  = 8,
 723         MLX5_VL_HW_0_14 = 15
 724 };
 725
 726 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 727                                 u8 *max_vl_num)
 728 {
 729         switch (vl_hw_cap) {
 730         case MLX5_VL_HW_0:
 731                 *max_vl_num = __IB_MAX_VL_0;
 732                 break;
 733         case MLX5_VL_HW_0_1:
 734                 *max_vl_num = __IB_MAX_VL_0_1;
 735                 break;
 736         case MLX5_VL_HW_0_3:
 737                 *max_vl_num = __IB_MAX_VL_0_3;
 738                 break;
 739         case MLX5_VL_HW_0_7:
 740                 *max_vl_num = __IB_MAX_VL_0_7;
 741                 break;
 742         case MLX5_VL_HW_0_14:
 743                 *max_vl_num = __IB_MAX_VL_0_14;
 744                 break;
 745
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 754                                struct ib_port_attr *props)
 755 {
 756         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 757         struct mlx5_core_dev *mdev = dev->mdev;
 758         struct mlx5_hca_vport_context *rep;
 759         u16 max_mtu;
 760         u16 oper_mtu;
 761         int err;
 762         u8 ib_link_width_oper;
 763         u8 vl_hw_cap;
 764
 765         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 766         if (!rep) {
 767                 err = -ENOMEM;
 768                 goto out;
 769         }
 770
 771         memset(props, 0, sizeof(*props));
 772
 773         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 774         if (err)
 775                 goto out;
 776
 777         props->lid              = rep->lid;
 778         props->lmc              = rep->lmc;
 779         props->sm_lid           = rep->sm_lid;
 780         props->sm_sl            = rep->sm_sl;
 781         props->state            = rep->vport_state;
 782         props->phys_state       = rep->port_physical_state;
 783         props->port_cap_flags   = rep->cap_mask1;
 784         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 785         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 786         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 787         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 788         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 789         props->subnet_timeout   = rep->subnet_timeout;
 790         props->init_type_reply  = rep->init_type_reply;
 791         props->grh_required     = rep->grh_required;
 792
 793         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 794         if (err)
 795                 goto out;
 796
 797         err = translate_active_width(ibdev, ib_link_width_oper,
 798                                      &props->active_width);
 799         if (err)
 800                 goto out;
 801         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 802         if (err)
 803                 goto out;
 804
 805         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 806
 807         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 808
 809         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 810
 811         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 812
 813         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 814         if (err)
 815                 goto out;
 816
 817         err = translate_max_vl_num(ibdev, vl_hw_cap,
 818                                    &props->max_vl_num);
 819 out:
 820         kfree(rep);
 821         return err;
 822 }
 823
 824 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 825                        struct ib_port_attr *props)
 826 {
 827         switch (mlx5_get_vport_access_method(ibdev)) {
 828         case MLX5_VPORT_ACCESS_METHOD_MAD:
 829                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 830
 831         case MLX5_VPORT_ACCESS_METHOD_HCA:
 832                 return mlx5_query_hca_port(ibdev, port, props);
 833
 834         case MLX5_VPORT_ACCESS_METHOD_NIC:
 835                 return mlx5_query_port_roce(ibdev, port, props);
 836
 837         default:
 838                 return -EINVAL;
 839         }
 840 }
 841
 842 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 843                              union ib_gid *gid)
 844 {
 845         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 846         struct mlx5_core_dev *mdev = dev->mdev;
 847
 848         switch (mlx5_get_vport_access_method(ibdev)) {
 849         case MLX5_VPORT_ACCESS_METHOD_MAD:
 850                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 851
 852         case MLX5_VPORT_ACCESS_METHOD_HCA:
 853                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 854
 855         default:
 856                 return -EINVAL;
 857         }
 858
 859 }
 860
 861 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 862                               u16 *pkey)
 863 {
 864         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 865         struct mlx5_core_dev *mdev = dev->mdev;
 866
 867         switch (mlx5_get_vport_access_method(ibdev)) {
 868         case MLX5_VPORT_ACCESS_METHOD_MAD:
 869                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 870
 871         case MLX5_VPORT_ACCESS_METHOD_HCA:
 872         case MLX5_VPORT_ACCESS_METHOD_NIC:
 873                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 874                                                  pkey);
 875         default:
 876                 return -EINVAL;
 877         }
 878 }
 879
 880 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 881                                  struct ib_device_modify *props)
 882 {
 883         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 884         struct mlx5_reg_node_desc in;
 885         struct mlx5_reg_node_desc out;
 886         int err;
 887
 888         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 889                 return -EOPNOTSUPP;
 890
 891         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 892                 return 0;
 893
 894         /*
 895          * If possible, pass node desc to FW, so it can generate
 896          * a 144 trap.  If cmd fails, just ignore.
 897          */
 898         memcpy(&in, props->node_desc, 64);
 899         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 900                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 901         if (err)
 902                 return err;
 903
 904         memcpy(ibdev->node_desc, props->node_desc, 64);
 905
 906         return err;
 907 }
 908
 909 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 910                                struct ib_port_modify *props)
 911 {
 912         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 913         struct ib_port_attr attr;
 914         u32 tmp;
 915         int err;
 916
 917         mutex_lock(&dev->cap_mask_mutex);
 918
 919         err = mlx5_ib_query_port(ibdev, port, &attr);
 920         if (err)
 921                 goto out;
 922
 923         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 924                 ~props->clr_port_cap_mask;
 925
 926         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 927
 928 out:
 929         mutex_unlock(&dev->cap_mask_mutex);
 930         return err;
 931 }
 932
 933 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 934                                                   struct ib_udata *udata)
 935 {
 936         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 937         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 938         struct mlx5_ib_alloc_ucontext_resp resp = {};
 939         struct mlx5_ib_ucontext *context;
 940         struct mlx5_uuar_info *uuari;
 941         struct mlx5_uar *uars;
 942         int gross_uuars;
 943         int num_uars;
 944         int ver;
 945         int uuarn;
 946         int err;
 947         int i;
 948         size_t reqlen;
 949         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 950                                      max_cqe_version);
 951
 952         if (!dev->ib_active)
 953                 return ERR_PTR(-EAGAIN);
 954
 955         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 956                 return ERR_PTR(-EINVAL);
 957
 958         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 959         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 960                 ver = 0;
 961         else if (reqlen >= min_req_v2)
 962                 ver = 2;
 963         else
 964                 return ERR_PTR(-EINVAL);
 965
 966         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 967         if (err)
 968                 return ERR_PTR(err);
 969
 970         if (req.flags)
 971                 return ERR_PTR(-EINVAL);
 972
 973         if (req.total_num_uuars > MLX5_MAX_UUARS)
 974                 return ERR_PTR(-ENOMEM);
 975
 976         if (req.total_num_uuars == 0)
 977                 return ERR_PTR(-EINVAL);
 978
 979         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
 980                 return ERR_PTR(-EOPNOTSUPP);
 981
 982         if (reqlen > sizeof(req) &&
 983             !ib_is_udata_cleared(udata, sizeof(req),
 984                                  reqlen - sizeof(req)))
 985                 return ERR_PTR(-EOPNOTSUPP);
 986
 987         req.total_num_uuars = ALIGN(req.total_num_uuars,
 988                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
 989         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
 990                 return ERR_PTR(-EINVAL);
 991
 992         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
 993         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
 994         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
 995         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
 996                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
 997         resp.cache_line_size = L1_CACHE_BYTES;
 998         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
 999         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1000         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1001         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1002         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1003         resp.cqe_version = min_t(__u8,
1004                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1005                                  req.max_cqe_version);
1006         resp.response_length = min(offsetof(typeof(resp), response_length) +
1007                                    sizeof(resp.response_length), udata->outlen);
1008
1009         context = kzalloc(sizeof(*context), GFP_KERNEL);
1010         if (!context)
1011                 return ERR_PTR(-ENOMEM);
1012
1013         uuari = &context->uuari;
1014         mutex_init(&uuari->lock);
1015         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1016         if (!uars) {
1017                 err = -ENOMEM;
1018                 goto out_ctx;
1019         }
1020
1021         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1022                                 sizeof(*uuari->bitmap),
1023                                 GFP_KERNEL);
1024         if (!uuari->bitmap) {
1025                 err = -ENOMEM;
1026                 goto out_uar_ctx;
1027         }
1028         /*
1029          * clear all fast path uuars
1030          */
1031         for (i = 0; i < gross_uuars; i++) {
1032                 uuarn = i & 3;
1033                 if (uuarn == 2 || uuarn == 3)
1034                         set_bit(i, uuari->bitmap);
1035         }
1036
1037         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1038         if (!uuari->count) {
1039                 err = -ENOMEM;
1040                 goto out_bitmap;
1041         }
1042
1043         for (i = 0; i < num_uars; i++) {
1044                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1045                 if (err)
1046                         goto out_count;
1047         }
1048
1049 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1050         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1051 #endif
1052
1053         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1054                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1055                                                        &context->tdn);
1056                 if (err)
1057                         goto out_uars;
1058         }
1059
1060         INIT_LIST_HEAD(&context->vma_private_list);
1061         INIT_LIST_HEAD(&context->db_page_list);
1062         mutex_init(&context->db_page_mutex);
1063
1064         resp.tot_uuars = req.total_num_uuars;
1065         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1066
1067         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1068                 resp.response_length += sizeof(resp.cqe_version);
1069
1070         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1071                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1072                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1073         }
1074
1075         /*
1076          * We don't want to expose information from the PCI bar that is located
1077          * after 4096 bytes, so if the arch only supports larger pages, let's
1078          * pretend we don't support reading the HCA's core clock. This is also
1079          * forced by mmap function.
1080          */
1081         if (PAGE_SIZE <= 4096 &&
1082             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1083                 resp.comp_mask |=
1084                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1085                 resp.hca_core_clock_offset =
1086                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1087                         PAGE_SIZE;
1088                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1089                                         sizeof(resp.reserved2);
1090         }
1091
1092         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1093         if (err)
1094                 goto out_td;
1095
1096         uuari->ver = ver;
1097         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1098         uuari->uars = uars;
1099         uuari->num_uars = num_uars;
1100         context->cqe_version = resp.cqe_version;
1101
1102         return &context->ibucontext;
1103
1104 out_td:
1105         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1106                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1107
1108 out_uars:
1109         for (i--; i >= 0; i--)
1110                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1111 out_count:
1112         kfree(uuari->count);
1113
1114 out_bitmap:
1115         kfree(uuari->bitmap);
1116
1117 out_uar_ctx:
1118         kfree(uars);
1119
1120 out_ctx:
1121         kfree(context);
1122         return ERR_PTR(err);
1123 }
1124
1125 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1126 {
1127         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1128         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1129         struct mlx5_uuar_info *uuari = &context->uuari;
1130         int i;
1131
1132         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1133                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1134
1135         for (i = 0; i < uuari->num_uars; i++) {
1136                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1137                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1138         }
1139
1140         kfree(uuari->count);
1141         kfree(uuari->bitmap);
1142         kfree(uuari->uars);
1143         kfree(context);
1144
1145         return 0;
1146 }
1147
1148 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1149 {
1150         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1151 }
1152
1153 static int get_command(unsigned long offset)
1154 {
1155         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1156 }
1157
1158 static int get_arg(unsigned long offset)
1159 {
1160         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1161 }
1162
1163 static int get_index(unsigned long offset)
1164 {
1165         return get_arg(offset);
1166 }
1167
1168 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1169 {
1170         /* vma_open is called when a new VMA is created on top of our VMA.  This
1171          * is done through either mremap flow or split_vma (usually due to
1172          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1173          * as this VMA is strongly hardware related.  Therefore we set the
1174          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1175          * calling us again and trying to do incorrect actions.  We assume that
1176          * the original VMA size is exactly a single page, and therefore all
1177          * "splitting" operation will not happen to it.
1178          */
1179         area->vm_ops = NULL;
1180 }
1181
1182 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1183 {
1184         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1185
1186         /* It's guaranteed that all VMAs opened on a FD are closed before the
1187          * file itself is closed, therefore no sync is needed with the regular
1188          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1189          * However need a sync with accessing the vma as part of
1190          * mlx5_ib_disassociate_ucontext.
1191          * The close operation is usually called under mm->mmap_sem except when
1192          * process is exiting.
1193          * The exiting case is handled explicitly as part of
1194          * mlx5_ib_disassociate_ucontext.
1195          */
1196         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1197
1198         /* setting the vma context pointer to null in the mlx5_ib driver's
1199          * private data, to protect a race condition in
1200          * mlx5_ib_disassociate_ucontext().
1201          */
1202         mlx5_ib_vma_priv_data->vma = NULL;
1203         list_del(&mlx5_ib_vma_priv_data->list);
1204         kfree(mlx5_ib_vma_priv_data);
1205 }
1206
1207 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1208         .open = mlx5_ib_vma_open,
1209         .close = mlx5_ib_vma_close
1210 };
1211
1212 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1213                                 struct mlx5_ib_ucontext *ctx)
1214 {
1215         struct mlx5_ib_vma_private_data *vma_prv;
1216         struct list_head *vma_head = &ctx->vma_private_list;
1217
1218         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1219         if (!vma_prv)
1220                 return -ENOMEM;
1221
1222         vma_prv->vma = vma;
1223         vma->vm_private_data = vma_prv;
1224         vma->vm_ops =  &mlx5_ib_vm_ops;
1225
1226         list_add(&vma_prv->list, vma_head);
1227
1228         return 0;
1229 }
1230
1231 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1232 {
1233         int ret;
1234         struct vm_area_struct *vma;
1235         struct mlx5_ib_vma_private_data *vma_private, *n;
1236         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1237         struct task_struct *owning_process  = NULL;
1238         struct mm_struct   *owning_mm       = NULL;
1239
1240         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1241         if (!owning_process)
1242                 return;
1243
1244         owning_mm = get_task_mm(owning_process);
1245         if (!owning_mm) {
1246                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1247                 while (1) {
1248                         put_task_struct(owning_process);
1249                         usleep_range(1000, 2000);
1250                         owning_process = get_pid_task(ibcontext->tgid,
1251                                                       PIDTYPE_PID);
1252                         if (!owning_process ||
1253                             owning_process->state == TASK_DEAD) {
1254                                 pr_info("disassociate ucontext done, task was terminated\n");
1255                                 /* in case task was dead need to release the
1256                                  * task struct.
1257                                  */
1258                                 if (owning_process)
1259                                         put_task_struct(owning_process);
1260                                 return;
1261                         }
1262                 }
1263         }
1264
1265         /* need to protect from a race on closing the vma as part of
1266          * mlx5_ib_vma_close.
1267          */
1268         down_read(&owning_mm->mmap_sem);
1269         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1270                                  list) {
1271                 vma = vma_private->vma;
1272                 ret = zap_vma_ptes(vma, vma->vm_start,
1273                                    PAGE_SIZE);
1274                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1275                 /* context going to be destroyed, should
1276                  * not access ops any more.
1277                  */
1278                 vma->vm_ops = NULL;
1279                 list_del(&vma_private->list);
1280                 kfree(vma_private);
1281         }
1282         up_read(&owning_mm->mmap_sem);
1283         mmput(owning_mm);
1284         put_task_struct(owning_process);
1285 }
1286
1287 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1288 {
1289         switch (cmd) {
1290         case MLX5_IB_MMAP_WC_PAGE:
1291                 return "WC";
1292         case MLX5_IB_MMAP_REGULAR_PAGE:
1293                 return "best effort WC";
1294         case MLX5_IB_MMAP_NC_PAGE:
1295                 return "NC";
1296         default:
1297                 return NULL;
1298         }
1299 }
1300
1301 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1302                     struct vm_area_struct *vma,
1303                     struct mlx5_ib_ucontext *context)
1304 {
1305         struct mlx5_uuar_info *uuari = &context->uuari;
1306         int err;
1307         unsigned long idx;
1308         phys_addr_t pfn, pa;
1309         pgprot_t prot;
1310
1311         switch (cmd) {
1312         case MLX5_IB_MMAP_WC_PAGE:
1313 /* Some architectures don't support WC memory */
1314 #if defined(CONFIG_X86)
1315                 if (!pat_enabled())
1316                         return -EPERM;
1317 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1318                         return -EPERM;
1319 #endif
1320         /* fall through */
1321         case MLX5_IB_MMAP_REGULAR_PAGE:
1322                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1323                 prot = pgprot_writecombine(vma->vm_page_prot);
1324                 break;
1325         case MLX5_IB_MMAP_NC_PAGE:
1326                 prot = pgprot_noncached(vma->vm_page_prot);
1327                 break;
1328         default:
1329                 return -EINVAL;
1330         }
1331
1332         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1333                 return -EINVAL;
1334
1335         idx = get_index(vma->vm_pgoff);
1336         if (idx >= uuari->num_uars)
1337                 return -EINVAL;
1338
1339         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1340         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1341
1342         vma->vm_page_prot = prot;
1343         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1344                                  PAGE_SIZE, vma->vm_page_prot);
1345         if (err) {
1346                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1347                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1348                 return -EAGAIN;
1349         }
1350
1351         pa = pfn << PAGE_SHIFT;
1352         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1353                     vma->vm_start, &pa);
1354
1355         return mlx5_ib_set_vma_data(vma, context);
1356 }
1357
1358 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1359 {
1360         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1361         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1362         unsigned long command;
1363         phys_addr_t pfn;
1364
1365         command = get_command(vma->vm_pgoff);
1366         switch (command) {
1367         case MLX5_IB_MMAP_WC_PAGE:
1368         case MLX5_IB_MMAP_NC_PAGE:
1369         case MLX5_IB_MMAP_REGULAR_PAGE:
1370                 return uar_mmap(dev, command, vma, context);
1371
1372         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1373                 return -ENOSYS;
1374
1375         case MLX5_IB_MMAP_CORE_CLOCK:
1376                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1377                         return -EINVAL;
1378
1379                 if (vma->vm_flags & VM_WRITE)
1380                         return -EPERM;
1381
1382                 /* Don't expose to user-space information it shouldn't have */
1383                 if (PAGE_SIZE > 4096)
1384                         return -EOPNOTSUPP;
1385
1386                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1387                 pfn = (dev->mdev->iseg_base +
1388                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1389                         PAGE_SHIFT;
1390                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1391                                        PAGE_SIZE, vma->vm_page_prot))
1392                         return -EAGAIN;
1393
1394                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1395                             vma->vm_start,
1396                             (unsigned long long)pfn << PAGE_SHIFT);
1397                 break;
1398
1399         default:
1400                 return -EINVAL;
1401         }
1402
1403         return 0;
1404 }
1405
1406 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1407                                       struct ib_ucontext *context,
1408                                       struct ib_udata *udata)
1409 {
1410         struct mlx5_ib_alloc_pd_resp resp;
1411         struct mlx5_ib_pd *pd;
1412         int err;
1413
1414         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1415         if (!pd)
1416                 return ERR_PTR(-ENOMEM);
1417
1418         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1419         if (err) {
1420                 kfree(pd);
1421                 return ERR_PTR(err);
1422         }
1423
1424         if (context) {
1425                 resp.pdn = pd->pdn;
1426                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1427                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1428                         kfree(pd);
1429                         return ERR_PTR(-EFAULT);
1430                 }
1431         }
1432
1433         return &pd->ibpd;
1434 }
1435
1436 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1437 {
1438         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1439         struct mlx5_ib_pd *mpd = to_mpd(pd);
1440
1441         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1442         kfree(mpd);
1443
1444         return 0;
1445 }
1446
1447 enum {
1448         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1449         MATCH_CRITERIA_ENABLE_MISC_BIT,
1450         MATCH_CRITERIA_ENABLE_INNER_BIT
1451 };
1452
1453 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1454         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1455                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1456
1457 static u8 get_match_criteria_enable(u32 *match_criteria)
1458 {
1459         u8 match_criteria_enable;
1460
1461         match_criteria_enable =
1462                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1463                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1464         match_criteria_enable |=
1465                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1466                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1467         match_criteria_enable |=
1468                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1469                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1470
1471         return match_criteria_enable;
1472 }
1473
1474 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1475 {
1476         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1477         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1478 }
1479
1480 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1481 {
1482         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1483         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1484         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1485         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1486 }
1487
1488 #define LAST_ETH_FIELD vlan_tag
1489 #define LAST_IB_FIELD sl
1490 #define LAST_IPV4_FIELD tos
1491 #define LAST_IPV6_FIELD traffic_class
1492 #define LAST_TCP_UDP_FIELD src_port
1493
1494 /* Field is the last supported field */
1495 #define FIELDS_NOT_SUPPORTED(filter, field)\
1496         memchr_inv((void *)&filter.field  +\
1497                    sizeof(filter.field), 0,\
1498                    sizeof(filter) -\
1499                    offsetof(typeof(filter), field) -\
1500                    sizeof(filter.field))
1501
1502 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1503                            const union ib_flow_spec *ib_spec)
1504 {
1505         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1506                                              outer_headers);
1507         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1508                                              outer_headers);
1509         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1510                                            misc_parameters);
1511         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1512                                            misc_parameters);
1513
1514         switch (ib_spec->type) {
1515         case IB_FLOW_SPEC_ETH:
1516                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1517                         return -ENOTSUPP;
1518
1519                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1520                                              dmac_47_16),
1521                                 ib_spec->eth.mask.dst_mac);
1522                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1523                                              dmac_47_16),
1524                                 ib_spec->eth.val.dst_mac);
1525
1526                 if (ib_spec->eth.mask.vlan_tag) {
1527                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1528                                  vlan_tag, 1);
1529                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1530                                  vlan_tag, 1);
1531
1532                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1533                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1534                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1535                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1536
1537                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1538                                  first_cfi,
1539                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1540                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1541                                  first_cfi,
1542                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1543
1544                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1545                                  first_prio,
1546                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1547                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1548                                  first_prio,
1549                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1550                 }
1551                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1552                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1553                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1554                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1555                 break;
1556         case IB_FLOW_SPEC_IPV4:
1557                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1558                         return -ENOTSUPP;
1559
1560                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1561                          ethertype, 0xffff);
1562                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1563                          ethertype, ETH_P_IP);
1564
1565                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1566                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1567                        &ib_spec->ipv4.mask.src_ip,
1568                        sizeof(ib_spec->ipv4.mask.src_ip));
1569                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1570                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1571                        &ib_spec->ipv4.val.src_ip,
1572                        sizeof(ib_spec->ipv4.val.src_ip));
1573                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1574                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1575                        &ib_spec->ipv4.mask.dst_ip,
1576                        sizeof(ib_spec->ipv4.mask.dst_ip));
1577                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1578                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1579                        &ib_spec->ipv4.val.dst_ip,
1580                        sizeof(ib_spec->ipv4.val.dst_ip));
1581
1582                 set_tos(outer_headers_c, outer_headers_v,
1583                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1584
1585                 set_proto(outer_headers_c, outer_headers_v,
1586                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1587                 break;
1588         case IB_FLOW_SPEC_IPV6:
1589                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1590                         return -ENOTSUPP;
1591
1592                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1593                          ethertype, 0xffff);
1594                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1595                          ethertype, ETH_P_IPV6);
1596
1597                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1598                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1599                        &ib_spec->ipv6.mask.src_ip,
1600                        sizeof(ib_spec->ipv6.mask.src_ip));
1601                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1602                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1603                        &ib_spec->ipv6.val.src_ip,
1604                        sizeof(ib_spec->ipv6.val.src_ip));
1605                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1606                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1607                        &ib_spec->ipv6.mask.dst_ip,
1608                        sizeof(ib_spec->ipv6.mask.dst_ip));
1609                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1610                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1611                        &ib_spec->ipv6.val.dst_ip,
1612                        sizeof(ib_spec->ipv6.val.dst_ip));
1613
1614                 set_tos(outer_headers_c, outer_headers_v,
1615                         ib_spec->ipv6.mask.traffic_class,
1616                         ib_spec->ipv6.val.traffic_class);
1617
1618                 set_proto(outer_headers_c, outer_headers_v,
1619                           ib_spec->ipv6.mask.next_hdr,
1620                           ib_spec->ipv6.val.next_hdr);
1621
1622                 MLX5_SET(fte_match_set_misc, misc_params_c,
1623                          outer_ipv6_flow_label,
1624                          ntohl(ib_spec->ipv6.mask.flow_label));
1625                 MLX5_SET(fte_match_set_misc, misc_params_v,
1626                          outer_ipv6_flow_label,
1627                          ntohl(ib_spec->ipv6.val.flow_label));
1628                 break;
1629         case IB_FLOW_SPEC_TCP:
1630                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1631                                          LAST_TCP_UDP_FIELD))
1632                         return -ENOTSUPP;
1633
1634                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1635                          0xff);
1636                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1637                          IPPROTO_TCP);
1638
1639                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1640                          ntohs(ib_spec->tcp_udp.mask.src_port));
1641                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1642                          ntohs(ib_spec->tcp_udp.val.src_port));
1643
1644                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1645                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1646                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1647                          ntohs(ib_spec->tcp_udp.val.dst_port));
1648                 break;
1649         case IB_FLOW_SPEC_UDP:
1650                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1651                                          LAST_TCP_UDP_FIELD))
1652                         return -ENOTSUPP;
1653
1654                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1655                          0xff);
1656                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1657                          IPPROTO_UDP);
1658
1659                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1660                          ntohs(ib_spec->tcp_udp.mask.src_port));
1661                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1662                          ntohs(ib_spec->tcp_udp.val.src_port));
1663
1664                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1665                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1666                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1667                          ntohs(ib_spec->tcp_udp.val.dst_port));
1668                 break;
1669         default:
1670                 return -EINVAL;
1671         }
1672
1673         return 0;
1674 }
1675
1676 /* If a flow could catch both multicast and unicast packets,
1677  * it won't fall into the multicast flow steering table and this rule
1678  * could steal other multicast packets.
1679  */
1680 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1681 {
1682         struct ib_flow_spec_eth *eth_spec;
1683
1684         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1685             ib_attr->size < sizeof(struct ib_flow_attr) +
1686             sizeof(struct ib_flow_spec_eth) ||
1687             ib_attr->num_of_specs < 1)
1688                 return false;
1689
1690         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1691         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1692             eth_spec->size != sizeof(*eth_spec))
1693                 return false;
1694
1695         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1696                is_multicast_ether_addr(eth_spec->val.dst_mac);
1697 }
1698
1699 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1700 {
1701         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1702         bool has_ipv4_spec = false;
1703         bool eth_type_ipv4 = true;
1704         unsigned int spec_index;
1705
1706         /* Validate that ethertype is correct */
1707         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1708                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1709                     ib_spec->eth.mask.ether_type) {
1710                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1711                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1712                                 eth_type_ipv4 = false;
1713                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1714                         has_ipv4_spec = true;
1715                 }
1716                 ib_spec = (void *)ib_spec + ib_spec->size;
1717         }
1718         return !has_ipv4_spec || eth_type_ipv4;
1719 }
1720
1721 static void put_flow_table(struct mlx5_ib_dev *dev,
1722                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1723 {
1724         prio->refcount -= !!ft_added;
1725         if (!prio->refcount) {
1726                 mlx5_destroy_flow_table(prio->flow_table);
1727                 prio->flow_table = NULL;
1728         }
1729 }
1730
1731 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1732 {
1733         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1734         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1735                                                           struct mlx5_ib_flow_handler,
1736                                                           ibflow);
1737         struct mlx5_ib_flow_handler *iter, *tmp;
1738
1739         mutex_lock(&dev->flow_db.lock);
1740
1741         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1742                 mlx5_del_flow_rule(iter->rule);
1743                 put_flow_table(dev, iter->prio, true);
1744                 list_del(&iter->list);
1745                 kfree(iter);
1746         }
1747
1748         mlx5_del_flow_rule(handler->rule);
1749         put_flow_table(dev, handler->prio, true);
1750         mutex_unlock(&dev->flow_db.lock);
1751
1752         kfree(handler);
1753
1754         return 0;
1755 }
1756
1757 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1758 {
1759         priority *= 2;
1760         if (!dont_trap)
1761                 priority++;
1762         return priority;
1763 }
1764
1765 enum flow_table_type {
1766         MLX5_IB_FT_RX,
1767         MLX5_IB_FT_TX
1768 };
1769
1770 #define MLX5_FS_MAX_TYPES        10
1771 #define MLX5_FS_MAX_ENTRIES      32000UL
1772 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1773                                                 struct ib_flow_attr *flow_attr,
1774                                                 enum flow_table_type ft_type)
1775 {
1776         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1777         struct mlx5_flow_namespace *ns = NULL;
1778         struct mlx5_ib_flow_prio *prio;
1779         struct mlx5_flow_table *ft;
1780         int num_entries;
1781         int num_groups;
1782         int priority;
1783         int err = 0;
1784
1785         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1786                 if (flow_is_multicast_only(flow_attr) &&
1787                     !dont_trap)
1788                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1789                 else
1790                         priority = ib_prio_to_core_prio(flow_attr->priority,
1791                                                         dont_trap);
1792                 ns = mlx5_get_flow_namespace(dev->mdev,
1793                                              MLX5_FLOW_NAMESPACE_BYPASS);
1794                 num_entries = MLX5_FS_MAX_ENTRIES;
1795                 num_groups = MLX5_FS_MAX_TYPES;
1796                 prio = &dev->flow_db.prios[priority];
1797         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1798                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1799                 ns = mlx5_get_flow_namespace(dev->mdev,
1800                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1801                 build_leftovers_ft_param(&priority,
1802                                          &num_entries,
1803                                          &num_groups);
1804                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1805         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1806                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1807                                         allow_sniffer_and_nic_rx_shared_tir))
1808                         return ERR_PTR(-ENOTSUPP);
1809
1810                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1811                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1812                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1813
1814                 prio = &dev->flow_db.sniffer[ft_type];
1815                 priority = 0;
1816                 num_entries = 1;
1817                 num_groups = 1;
1818         }
1819
1820         if (!ns)
1821                 return ERR_PTR(-ENOTSUPP);
1822
1823         ft = prio->flow_table;
1824         if (!ft) {
1825                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1826                                                          num_entries,
1827                                                          num_groups,
1828                                                          0);
1829
1830                 if (!IS_ERR(ft)) {
1831                         prio->refcount = 0;
1832                         prio->flow_table = ft;
1833                 } else {
1834                         err = PTR_ERR(ft);
1835                 }
1836         }
1837
1838         return err ? ERR_PTR(err) : prio;
1839 }
1840
1841 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1842                                                      struct mlx5_ib_flow_prio *ft_prio,
1843                                                      const struct ib_flow_attr *flow_attr,
1844                                                      struct mlx5_flow_destination *dst)
1845 {
1846         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1847         struct mlx5_ib_flow_handler *handler;
1848         struct mlx5_flow_spec *spec;
1849         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1850         unsigned int spec_index;
1851         u32 action;
1852         int err = 0;
1853
1854         if (!is_valid_attr(flow_attr))
1855                 return ERR_PTR(-EINVAL);
1856
1857         spec = mlx5_vzalloc(sizeof(*spec));
1858         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1859         if (!handler || !spec) {
1860                 err = -ENOMEM;
1861                 goto free;
1862         }
1863
1864         INIT_LIST_HEAD(&handler->list);
1865
1866         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1867                 err = parse_flow_attr(spec->match_criteria,
1868                                       spec->match_value, ib_flow);
1869                 if (err < 0)
1870                         goto free;
1871
1872                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1873         }
1874
1875         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1876         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1877                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1878         handler->rule = mlx5_add_flow_rule(ft, spec,
1879                                            action,
1880                                            MLX5_FS_DEFAULT_FLOW_TAG,
1881                                            dst);
1882
1883         if (IS_ERR(handler->rule)) {
1884                 err = PTR_ERR(handler->rule);
1885                 goto free;
1886         }
1887
1888         ft_prio->refcount++;
1889         handler->prio = ft_prio;
1890
1891         ft_prio->flow_table = ft;
1892 free:
1893         if (err)
1894                 kfree(handler);
1895         kvfree(spec);
1896         return err ? ERR_PTR(err) : handler;
1897 }
1898
1899 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1900                                                           struct mlx5_ib_flow_prio *ft_prio,
1901                                                           struct ib_flow_attr *flow_attr,
1902                                                           struct mlx5_flow_destination *dst)
1903 {
1904         struct mlx5_ib_flow_handler *handler_dst = NULL;
1905         struct mlx5_ib_flow_handler *handler = NULL;
1906
1907         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1908         if (!IS_ERR(handler)) {
1909                 handler_dst = create_flow_rule(dev, ft_prio,
1910                                                flow_attr, dst);
1911                 if (IS_ERR(handler_dst)) {
1912                         mlx5_del_flow_rule(handler->rule);
1913                         ft_prio->refcount--;
1914                         kfree(handler);
1915                         handler = handler_dst;
1916                 } else {
1917                         list_add(&handler_dst->list, &handler->list);
1918                 }
1919         }
1920
1921         return handler;
1922 }
1923 enum {
1924         LEFTOVERS_MC,
1925         LEFTOVERS_UC,
1926 };
1927
1928 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1929                                                           struct mlx5_ib_flow_prio *ft_prio,
1930                                                           struct ib_flow_attr *flow_attr,
1931                                                           struct mlx5_flow_destination *dst)
1932 {
1933         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1934         struct mlx5_ib_flow_handler *handler = NULL;
1935
1936         static struct {
1937                 struct ib_flow_attr     flow_attr;
1938                 struct ib_flow_spec_eth eth_flow;
1939         } leftovers_specs[] = {
1940                 [LEFTOVERS_MC] = {
1941                         .flow_attr = {
1942                                 .num_of_specs = 1,
1943                                 .size = sizeof(leftovers_specs[0])
1944                         },
1945                         .eth_flow = {
1946                                 .type = IB_FLOW_SPEC_ETH,
1947                                 .size = sizeof(struct ib_flow_spec_eth),
1948                                 .mask = {.dst_mac = {0x1} },
1949                                 .val =  {.dst_mac = {0x1} }
1950                         }
1951                 },
1952                 [LEFTOVERS_UC] = {
1953                         .flow_attr = {
1954                                 .num_of_specs = 1,
1955                                 .size = sizeof(leftovers_specs[0])
1956                         },
1957                         .eth_flow = {
1958                                 .type = IB_FLOW_SPEC_ETH,
1959                                 .size = sizeof(struct ib_flow_spec_eth),
1960                                 .mask = {.dst_mac = {0x1} },
1961                                 .val = {.dst_mac = {} }
1962                         }
1963                 }
1964         };
1965
1966         handler = create_flow_rule(dev, ft_prio,
1967                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1968                                    dst);
1969         if (!IS_ERR(handler) &&
1970             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1971                 handler_ucast = create_flow_rule(dev, ft_prio,
1972                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1973                                                  dst);
1974                 if (IS_ERR(handler_ucast)) {
1975                         mlx5_del_flow_rule(handler->rule);
1976                         ft_prio->refcount--;
1977                         kfree(handler);
1978                         handler = handler_ucast;
1979                 } else {
1980                         list_add(&handler_ucast->list, &handler->list);
1981                 }
1982         }
1983
1984         return handler;
1985 }
1986
1987 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
1988                                                         struct mlx5_ib_flow_prio *ft_rx,
1989                                                         struct mlx5_ib_flow_prio *ft_tx,
1990                                                         struct mlx5_flow_destination *dst)
1991 {
1992         struct mlx5_ib_flow_handler *handler_rx;
1993         struct mlx5_ib_flow_handler *handler_tx;
1994         int err;
1995         static const struct ib_flow_attr flow_attr  = {
1996                 .num_of_specs = 0,
1997                 .size = sizeof(flow_attr)
1998         };
1999
2000         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2001         if (IS_ERR(handler_rx)) {
2002                 err = PTR_ERR(handler_rx);
2003                 goto err;
2004         }
2005
2006         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2007         if (IS_ERR(handler_tx)) {
2008                 err = PTR_ERR(handler_tx);
2009                 goto err_tx;
2010         }
2011
2012         list_add(&handler_tx->list, &handler_rx->list);
2013
2014         return handler_rx;
2015
2016 err_tx:
2017         mlx5_del_flow_rule(handler_rx->rule);
2018         ft_rx->refcount--;
2019         kfree(handler_rx);
2020 err:
2021         return ERR_PTR(err);
2022 }
2023
2024 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2025                                            struct ib_flow_attr *flow_attr,
2026                                            int domain)
2027 {
2028         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2029         struct mlx5_ib_flow_handler *handler = NULL;
2030         struct mlx5_flow_destination *dst = NULL;
2031         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2032         struct mlx5_ib_flow_prio *ft_prio;
2033         int err;
2034
2035         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2036                 return ERR_PTR(-ENOSPC);
2037
2038         if (domain != IB_FLOW_DOMAIN_USER ||
2039             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2040             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2041                 return ERR_PTR(-EINVAL);
2042
2043         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2044         if (!dst)
2045                 return ERR_PTR(-ENOMEM);
2046
2047         mutex_lock(&dev->flow_db.lock);
2048
2049         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2050         if (IS_ERR(ft_prio)) {
2051                 err = PTR_ERR(ft_prio);
2052                 goto unlock;
2053         }
2054         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2055                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2056                 if (IS_ERR(ft_prio_tx)) {
2057                         err = PTR_ERR(ft_prio_tx);
2058                         ft_prio_tx = NULL;
2059                         goto destroy_ft;
2060                 }
2061         }
2062
2063         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2064         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
2065
2066         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2067                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2068                         handler = create_dont_trap_rule(dev, ft_prio,
2069                                                         flow_attr, dst);
2070                 } else {
2071                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2072                                                    dst);
2073                 }
2074         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2075                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2076                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2077                                                 dst);
2078         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2079                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2080         } else {
2081                 err = -EINVAL;
2082                 goto destroy_ft;
2083         }
2084
2085         if (IS_ERR(handler)) {
2086                 err = PTR_ERR(handler);
2087                 handler = NULL;
2088                 goto destroy_ft;
2089         }
2090
2091         mutex_unlock(&dev->flow_db.lock);
2092         kfree(dst);
2093
2094         return &handler->ibflow;
2095
2096 destroy_ft:
2097         put_flow_table(dev, ft_prio, false);
2098         if (ft_prio_tx)
2099                 put_flow_table(dev, ft_prio_tx, false);
2100 unlock:
2101         mutex_unlock(&dev->flow_db.lock);
2102         kfree(dst);
2103         kfree(handler);
2104         return ERR_PTR(err);
2105 }
2106
2107 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2108 {
2109         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2110         int err;
2111
2112         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2113         if (err)
2114                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2115                              ibqp->qp_num, gid->raw);
2116
2117         return err;
2118 }
2119
2120 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2121 {
2122         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2123         int err;
2124
2125         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2126         if (err)
2127                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2128                              ibqp->qp_num, gid->raw);
2129
2130         return err;
2131 }
2132
2133 static int init_node_data(struct mlx5_ib_dev *dev)
2134 {
2135         int err;
2136
2137         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2138         if (err)
2139                 return err;
2140
2141         dev->mdev->rev_id = dev->mdev->pdev->revision;
2142
2143         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2144 }
2145
2146 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2147                              char *buf)
2148 {
2149         struct mlx5_ib_dev *dev =
2150                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2151
2152         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2153 }
2154
2155 static ssize_t show_reg_pages(struct device *device,
2156                               struct device_attribute *attr, char *buf)
2157 {
2158         struct mlx5_ib_dev *dev =
2159                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2160
2161         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2162 }
2163
2164 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2165                         char *buf)
2166 {
2167         struct mlx5_ib_dev *dev =
2168                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2169         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2170 }
2171
2172 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2173                         char *buf)
2174 {
2175         struct mlx5_ib_dev *dev =
2176                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2177         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2178 }
2179
2180 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2181                           char *buf)
2182 {
2183         struct mlx5_ib_dev *dev =
2184                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2185         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2186                        dev->mdev->board_id);
2187 }
2188
2189 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2190 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2191 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2192 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2193 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2194
2195 static struct device_attribute *mlx5_class_attributes[] = {
2196         &dev_attr_hw_rev,
2197         &dev_attr_hca_type,
2198         &dev_attr_board_id,
2199         &dev_attr_fw_pages,
2200         &dev_attr_reg_pages,
2201 };
2202
2203 static void pkey_change_handler(struct work_struct *work)
2204 {
2205         struct mlx5_ib_port_resources *ports =
2206                 container_of(work, struct mlx5_ib_port_resources,
2207                              pkey_change_work);
2208
2209         mutex_lock(&ports->devr->mutex);
2210         mlx5_ib_gsi_pkey_change(ports->gsi);
2211         mutex_unlock(&ports->devr->mutex);
2212 }
2213
2214 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2215 {
2216         struct mlx5_ib_qp *mqp;
2217         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2218         struct mlx5_core_cq *mcq;
2219         struct list_head cq_armed_list;
2220         unsigned long flags_qp;
2221         unsigned long flags_cq;
2222         unsigned long flags;
2223
2224         INIT_LIST_HEAD(&cq_armed_list);
2225
2226         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2227         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2228         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2229                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2230                 if (mqp->sq.tail != mqp->sq.head) {
2231                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2232                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2233                         if (send_mcq->mcq.comp &&
2234                             mqp->ibqp.send_cq->comp_handler) {
2235                                 if (!send_mcq->mcq.reset_notify_added) {
2236                                         send_mcq->mcq.reset_notify_added = 1;
2237                                         list_add_tail(&send_mcq->mcq.reset_notify,
2238                                                       &cq_armed_list);
2239                                 }
2240                         }
2241                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2242                 }
2243                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2244                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2245                 /* no handling is needed for SRQ */
2246                 if (!mqp->ibqp.srq) {
2247                         if (mqp->rq.tail != mqp->rq.head) {
2248                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2249                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2250                                 if (recv_mcq->mcq.comp &&
2251                                     mqp->ibqp.recv_cq->comp_handler) {
2252                                         if (!recv_mcq->mcq.reset_notify_added) {
2253                                                 recv_mcq->mcq.reset_notify_added = 1;
2254                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2255                                                               &cq_armed_list);
2256                                         }
2257                                 }
2258                                 spin_unlock_irqrestore(&recv_mcq->lock,
2259                                                        flags_cq);
2260                         }
2261                 }
2262                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2263         }
2264         /*At that point all inflight post send were put to be executed as of we
2265          * lock/unlock above locks Now need to arm all involved CQs.
2266          */
2267         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2268                 mcq->comp(mcq);
2269         }
2270         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2271 }
2272
2273 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2274                           enum mlx5_dev_event event, unsigned long param)
2275 {
2276         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2277         struct ib_event ibev;
2278
2279         u8 port = 0;
2280
2281         switch (event) {
2282         case MLX5_DEV_EVENT_SYS_ERROR:
2283                 ibdev->ib_active = false;
2284                 ibev.event = IB_EVENT_DEVICE_FATAL;
2285                 mlx5_ib_handle_internal_error(ibdev);
2286                 break;
2287
2288         case MLX5_DEV_EVENT_PORT_UP:
2289         case MLX5_DEV_EVENT_PORT_DOWN:
2290         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2291                 port = (u8)param;
2292
2293                 /* In RoCE, port up/down events are handled in
2294                  * mlx5_netdev_event().
2295                  */
2296                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2297                         IB_LINK_LAYER_ETHERNET)
2298                         return;
2299
2300                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2301                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2302                 break;
2303
2304         case MLX5_DEV_EVENT_LID_CHANGE:
2305                 ibev.event = IB_EVENT_LID_CHANGE;
2306                 port = (u8)param;
2307                 break;
2308
2309         case MLX5_DEV_EVENT_PKEY_CHANGE:
2310                 ibev.event = IB_EVENT_PKEY_CHANGE;
2311                 port = (u8)param;
2312
2313                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2314                 break;
2315
2316         case MLX5_DEV_EVENT_GUID_CHANGE:
2317                 ibev.event = IB_EVENT_GID_CHANGE;
2318                 port = (u8)param;
2319                 break;
2320
2321         case MLX5_DEV_EVENT_CLIENT_REREG:
2322                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2323                 port = (u8)param;
2324                 break;
2325         }
2326
2327         ibev.device           = &ibdev->ib_dev;
2328         ibev.element.port_num = port;
2329
2330         if (port < 1 || port > ibdev->num_ports) {
2331                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2332                 return;
2333         }
2334
2335         if (ibdev->ib_active)
2336                 ib_dispatch_event(&ibev);
2337 }
2338
2339 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2340 {
2341         int port;
2342
2343         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2344                 mlx5_query_ext_port_caps(dev, port);
2345 }
2346
2347 static int get_port_caps(struct mlx5_ib_dev *dev)
2348 {
2349         struct ib_device_attr *dprops = NULL;
2350         struct ib_port_attr *pprops = NULL;
2351         int err = -ENOMEM;
2352         int port;
2353         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2354
2355         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2356         if (!pprops)
2357                 goto out;
2358
2359         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2360         if (!dprops)
2361                 goto out;
2362
2363         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2364         if (err) {
2365                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2366                 goto out;
2367         }
2368
2369         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2370                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2371                 if (err) {
2372                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2373                                      port, err);
2374                         break;
2375                 }
2376                 dev->mdev->port_caps[port - 1].pkey_table_len =
2377                                                 dprops->max_pkeys;
2378                 dev->mdev->port_caps[port - 1].gid_table_len =
2379                                                 pprops->gid_tbl_len;
2380                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2381                             dprops->max_pkeys, pprops->gid_tbl_len);
2382         }
2383
2384 out:
2385         kfree(pprops);
2386         kfree(dprops);
2387
2388         return err;
2389 }
2390
2391 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2392 {
2393         int err;
2394
2395         err = mlx5_mr_cache_cleanup(dev);
2396         if (err)
2397                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2398
2399         mlx5_ib_destroy_qp(dev->umrc.qp);
2400         ib_free_cq(dev->umrc.cq);
2401         ib_dealloc_pd(dev->umrc.pd);
2402 }
2403
2404 enum {
2405         MAX_UMR_WR = 128,
2406 };
2407
2408 static int create_umr_res(struct mlx5_ib_dev *dev)
2409 {
2410         struct ib_qp_init_attr *init_attr = NULL;
2411         struct ib_qp_attr *attr = NULL;
2412         struct ib_pd *pd;
2413         struct ib_cq *cq;
2414         struct ib_qp *qp;
2415         int ret;
2416
2417         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2418         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2419         if (!attr || !init_attr) {
2420                 ret = -ENOMEM;
2421                 goto error_0;
2422         }
2423
2424         pd = ib_alloc_pd(&dev->ib_dev, 0);
2425         if (IS_ERR(pd)) {
2426                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2427                 ret = PTR_ERR(pd);
2428                 goto error_0;
2429         }
2430
2431         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2432         if (IS_ERR(cq)) {
2433                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2434                 ret = PTR_ERR(cq);
2435                 goto error_2;
2436         }
2437
2438         init_attr->send_cq = cq;
2439         init_attr->recv_cq = cq;
2440         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2441         init_attr->cap.max_send_wr = MAX_UMR_WR;
2442         init_attr->cap.max_send_sge = 1;
2443         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2444         init_attr->port_num = 1;
2445         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2446         if (IS_ERR(qp)) {
2447                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2448                 ret = PTR_ERR(qp);
2449                 goto error_3;
2450         }
2451         qp->device     = &dev->ib_dev;
2452         qp->real_qp    = qp;
2453         qp->uobject    = NULL;
2454         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2455
2456         attr->qp_state = IB_QPS_INIT;
2457         attr->port_num = 1;
2458         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2459                                 IB_QP_PORT, NULL);
2460         if (ret) {
2461                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2462                 goto error_4;
2463         }
2464
2465         memset(attr, 0, sizeof(*attr));
2466         attr->qp_state = IB_QPS_RTR;
2467         attr->path_mtu = IB_MTU_256;
2468
2469         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2470         if (ret) {
2471                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2472                 goto error_4;
2473         }
2474
2475         memset(attr, 0, sizeof(*attr));
2476         attr->qp_state = IB_QPS_RTS;
2477         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2478         if (ret) {
2479                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2480                 goto error_4;
2481         }
2482
2483         dev->umrc.qp = qp;
2484         dev->umrc.cq = cq;
2485         dev->umrc.pd = pd;
2486
2487         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2488         ret = mlx5_mr_cache_init(dev);
2489         if (ret) {
2490                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2491                 goto error_4;
2492         }
2493
2494         kfree(attr);
2495         kfree(init_attr);
2496
2497         return 0;
2498
2499 error_4:
2500         mlx5_ib_destroy_qp(qp);
2501
2502 error_3:
2503         ib_free_cq(cq);
2504
2505 error_2:
2506         ib_dealloc_pd(pd);
2507
2508 error_0:
2509         kfree(attr);
2510         kfree(init_attr);
2511         return ret;
2512 }
2513
2514 static int create_dev_resources(struct mlx5_ib_resources *devr)
2515 {
2516         struct ib_srq_init_attr attr;
2517         struct mlx5_ib_dev *dev;
2518         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2519         int port;
2520         int ret = 0;
2521
2522         dev = container_of(devr, struct mlx5_ib_dev, devr);
2523
2524         mutex_init(&devr->mutex);
2525
2526         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2527         if (IS_ERR(devr->p0)) {
2528                 ret = PTR_ERR(devr->p0);
2529                 goto error0;
2530         }
2531         devr->p0->device  = &dev->ib_dev;
2532         devr->p0->uobject = NULL;
2533         atomic_set(&devr->p0->usecnt, 0);
2534
2535         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2536         if (IS_ERR(devr->c0)) {
2537                 ret = PTR_ERR(devr->c0);
2538                 goto error1;
2539         }
2540         devr->c0->device        = &dev->ib_dev;
2541         devr->c0->uobject       = NULL;
2542         devr->c0->comp_handler  = NULL;
2543         devr->c0->event_handler = NULL;
2544         devr->c0->cq_context    = NULL;
2545         atomic_set(&devr->c0->usecnt, 0);
2546
2547         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2548         if (IS_ERR(devr->x0)) {
2549                 ret = PTR_ERR(devr->x0);
2550                 goto error2;
2551         }
2552         devr->x0->device = &dev->ib_dev;
2553         devr->x0->inode = NULL;
2554         atomic_set(&devr->x0->usecnt, 0);
2555         mutex_init(&devr->x0->tgt_qp_mutex);
2556         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2557
2558         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2559         if (IS_ERR(devr->x1)) {
2560                 ret = PTR_ERR(devr->x1);
2561                 goto error3;
2562         }
2563         devr->x1->device = &dev->ib_dev;
2564         devr->x1->inode = NULL;
2565         atomic_set(&devr->x1->usecnt, 0);
2566         mutex_init(&devr->x1->tgt_qp_mutex);
2567         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2568
2569         memset(&attr, 0, sizeof(attr));
2570         attr.attr.max_sge = 1;
2571         attr.attr.max_wr = 1;
2572         attr.srq_type = IB_SRQT_XRC;
2573         attr.ext.xrc.cq = devr->c0;
2574         attr.ext.xrc.xrcd = devr->x0;
2575
2576         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2577         if (IS_ERR(devr->s0)) {
2578                 ret = PTR_ERR(devr->s0);
2579                 goto error4;
2580         }
2581         devr->s0->device        = &dev->ib_dev;
2582         devr->s0->pd            = devr->p0;
2583         devr->s0->uobject       = NULL;
2584         devr->s0->event_handler = NULL;
2585         devr->s0->srq_context   = NULL;
2586         devr->s0->srq_type      = IB_SRQT_XRC;
2587         devr->s0->ext.xrc.xrcd  = devr->x0;
2588         devr->s0->ext.xrc.cq    = devr->c0;
2589         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2590         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2591         atomic_inc(&devr->p0->usecnt);
2592         atomic_set(&devr->s0->usecnt, 0);
2593
2594         memset(&attr, 0, sizeof(attr));
2595         attr.attr.max_sge = 1;
2596         attr.attr.max_wr = 1;
2597         attr.srq_type = IB_SRQT_BASIC;
2598         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2599         if (IS_ERR(devr->s1)) {
2600                 ret = PTR_ERR(devr->s1);
2601                 goto error5;
2602         }
2603         devr->s1->device        = &dev->ib_dev;
2604         devr->s1->pd            = devr->p0;
2605         devr->s1->uobject       = NULL;
2606         devr->s1->event_handler = NULL;
2607         devr->s1->srq_context   = NULL;
2608         devr->s1->srq_type      = IB_SRQT_BASIC;
2609         devr->s1->ext.xrc.cq    = devr->c0;
2610         atomic_inc(&devr->p0->usecnt);
2611         atomic_set(&devr->s0->usecnt, 0);
2612
2613         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2614                 INIT_WORK(&devr->ports[port].pkey_change_work,
2615                           pkey_change_handler);
2616                 devr->ports[port].devr = devr;
2617         }
2618
2619         return 0;
2620
2621 error5:
2622         mlx5_ib_destroy_srq(devr->s0);
2623 error4:
2624         mlx5_ib_dealloc_xrcd(devr->x1);
2625 error3:
2626         mlx5_ib_dealloc_xrcd(devr->x0);
2627 error2:
2628         mlx5_ib_destroy_cq(devr->c0);
2629 error1:
2630         mlx5_ib_dealloc_pd(devr->p0);
2631 error0:
2632         return ret;
2633 }
2634
2635 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2636 {
2637         struct mlx5_ib_dev *dev =
2638                 container_of(devr, struct mlx5_ib_dev, devr);
2639         int port;
2640
2641         mlx5_ib_destroy_srq(devr->s1);
2642         mlx5_ib_destroy_srq(devr->s0);
2643         mlx5_ib_dealloc_xrcd(devr->x0);
2644         mlx5_ib_dealloc_xrcd(devr->x1);
2645         mlx5_ib_destroy_cq(devr->c0);
2646         mlx5_ib_dealloc_pd(devr->p0);
2647
2648         /* Make sure no change P_Key work items are still executing */
2649         for (port = 0; port < dev->num_ports; ++port)
2650                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2651 }
2652
2653 static u32 get_core_cap_flags(struct ib_device *ibdev)
2654 {
2655         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2656         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2657         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2658         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2659         u32 ret = 0;
2660
2661         if (ll == IB_LINK_LAYER_INFINIBAND)
2662                 return RDMA_CORE_PORT_IBA_IB;
2663
2664         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2665                 return 0;
2666
2667         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2668                 return 0;
2669
2670         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2671                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2672
2673         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2674                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2675
2676         return ret;
2677 }
2678
2679 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2680                                struct ib_port_immutable *immutable)
2681 {
2682         struct ib_port_attr attr;
2683         int err;
2684
2685         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2686         if (err)
2687                 return err;
2688
2689         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2690         immutable->gid_tbl_len = attr.gid_tbl_len;
2691         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2692         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2693
2694         return 0;
2695 }
2696
2697 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2698                            size_t str_len)
2699 {
2700         struct mlx5_ib_dev *dev =
2701                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2702         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2703                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2704 }
2705
2706 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2707 {
2708         struct mlx5_core_dev *mdev = dev->mdev;
2709         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2710                                                                  MLX5_FLOW_NAMESPACE_LAG);
2711         struct mlx5_flow_table *ft;
2712         int err;
2713
2714         if (!ns || !mlx5_lag_is_active(mdev))
2715                 return 0;
2716
2717         err = mlx5_cmd_create_vport_lag(mdev);
2718         if (err)
2719                 return err;
2720
2721         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2722         if (IS_ERR(ft)) {
2723                 err = PTR_ERR(ft);
2724                 goto err_destroy_vport_lag;
2725         }
2726
2727         dev->flow_db.lag_demux_ft = ft;
2728         return 0;
2729
2730 err_destroy_vport_lag:
2731         mlx5_cmd_destroy_vport_lag(mdev);
2732         return err;
2733 }
2734
2735 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2736 {
2737         struct mlx5_core_dev *mdev = dev->mdev;
2738
2739         if (dev->flow_db.lag_demux_ft) {
2740                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2741                 dev->flow_db.lag_demux_ft = NULL;
2742
2743                 mlx5_cmd_destroy_vport_lag(mdev);
2744         }
2745 }
2746
2747 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2748 {
2749         if (dev->roce.nb.notifier_call) {
2750                 unregister_netdevice_notifier(&dev->roce.nb);
2751                 dev->roce.nb.notifier_call = NULL;
2752         }
2753 }
2754
2755 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2756 {
2757         int err;
2758
2759         dev->roce.nb.notifier_call = mlx5_netdev_event;
2760         err = register_netdevice_notifier(&dev->roce.nb);
2761         if (err) {
2762                 dev->roce.nb.notifier_call = NULL;
2763                 return err;
2764         }
2765
2766         err = mlx5_nic_vport_enable_roce(dev->mdev);
2767         if (err)
2768                 goto err_unregister_netdevice_notifier;
2769
2770         err = mlx5_roce_lag_init(dev);
2771         if (err)
2772                 goto err_disable_roce;
2773
2774         return 0;
2775
2776 err_disable_roce:
2777         mlx5_nic_vport_disable_roce(dev->mdev);
2778
2779 err_unregister_netdevice_notifier:
2780         mlx5_remove_roce_notifier(dev);
2781         return err;
2782 }
2783
2784 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2785 {
2786         mlx5_roce_lag_cleanup(dev);
2787         mlx5_nic_vport_disable_roce(dev->mdev);
2788 }
2789
2790 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2791 {
2792         unsigned int i;
2793
2794         for (i = 0; i < dev->num_ports; i++)
2795                 mlx5_core_dealloc_q_counter(dev->mdev,
2796                                             dev->port[i].q_cnt_id);
2797 }
2798
2799 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2800 {
2801         int i;
2802         int ret;
2803
2804         for (i = 0; i < dev->num_ports; i++) {
2805                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2806                                                 &dev->port[i].q_cnt_id);
2807                 if (ret) {
2808                         mlx5_ib_warn(dev,
2809                                      "couldn't allocate queue counter for port %d, err %d\n",
2810                                      i + 1, ret);
2811                         goto dealloc_counters;
2812                 }
2813         }
2814
2815         return 0;
2816
2817 dealloc_counters:
2818         while (--i >= 0)
2819                 mlx5_core_dealloc_q_counter(dev->mdev,
2820                                             dev->port[i].q_cnt_id);
2821
2822         return ret;
2823 }
2824
2825 static const char * const names[] = {
2826         "rx_write_requests",
2827         "rx_read_requests",
2828         "rx_atomic_requests",
2829         "out_of_buffer",
2830         "out_of_sequence",
2831         "duplicate_request",
2832         "rnr_nak_retry_err",
2833         "packet_seq_err",
2834         "implied_nak_seq_err",
2835         "local_ack_timeout_err",
2836 };
2837
2838 static const size_t stats_offsets[] = {
2839         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2840         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2841         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2842         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2843         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2844         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2845         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2846         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2847         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2848         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2849 };
2850
2851 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2852                                                     u8 port_num)
2853 {
2854         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2855
2856         /* We support only per port stats */
2857         if (port_num == 0)
2858                 return NULL;
2859
2860         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2861                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2862 }
2863
2864 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2865                                 struct rdma_hw_stats *stats,
2866                                 u8 port, int index)
2867 {
2868         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2869         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2870         void *out;
2871         __be32 val;
2872         int ret;
2873         int i;
2874
2875         if (!port || !stats)
2876                 return -ENOSYS;
2877
2878         out = mlx5_vzalloc(outlen);
2879         if (!out)
2880                 return -ENOMEM;
2881
2882         ret = mlx5_core_query_q_counter(dev->mdev,
2883                                         dev->port[port - 1].q_cnt_id, 0,
2884                                         out, outlen);
2885         if (ret)
2886                 goto free;
2887
2888         for (i = 0; i < ARRAY_SIZE(names); i++) {
2889                 val = *(__be32 *)(out + stats_offsets[i]);
2890                 stats->value[i] = (u64)be32_to_cpu(val);
2891         }
2892 free:
2893         kvfree(out);
2894         return ARRAY_SIZE(names);
2895 }
2896
2897 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2898 {
2899         struct mlx5_ib_dev *dev;
2900         enum rdma_link_layer ll;
2901         int port_type_cap;
2902         int err;
2903         int i;
2904
2905         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2906         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2907
2908         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2909                 return NULL;
2910
2911         printk_once(KERN_INFO "%s", mlx5_version);
2912
2913         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2914         if (!dev)
2915                 return NULL;
2916
2917         dev->mdev = mdev;
2918
2919         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2920                             GFP_KERNEL);
2921         if (!dev->port)
2922                 goto err_dealloc;
2923
2924         rwlock_init(&dev->roce.netdev_lock);
2925         err = get_port_caps(dev);
2926         if (err)
2927                 goto err_free_port;
2928
2929         if (mlx5_use_mad_ifc(dev))
2930                 get_ext_port_caps(dev);
2931
2932         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2933
2934         strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2935         dev->ib_dev.owner               = THIS_MODULE;
2936         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2937         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2938         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2939         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2940         dev->ib_dev.num_comp_vectors    =
2941                 dev->mdev->priv.eq_table.num_comp_vectors;
2942         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2943
2944         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2945         dev->ib_dev.uverbs_cmd_mask     =
2946                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2947                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2948                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2949                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2950                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2951                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2952                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2953                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2954                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2955                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2956                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2957                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2958                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2959                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2960                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2961                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2962                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2963                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2964                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2965                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2966                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2967                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2968                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
2969                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2970         dev->ib_dev.uverbs_ex_cmd_mask =
2971                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
2972                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
2973                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2974
2975         dev->ib_dev.query_device        = mlx5_ib_query_device;
2976         dev->ib_dev.query_port          = mlx5_ib_query_port;
2977         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
2978         if (ll == IB_LINK_LAYER_ETHERNET)
2979                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
2980         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
2981         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
2982         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
2983         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
2984         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
2985         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
2986         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
2987         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
2988         dev->ib_dev.mmap                = mlx5_ib_mmap;
2989         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
2990         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
2991         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
2992         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
2993         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
2994         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
2995         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
2996         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
2997         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
2998         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
2999         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3000         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3001         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3002         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3003         dev->ib_dev.post_send           = mlx5_ib_post_send;
3004         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3005         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3006         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3007         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3008         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3009         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3010         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3011         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3012         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3013         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3014         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3015         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3016         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3017         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3018         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3019         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3020         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3021         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3022         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3023         if (mlx5_core_is_pf(mdev)) {
3024                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3025                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3026                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3027                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3028         }
3029
3030         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3031
3032         mlx5_ib_internal_fill_odp_caps(dev);
3033
3034         if (MLX5_CAP_GEN(mdev, imaicl)) {
3035                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3036                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3037                 dev->ib_dev.uverbs_cmd_mask |=
3038                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3039                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3040         }
3041
3042         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3043             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3044                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3045                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3046         }
3047
3048         if (MLX5_CAP_GEN(mdev, xrc)) {
3049                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3050                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3051                 dev->ib_dev.uverbs_cmd_mask |=
3052                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3053                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3054         }
3055
3056         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3057             IB_LINK_LAYER_ETHERNET) {
3058                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3059                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3060                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3061                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3062                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3063                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3064                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3065                 dev->ib_dev.uverbs_ex_cmd_mask |=
3066                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3067                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3068                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3069                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3070                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3071                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3072                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3073         }
3074         err = init_node_data(dev);
3075         if (err)
3076                 goto err_dealloc;
3077
3078         mutex_init(&dev->flow_db.lock);
3079         mutex_init(&dev->cap_mask_mutex);
3080         INIT_LIST_HEAD(&dev->qp_list);
3081         spin_lock_init(&dev->reset_flow_resource_lock);
3082
3083         if (ll == IB_LINK_LAYER_ETHERNET) {
3084                 err = mlx5_enable_roce(dev);
3085                 if (err)
3086                         goto err_dealloc;
3087         }
3088
3089         err = create_dev_resources(&dev->devr);
3090         if (err)
3091                 goto err_disable_roce;
3092
3093         err = mlx5_ib_odp_init_one(dev);
3094         if (err)
3095                 goto err_rsrc;
3096
3097         err = mlx5_ib_alloc_q_counters(dev);
3098         if (err)
3099                 goto err_odp;
3100
3101         err = ib_register_device(&dev->ib_dev, NULL);
3102         if (err)
3103                 goto err_q_cnt;
3104
3105         err = create_umr_res(dev);
3106         if (err)
3107                 goto err_dev;
3108
3109         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3110                 err = device_create_file(&dev->ib_dev.dev,
3111                                          mlx5_class_attributes[i]);
3112                 if (err)
3113                         goto err_umrc;
3114         }
3115
3116         dev->ib_active = true;
3117
3118         return dev;
3119
3120 err_umrc:
3121         destroy_umrc_res(dev);
3122
3123 err_dev:
3124         ib_unregister_device(&dev->ib_dev);
3125
3126 err_q_cnt:
3127         mlx5_ib_dealloc_q_counters(dev);
3128
3129 err_odp:
3130         mlx5_ib_odp_remove_one(dev);
3131
3132 err_rsrc:
3133         destroy_dev_resources(&dev->devr);
3134
3135 err_disable_roce:
3136         if (ll == IB_LINK_LAYER_ETHERNET) {
3137                 mlx5_disable_roce(dev);
3138                 mlx5_remove_roce_notifier(dev);
3139         }
3140
3141 err_free_port:
3142         kfree(dev->port);
3143
3144 err_dealloc:
3145         ib_dealloc_device((struct ib_device *)dev);
3146
3147         return NULL;
3148 }
3149
3150 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3151 {
3152         struct mlx5_ib_dev *dev = context;
3153         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3154
3155         mlx5_remove_roce_notifier(dev);
3156         ib_unregister_device(&dev->ib_dev);
3157         mlx5_ib_dealloc_q_counters(dev);
3158         destroy_umrc_res(dev);
3159         mlx5_ib_odp_remove_one(dev);
3160         destroy_dev_resources(&dev->devr);
3161         if (ll == IB_LINK_LAYER_ETHERNET)
3162                 mlx5_disable_roce(dev);
3163         kfree(dev->port);
3164         ib_dealloc_device(&dev->ib_dev);
3165 }
3166
3167 static struct mlx5_interface mlx5_ib_interface = {
3168         .add            = mlx5_ib_add,
3169         .remove         = mlx5_ib_remove,
3170         .event          = mlx5_ib_event,
3171         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3172 };
3173
3174 static int __init mlx5_ib_init(void)
3175 {
3176         int err;
3177
3178         if (deprecated_prof_sel != 2)
3179                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3180
3181         err = mlx5_ib_odp_init();
3182         if (err)
3183                 return err;
3184
3185         err = mlx5_register_interface(&mlx5_ib_interface);
3186         if (err)
3187                 goto clean_odp;
3188
3189         return err;
3190
3191 clean_odp:
3192         mlx5_ib_odp_cleanup();
3193         return err;
3194 }
3195
3196 static void __exit mlx5_ib_cleanup(void)
3197 {
3198         mlx5_unregister_interface(&mlx5_ib_interface);
3199         mlx5_ib_odp_cleanup();
3200 }
3201
3202 module_init(mlx5_ib_init);
3203 module_exit(mlx5_ib_cleanup);