2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
47 #define mlx5_ib_dbg(dev, format, arg...) \
48 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
49 __LINE__, current->pid, ##arg)
51 #define mlx5_ib_err(dev, format, arg...) \
52 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
53 __LINE__, current->pid, ##arg)
55 #define mlx5_ib_warn(dev, format, arg...) \
56 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
60 sizeof(((type *)0)->fld) <= (sz))
61 #define MLX5_IB_DEFAULT_UIDX 0xffffff
62 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
65 MLX5_IB_MMAP_CMD_SHIFT = 8,
66 MLX5_IB_MMAP_CMD_MASK = 0xff,
69 enum mlx5_ib_mmap_cmd {
70 MLX5_IB_MMAP_REGULAR_PAGE = 0,
71 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
72 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
73 MLX5_IB_MMAP_CORE_CLOCK = 5,
77 MLX5_RES_SCAT_DATA32_CQE = 0x1,
78 MLX5_RES_SCAT_DATA64_CQE = 0x2,
79 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
80 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
83 enum mlx5_ib_latency_class {
84 MLX5_IB_LATENCY_CLASS_LOW,
85 MLX5_IB_LATENCY_CLASS_MEDIUM,
86 MLX5_IB_LATENCY_CLASS_HIGH,
87 MLX5_IB_LATENCY_CLASS_FAST_PATH
90 enum mlx5_ib_mad_ifc_flags {
91 MLX5_MAD_IFC_IGNORE_MKEY = 1,
92 MLX5_MAD_IFC_IGNORE_BKEY = 2,
93 MLX5_MAD_IFC_NET_VIEW = 4,
97 MLX5_CROSS_CHANNEL_UUAR = 0,
105 struct mlx5_ib_ucontext {
106 struct ib_ucontext ibucontext;
107 struct list_head db_page_list;
109 /* protect doorbell record alloc/free
111 struct mutex db_page_mutex;
112 struct mlx5_uuar_info uuari;
114 /* Transport Domain number */
118 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
120 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
128 /* Use macros here so that don't have to duplicate
129 * enum ib_send_flags and enum ib_qp_type for low-level driver
132 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START
133 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
134 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
135 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
136 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
146 struct wr_list *w_list;
150 /* serialize post to the work queue
172 * Connect-IB can trigger up to four concurrent pagefaults
175 enum mlx5_ib_pagefault_context {
176 MLX5_IB_PAGEFAULT_RESPONDER_READ,
177 MLX5_IB_PAGEFAULT_REQUESTOR_READ,
178 MLX5_IB_PAGEFAULT_RESPONDER_WRITE,
179 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE,
180 MLX5_IB_PAGEFAULT_CONTEXTS
183 static inline enum mlx5_ib_pagefault_context
184 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault)
186 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE);
189 struct mlx5_ib_pfault {
190 struct work_struct work;
191 struct mlx5_pagefault mpfault;
194 struct mlx5_ib_ubuffer {
195 struct ib_umem *umem;
200 struct mlx5_ib_qp_base {
201 struct mlx5_ib_qp *container_mibqp;
202 struct mlx5_core_qp mqp;
203 struct mlx5_ib_ubuffer ubuffer;
206 struct mlx5_ib_qp_trans {
207 struct mlx5_ib_qp_base base;
215 struct mlx5_ib_qp_base base;
216 struct mlx5_ib_wq *rq;
217 struct mlx5_ib_ubuffer ubuffer;
218 struct mlx5_db *doorbell;
224 struct mlx5_ib_qp_base base;
225 struct mlx5_ib_wq *sq;
226 struct mlx5_ib_ubuffer ubuffer;
227 struct mlx5_db *doorbell;
232 struct mlx5_ib_raw_packet_qp {
233 struct mlx5_ib_sq sq;
234 struct mlx5_ib_rq rq;
240 struct mlx5_ib_qp_trans trans_qp;
241 struct mlx5_ib_raw_packet_qp raw_packet_qp;
246 struct mlx5_ib_wq rq;
250 struct mlx5_ib_wq sq;
252 /* serialize qp state modifications
264 /* only for user space QPs. For kernel
265 * we have it from the bf object
271 /* Store signature errors */
274 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
276 * A flag that is true for QP's that are in a state that doesn't
277 * allow page faults, and shouldn't schedule any more faults.
279 int disable_page_faults;
281 * The disable_page_faults_lock protects a QP's disable_page_faults
282 * field, allowing for a thread to atomically check whether the QP
283 * allows page faults, and if so schedule a page fault.
285 spinlock_t disable_page_faults_lock;
286 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS];
290 struct mlx5_ib_cq_buf {
292 struct ib_umem *umem;
297 enum mlx5_ib_qp_flags {
298 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = 1 << 0,
299 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 1,
300 MLX5_IB_QP_CROSS_CHANNEL = 1 << 2,
301 MLX5_IB_QP_MANAGED_SEND = 1 << 3,
302 MLX5_IB_QP_MANAGED_RECV = 1 << 4,
306 struct ib_send_wr wr;
312 unsigned int page_shift;
319 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
321 return container_of(wr, struct mlx5_umr_wr, wr);
324 struct mlx5_shared_mr_info {
326 struct ib_umem *umem;
331 struct mlx5_core_cq mcq;
332 struct mlx5_ib_cq_buf buf;
335 /* serialize access to the CQ
341 struct mutex resize_mutex;
342 struct mlx5_ib_cq_buf *resize_buf;
343 struct ib_umem *resize_umem;
350 struct mlx5_core_srq msrq;
354 /* protect SRQ hanlding
360 struct ib_umem *umem;
361 /* serialize arming a SRQ
367 struct mlx5_ib_xrcd {
368 struct ib_xrcd ibxrcd;
372 enum mlx5_ib_mtt_access_flags {
373 MLX5_IB_MTT_READ = (1 << 0),
374 MLX5_IB_MTT_WRITE = (1 << 1),
377 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
386 struct mlx5_core_mr mmr;
387 struct ib_umem *umem;
388 struct mlx5_shared_mr_info *smr_info;
389 struct list_head list;
393 struct mlx5_ib_dev *dev;
394 struct mlx5_create_mkey_mbox_out out;
395 struct mlx5_core_sig_ctx *sig;
400 struct mlx5_ib_umr_context {
401 enum ib_wc_status status;
402 struct completion done;
405 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
407 context->status = -1;
408 init_completion(&context->done);
415 /* control access to UMR QP
417 struct semaphore sem;
426 struct mlx5_cache_ent {
427 struct list_head head;
428 /* sync access to the cahce entry
441 struct dentry *fsize;
443 struct dentry *fmiss;
444 struct dentry *flimit;
446 struct mlx5_ib_dev *dev;
447 struct work_struct work;
448 struct delayed_work dwork;
452 struct mlx5_mr_cache {
453 struct workqueue_struct *wq;
454 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
457 unsigned long last_add;
460 struct mlx5_ib_resources {
470 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
473 rwlock_t netdev_lock;
474 struct net_device *netdev;
475 struct notifier_block nb;
479 struct ib_device ib_dev;
480 struct mlx5_core_dev *mdev;
481 struct mlx5_roce roce;
482 MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
484 /* serialize update of capability mask
486 struct mutex cap_mask_mutex;
488 struct umr_common umrc;
489 /* sync used page count stats
491 struct mlx5_ib_resources devr;
492 struct mlx5_mr_cache cache;
493 struct timer_list delay_timer;
495 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
496 struct ib_odp_caps odp_caps;
498 * Sleepable RCU that prevents destruction of MRs while they are still
499 * being used by a page fault handler.
501 struct srcu_struct mr_srcu;
505 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
507 return container_of(mcq, struct mlx5_ib_cq, mcq);
510 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
512 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
515 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
517 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
520 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
522 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
525 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
527 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
530 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
532 return container_of(mmr, struct mlx5_ib_mr, mmr);
535 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
537 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
540 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
542 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
545 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
547 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
550 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
552 return container_of(msrq, struct mlx5_ib_srq, msrq);
555 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
557 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
565 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
567 return container_of(ibah, struct mlx5_ib_ah, ibah);
570 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
572 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
573 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
574 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
575 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
576 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
577 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
578 const void *in_mad, void *response_mad);
579 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
580 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
581 int mlx5_ib_destroy_ah(struct ib_ah *ah);
582 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
583 struct ib_srq_init_attr *init_attr,
584 struct ib_udata *udata);
585 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
586 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
587 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
588 int mlx5_ib_destroy_srq(struct ib_srq *srq);
589 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
590 struct ib_recv_wr **bad_wr);
591 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
592 struct ib_qp_init_attr *init_attr,
593 struct ib_udata *udata);
594 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
595 int attr_mask, struct ib_udata *udata);
596 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
597 struct ib_qp_init_attr *qp_init_attr);
598 int mlx5_ib_destroy_qp(struct ib_qp *qp);
599 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
600 struct ib_send_wr **bad_wr);
601 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
602 struct ib_recv_wr **bad_wr);
603 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
604 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
605 void *buffer, u32 length,
606 struct mlx5_ib_qp_base *base);
607 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
608 const struct ib_cq_init_attr *attr,
609 struct ib_ucontext *context,
610 struct ib_udata *udata);
611 int mlx5_ib_destroy_cq(struct ib_cq *cq);
612 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
613 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
614 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
615 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
616 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
617 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
618 u64 virt_addr, int access_flags,
619 struct ib_udata *udata);
620 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
621 int npages, int zap);
622 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
623 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
624 enum ib_mr_type mr_type,
626 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr,
627 struct scatterlist *sg,
629 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
630 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
631 const struct ib_mad_hdr *in, size_t in_mad_size,
632 struct ib_mad_hdr *out, size_t *out_mad_size,
633 u16 *out_mad_pkey_index);
634 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
635 struct ib_ucontext *context,
636 struct ib_udata *udata);
637 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
638 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
639 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
640 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
641 struct ib_smp *out_mad);
642 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
643 __be64 *sys_image_guid);
644 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
646 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
648 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
649 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
650 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
652 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
654 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
655 struct ib_port_attr *props);
656 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
657 struct ib_port_attr *props);
658 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
659 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
660 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
661 int *ncont, int *order);
662 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
663 int page_shift, size_t offset, size_t num_pages,
664 __be64 *pas, int access_flags);
665 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
666 int page_shift, __be64 *pas, int access_flags);
667 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
668 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
669 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
670 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
671 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
672 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
673 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
674 struct ib_mr_status *mr_status);
676 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
677 extern struct workqueue_struct *mlx5_ib_page_fault_wq;
679 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
680 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
681 struct mlx5_ib_pfault *pfault);
682 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp);
683 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
684 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev);
685 int __init mlx5_ib_odp_init(void);
686 void mlx5_ib_odp_cleanup(void);
687 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp);
688 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp);
689 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
692 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
693 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
698 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {}
699 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
700 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {}
701 static inline int mlx5_ib_odp_init(void) { return 0; }
702 static inline void mlx5_ib_odp_cleanup(void) {}
703 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {}
704 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {}
706 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
708 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
711 static inline void init_query_mad(struct ib_smp *mad)
713 mad->base_version = 1;
714 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
715 mad->class_version = 1;
716 mad->method = IB_MGMT_METHOD_GET;
719 static inline u8 convert_access(int acc)
721 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
722 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
723 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
724 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
725 MLX5_PERM_LOCAL_READ;
728 static inline int is_qp1(enum ib_qp_type qp_type)
730 return qp_type == IB_QPT_GSI;
733 #define MLX5_MAX_UMR_SHIFT 16
734 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
736 static inline u32 check_cq_create_flags(u32 flags)
739 * It returns non-zero value for unsupported CQ
740 * create flags, otherwise it returns zero.
742 return (flags & ~IB_CQ_FLAGS_IGNORE_OVERRUN);
745 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
749 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
750 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
752 *user_index = cmd_uidx;
754 *user_index = MLX5_IB_DEFAULT_UIDX;
759 #endif /* MLX5_IB_H */