drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38 #include "user.h"
  39
  40 /* not supported currently */
  41 static int wq_signature;
  42
  43 enum {
  44         MLX5_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  50         MLX5_IB_LINK_TYPE_IB            = 0,
  51         MLX5_IB_LINK_TYPE_ETH           = 1
  52 };
  53
  54 enum {
  55         MLX5_IB_SQ_STRIDE       = 6,
  56         MLX5_IB_CACHE_LINE_SIZE = 64,
  57 };
  58
  59 static const u32 mlx5_ib_opcode[] = {
  60         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  61         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  62         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  63         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  64         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  65         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  66         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  67         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  68         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  69         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  70         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  71         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  72         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  73         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  74 };
  75
  76 struct mlx5_wqe_eth_pad {
  77         u8 rsvd0[16];
  78 };
  79
  80 static void get_cqs(enum ib_qp_type qp_type,
  81                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  82                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
  83
  84 static int is_qp0(enum ib_qp_type qp_type)
  85 {
  86         return qp_type == IB_QPT_SMI;
  87 }
  88
  89 static int is_sqp(enum ib_qp_type qp_type)
  90 {
  91         return is_qp0(qp_type) || is_qp1(qp_type);
  92 }
  93
  94 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  95 {
  96         return mlx5_buf_offset(&qp->buf, offset);
  97 }
  98
  99 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 100 {
 101         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 102 }
 103
 104 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 105 {
 106         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 107 }
 108
 109 /**
 110  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 111  *
 112  * @qp: QP to copy from.
 113  * @send: copy from the send queue when non-zero, use the receive queue
 114  *        otherwise.
 115  * @wqe_index:  index to start copying from. For send work queues, the
 116  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 117  *              For receive work queue, it is the number of work queue
 118  *              element in the queue.
 119  * @buffer: destination buffer.
 120  * @length: maximum number of bytes to copy.
 121  *
 122  * Copies at least a single WQE, but may copy more data.
 123  *
 124  * Return: the number of bytes copied, or an error code.
 125  */
 126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 127                           void *buffer, u32 length,
 128                           struct mlx5_ib_qp_base *base)
 129 {
 130         struct ib_device *ibdev = qp->ibqp.device;
 131         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 132         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 133         size_t offset;
 134         size_t wq_end;
 135         struct ib_umem *umem = base->ubuffer.umem;
 136         u32 first_copy_length;
 137         int wqe_length;
 138         int ret;
 139
 140         if (wq->wqe_cnt == 0) {
 141                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 142                             qp->ibqp.qp_type);
 143                 return -EINVAL;
 144         }
 145
 146         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 147         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 148
 149         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 150                 return -EINVAL;
 151
 152         if (offset > umem->length ||
 153             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 154                 return -EINVAL;
 155
 156         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 157         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 158         if (ret)
 159                 return ret;
 160
 161         if (send) {
 162                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 163                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 164
 165                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 166         } else {
 167                 wqe_length = 1 << wq->wqe_shift;
 168         }
 169
 170         if (wqe_length <= first_copy_length)
 171                 return first_copy_length;
 172
 173         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 174                                 wqe_length - first_copy_length);
 175         if (ret)
 176                 return ret;
 177
 178         return wqe_length;
 179 }
 180
 181 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 182 {
 183         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 184         struct ib_event event;
 185
 186         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 187                 /* This event is only valid for trans_qps */
 188                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 189         }
 190
 191         if (ibqp->event_handler) {
 192                 event.device     = ibqp->device;
 193                 event.element.qp = ibqp;
 194                 switch (type) {
 195                 case MLX5_EVENT_TYPE_PATH_MIG:
 196                         event.event = IB_EVENT_PATH_MIG;
 197                         break;
 198                 case MLX5_EVENT_TYPE_COMM_EST:
 199                         event.event = IB_EVENT_COMM_EST;
 200                         break;
 201                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 202                         event.event = IB_EVENT_SQ_DRAINED;
 203                         break;
 204                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 205                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 206                         break;
 207                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 208                         event.event = IB_EVENT_QP_FATAL;
 209                         break;
 210                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 211                         event.event = IB_EVENT_PATH_MIG_ERR;
 212                         break;
 213                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 214                         event.event = IB_EVENT_QP_REQ_ERR;
 215                         break;
 216                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 217                         event.event = IB_EVENT_QP_ACCESS_ERR;
 218                         break;
 219                 default:
 220                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 221                         return;
 222                 }
 223
 224                 ibqp->event_handler(&event, ibqp->qp_context);
 225         }
 226 }
 227
 228 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 229                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 230 {
 231         int wqe_size;
 232         int wq_size;
 233
 234         /* Sanity check RQ size before proceeding */
 235         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 236                 return -EINVAL;
 237
 238         if (!has_rq) {
 239                 qp->rq.max_gs = 0;
 240                 qp->rq.wqe_cnt = 0;
 241                 qp->rq.wqe_shift = 0;
 242                 cap->max_recv_wr = 0;
 243                 cap->max_recv_sge = 0;
 244         } else {
 245                 if (ucmd) {
 246                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 247                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 248                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 249                         qp->rq.max_post = qp->rq.wqe_cnt;
 250                 } else {
 251                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 252                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 253                         wqe_size = roundup_pow_of_two(wqe_size);
 254                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 255                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 256                         qp->rq.wqe_cnt = wq_size / wqe_size;
 257                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 258                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 259                                             wqe_size,
 260                                             MLX5_CAP_GEN(dev->mdev,
 261                                                          max_wqe_sz_rq));
 262                                 return -EINVAL;
 263                         }
 264                         qp->rq.wqe_shift = ilog2(wqe_size);
 265                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 266                         qp->rq.max_post = qp->rq.wqe_cnt;
 267                 }
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int sq_overhead(struct ib_qp_init_attr *attr)
 274 {
 275         int size = 0;
 276
 277         switch (attr->qp_type) {
 278         case IB_QPT_XRC_INI:
 279                 size += sizeof(struct mlx5_wqe_xrc_seg);
 280                 /* fall through */
 281         case IB_QPT_RC:
 282                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 283                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 284                             sizeof(struct mlx5_wqe_raddr_seg),
 285                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 286                             sizeof(struct mlx5_mkey_seg));
 287                 break;
 288
 289         case IB_QPT_XRC_TGT:
 290                 return 0;
 291
 292         case IB_QPT_UC:
 293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 294                         max(sizeof(struct mlx5_wqe_raddr_seg),
 295                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 296                             sizeof(struct mlx5_mkey_seg));
 297                 break;
 298
 299         case IB_QPT_UD:
 300                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 301                         size += sizeof(struct mlx5_wqe_eth_pad) +
 302                                 sizeof(struct mlx5_wqe_eth_seg);
 303                 /* fall through */
 304         case IB_QPT_SMI:
 305         case MLX5_IB_QPT_HW_GSI:
 306                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 307                         sizeof(struct mlx5_wqe_datagram_seg);
 308                 break;
 309
 310         case MLX5_IB_QPT_REG_UMR:
 311                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 312                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 313                         sizeof(struct mlx5_mkey_seg);
 314                 break;
 315
 316         default:
 317                 return -EINVAL;
 318         }
 319
 320         return size;
 321 }
 322
 323 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 324 {
 325         int inl_size = 0;
 326         int size;
 327
 328         size = sq_overhead(attr);
 329         if (size < 0)
 330                 return size;
 331
 332         if (attr->cap.max_inline_data) {
 333                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 334                         attr->cap.max_inline_data;
 335         }
 336
 337         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 338         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 339             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 340                         return MLX5_SIG_WQE_SIZE;
 341         else
 342                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 343 }
 344
 345 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 346                         struct mlx5_ib_qp *qp)
 347 {
 348         int wqe_size;
 349         int wq_size;
 350
 351         if (!attr->cap.max_send_wr)
 352                 return 0;
 353
 354         wqe_size = calc_send_wqe(attr);
 355         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 356         if (wqe_size < 0)
 357                 return wqe_size;
 358
 359         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 360                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 361                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 362                 return -EINVAL;
 363         }
 364
 365         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 366                               sizeof(struct mlx5_wqe_inline_seg);
 367         attr->cap.max_inline_data = qp->max_inline_data;
 368
 369         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 370                 qp->signature_en = true;
 371
 372         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 373         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 374         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 375                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 376                             qp->sq.wqe_cnt,
 377                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 378                 return -ENOMEM;
 379         }
 380         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 381         qp->sq.max_gs = attr->cap.max_send_sge;
 382         qp->sq.max_post = wq_size / wqe_size;
 383         attr->cap.max_send_wr = qp->sq.max_post;
 384
 385         return wq_size;
 386 }
 387
 388 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 389                             struct mlx5_ib_qp *qp,
 390                             struct mlx5_ib_create_qp *ucmd,
 391                             struct mlx5_ib_qp_base *base,
 392                             struct ib_qp_init_attr *attr)
 393 {
 394         int desc_sz = 1 << qp->sq.wqe_shift;
 395
 396         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 397                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 398                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 399                 return -EINVAL;
 400         }
 401
 402         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 403                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 404                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 405                 return -EINVAL;
 406         }
 407
 408         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 409
 410         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 411                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 412                              qp->sq.wqe_cnt,
 413                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 414                 return -EINVAL;
 415         }
 416
 417         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 418                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 419                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 420         } else {
 421                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 422                                          (qp->sq.wqe_cnt << 6);
 423         }
 424
 425         return 0;
 426 }
 427
 428 static int qp_has_rq(struct ib_qp_init_attr *attr)
 429 {
 430         if (attr->qp_type == IB_QPT_XRC_INI ||
 431             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 432             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 433             !attr->cap.max_recv_wr)
 434                 return 0;
 435
 436         return 1;
 437 }
 438
 439 static int first_med_uuar(void)
 440 {
 441         return 1;
 442 }
 443
 444 static int next_uuar(int n)
 445 {
 446         n++;
 447
 448         while (((n % 4) & 2))
 449                 n++;
 450
 451         return n;
 452 }
 453
 454 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 455 {
 456         int n;
 457
 458         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 459                 uuari->num_low_latency_uuars - 1;
 460
 461         return n >= 0 ? n : 0;
 462 }
 463
 464 static int max_uuari(struct mlx5_uuar_info *uuari)
 465 {
 466         return uuari->num_uars * 4;
 467 }
 468
 469 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 470 {
 471         int med;
 472         int i;
 473         int t;
 474
 475         med = num_med_uuar(uuari);
 476         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 477                 t++;
 478                 if (t == med)
 479                         return next_uuar(i);
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 486 {
 487         int i;
 488
 489         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 490                 if (!test_bit(i, uuari->bitmap)) {
 491                         set_bit(i, uuari->bitmap);
 492                         uuari->count[i]++;
 493                         return i;
 494                 }
 495         }
 496
 497         return -ENOMEM;
 498 }
 499
 500 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 501 {
 502         int minidx = first_med_uuar();
 503         int i;
 504
 505         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 506                 if (uuari->count[i] < uuari->count[minidx])
 507                         minidx = i;
 508         }
 509
 510         uuari->count[minidx]++;
 511         return minidx;
 512 }
 513
 514 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 515                       enum mlx5_ib_latency_class lat)
 516 {
 517         int uuarn = -EINVAL;
 518
 519         mutex_lock(&uuari->lock);
 520         switch (lat) {
 521         case MLX5_IB_LATENCY_CLASS_LOW:
 522                 uuarn = 0;
 523                 uuari->count[uuarn]++;
 524                 break;
 525
 526         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 527                 if (uuari->ver < 2)
 528                         uuarn = -ENOMEM;
 529                 else
 530                         uuarn = alloc_med_class_uuar(uuari);
 531                 break;
 532
 533         case MLX5_IB_LATENCY_CLASS_HIGH:
 534                 if (uuari->ver < 2)
 535                         uuarn = -ENOMEM;
 536                 else
 537                         uuarn = alloc_high_class_uuar(uuari);
 538                 break;
 539
 540         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 541                 uuarn = 2;
 542                 break;
 543         }
 544         mutex_unlock(&uuari->lock);
 545
 546         return uuarn;
 547 }
 548
 549 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 550 {
 551         clear_bit(uuarn, uuari->bitmap);
 552         --uuari->count[uuarn];
 553 }
 554
 555 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 556 {
 557         clear_bit(uuarn, uuari->bitmap);
 558         --uuari->count[uuarn];
 559 }
 560
 561 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 562 {
 563         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 564         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 565
 566         mutex_lock(&uuari->lock);
 567         if (uuarn == 0) {
 568                 --uuari->count[uuarn];
 569                 goto out;
 570         }
 571
 572         if (uuarn < high_uuar) {
 573                 free_med_class_uuar(uuari, uuarn);
 574                 goto out;
 575         }
 576
 577         free_high_class_uuar(uuari, uuarn);
 578
 579 out:
 580         mutex_unlock(&uuari->lock);
 581 }
 582
 583 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 584 {
 585         switch (state) {
 586         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 587         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 588         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 589         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 590         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 591         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 592         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 593         default:                return -1;
 594         }
 595 }
 596
 597 static int to_mlx5_st(enum ib_qp_type type)
 598 {
 599         switch (type) {
 600         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 601         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 602         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 603         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 604         case IB_QPT_XRC_INI:
 605         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 606         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 607         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 608         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 609         case IB_QPT_RAW_PACKET:
 610         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 611         case IB_QPT_MAX:
 612         default:                return -EINVAL;
 613         }
 614 }
 615
 616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 617                              struct mlx5_ib_cq *recv_cq);
 618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 619                                struct mlx5_ib_cq *recv_cq);
 620
 621 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 622 {
 623         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 624 }
 625
 626 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 627                             struct ib_pd *pd,
 628                             unsigned long addr, size_t size,
 629                             struct ib_umem **umem,
 630                             int *npages, int *page_shift, int *ncont,
 631                             u32 *offset)
 632 {
 633         int err;
 634
 635         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 636         if (IS_ERR(*umem)) {
 637                 mlx5_ib_dbg(dev, "umem_get failed\n");
 638                 return PTR_ERR(*umem);
 639         }
 640
 641         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 642
 643         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 644         if (err) {
 645                 mlx5_ib_warn(dev, "bad offset\n");
 646                 goto err_umem;
 647         }
 648
 649         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 650                     addr, size, *npages, *page_shift, *ncont, *offset);
 651
 652         return 0;
 653
 654 err_umem:
 655         ib_umem_release(*umem);
 656         *umem = NULL;
 657
 658         return err;
 659 }
 660
 661 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 662 {
 663         struct mlx5_ib_ucontext *context;
 664
 665         context = to_mucontext(pd->uobject->context);
 666         mlx5_ib_db_unmap_user(context, &rwq->db);
 667         if (rwq->umem)
 668                 ib_umem_release(rwq->umem);
 669 }
 670
 671 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 672                           struct mlx5_ib_rwq *rwq,
 673                           struct mlx5_ib_create_wq *ucmd)
 674 {
 675         struct mlx5_ib_ucontext *context;
 676         int page_shift = 0;
 677         int npages;
 678         u32 offset = 0;
 679         int ncont = 0;
 680         int err;
 681
 682         if (!ucmd->buf_addr)
 683                 return -EINVAL;
 684
 685         context = to_mucontext(pd->uobject->context);
 686         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 687                                rwq->buf_size, 0, 0);
 688         if (IS_ERR(rwq->umem)) {
 689                 mlx5_ib_dbg(dev, "umem_get failed\n");
 690                 err = PTR_ERR(rwq->umem);
 691                 return err;
 692         }
 693
 694         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 695                            &ncont, NULL);
 696         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 697                                      &rwq->rq_page_offset);
 698         if (err) {
 699                 mlx5_ib_warn(dev, "bad offset\n");
 700                 goto err_umem;
 701         }
 702
 703         rwq->rq_num_pas = ncont;
 704         rwq->page_shift = page_shift;
 705         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 706         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 707
 708         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 709                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 710                     npages, page_shift, ncont, offset);
 711
 712         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 713         if (err) {
 714                 mlx5_ib_dbg(dev, "map failed\n");
 715                 goto err_umem;
 716         }
 717
 718         rwq->create_type = MLX5_WQ_USER;
 719         return 0;
 720
 721 err_umem:
 722         ib_umem_release(rwq->umem);
 723         return err;
 724 }
 725
 726 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 727                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 728                           struct ib_qp_init_attr *attr,
 729                           u32 **in,
 730                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 731                           struct mlx5_ib_qp_base *base)
 732 {
 733         struct mlx5_ib_ucontext *context;
 734         struct mlx5_ib_create_qp ucmd;
 735         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 736         int page_shift = 0;
 737         int uar_index;
 738         int npages;
 739         u32 offset = 0;
 740         int uuarn;
 741         int ncont = 0;
 742         __be64 *pas;
 743         void *qpc;
 744         int err;
 745
 746         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 747         if (err) {
 748                 mlx5_ib_dbg(dev, "copy failed\n");
 749                 return err;
 750         }
 751
 752         context = to_mucontext(pd->uobject->context);
 753         /*
 754          * TBD: should come from the verbs when we have the API
 755          */
 756         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 757                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 758                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 759         else {
 760                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 761                 if (uuarn < 0) {
 762                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 763                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 764                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 765                         if (uuarn < 0) {
 766                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 767                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 768                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 769                                 if (uuarn < 0) {
 770                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 771                                         return uuarn;
 772                                 }
 773                         }
 774                 }
 775         }
 776
 777         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 778         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 779
 780         qp->rq.offset = 0;
 781         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 782         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 783
 784         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 785         if (err)
 786                 goto err_uuar;
 787
 788         if (ucmd.buf_addr && ubuffer->buf_size) {
 789                 ubuffer->buf_addr = ucmd.buf_addr;
 790                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 791                                        ubuffer->buf_size,
 792                                        &ubuffer->umem, &npages, &page_shift,
 793                                        &ncont, &offset);
 794                 if (err)
 795                         goto err_uuar;
 796         } else {
 797                 ubuffer->umem = NULL;
 798         }
 799
 800         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 801                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 802         *in = mlx5_vzalloc(*inlen);
 803         if (!*in) {
 804                 err = -ENOMEM;
 805                 goto err_umem;
 806         }
 807
 808         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 809         if (ubuffer->umem)
 810                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 811
 812         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 813
 814         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 815         MLX5_SET(qpc, qpc, page_offset, offset);
 816
 817         MLX5_SET(qpc, qpc, uar_page, uar_index);
 818         resp->uuar_index = uuarn;
 819         qp->uuarn = uuarn;
 820
 821         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 822         if (err) {
 823                 mlx5_ib_dbg(dev, "map failed\n");
 824                 goto err_free;
 825         }
 826
 827         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 828         if (err) {
 829                 mlx5_ib_dbg(dev, "copy failed\n");
 830                 goto err_unmap;
 831         }
 832         qp->create_type = MLX5_QP_USER;
 833
 834         return 0;
 835
 836 err_unmap:
 837         mlx5_ib_db_unmap_user(context, &qp->db);
 838
 839 err_free:
 840         kvfree(*in);
 841
 842 err_umem:
 843         if (ubuffer->umem)
 844                 ib_umem_release(ubuffer->umem);
 845
 846 err_uuar:
 847         free_uuar(&context->uuari, uuarn);
 848         return err;
 849 }
 850
 851 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 852                             struct mlx5_ib_qp_base *base)
 853 {
 854         struct mlx5_ib_ucontext *context;
 855
 856         context = to_mucontext(pd->uobject->context);
 857         mlx5_ib_db_unmap_user(context, &qp->db);
 858         if (base->ubuffer.umem)
 859                 ib_umem_release(base->ubuffer.umem);
 860         free_uuar(&context->uuari, qp->uuarn);
 861 }
 862
 863 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 864                             struct ib_qp_init_attr *init_attr,
 865                             struct mlx5_ib_qp *qp,
 866                             u32 **in, int *inlen,
 867                             struct mlx5_ib_qp_base *base)
 868 {
 869         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 870         struct mlx5_uuar_info *uuari;
 871         int uar_index;
 872         void *qpc;
 873         int uuarn;
 874         int err;
 875
 876         uuari = &dev->mdev->priv.uuari;
 877         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 878                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 879                                         IB_QP_CREATE_IPOIB_UD_LSO |
 880                                         mlx5_ib_create_qp_sqpn_qp1()))
 881                 return -EINVAL;
 882
 883         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 884                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 885
 886         uuarn = alloc_uuar(uuari, lc);
 887         if (uuarn < 0) {
 888                 mlx5_ib_dbg(dev, "\n");
 889                 return -ENOMEM;
 890         }
 891
 892         qp->bf = &uuari->bfs[uuarn];
 893         uar_index = qp->bf->uar->index;
 894
 895         err = calc_sq_size(dev, init_attr, qp);
 896         if (err < 0) {
 897                 mlx5_ib_dbg(dev, "err %d\n", err);
 898                 goto err_uuar;
 899         }
 900
 901         qp->rq.offset = 0;
 902         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 903         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 904
 905         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 906         if (err) {
 907                 mlx5_ib_dbg(dev, "err %d\n", err);
 908                 goto err_uuar;
 909         }
 910
 911         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 912         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 913                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 914         *in = mlx5_vzalloc(*inlen);
 915         if (!*in) {
 916                 err = -ENOMEM;
 917                 goto err_buf;
 918         }
 919
 920         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 921         MLX5_SET(qpc, qpc, uar_page, uar_index);
 922         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 923
 924         /* Set "fast registration enabled" for all kernel QPs */
 925         MLX5_SET(qpc, qpc, fre, 1);
 926         MLX5_SET(qpc, qpc, rlky, 1);
 927
 928         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 929                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 930                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 931         }
 932
 933         mlx5_fill_page_array(&qp->buf,
 934                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 935
 936         err = mlx5_db_alloc(dev->mdev, &qp->db);
 937         if (err) {
 938                 mlx5_ib_dbg(dev, "err %d\n", err);
 939                 goto err_free;
 940         }
 941
 942         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 943         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 944         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 945         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 946         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 947
 948         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 949             !qp->sq.w_list || !qp->sq.wqe_head) {
 950                 err = -ENOMEM;
 951                 goto err_wrid;
 952         }
 953         qp->create_type = MLX5_QP_KERNEL;
 954
 955         return 0;
 956
 957 err_wrid:
 958         mlx5_db_free(dev->mdev, &qp->db);
 959         kfree(qp->sq.wqe_head);
 960         kfree(qp->sq.w_list);
 961         kfree(qp->sq.wrid);
 962         kfree(qp->sq.wr_data);
 963         kfree(qp->rq.wrid);
 964
 965 err_free:
 966         kvfree(*in);
 967
 968 err_buf:
 969         mlx5_buf_free(dev->mdev, &qp->buf);
 970
 971 err_uuar:
 972         free_uuar(&dev->mdev->priv.uuari, uuarn);
 973         return err;
 974 }
 975
 976 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 977 {
 978         mlx5_db_free(dev->mdev, &qp->db);
 979         kfree(qp->sq.wqe_head);
 980         kfree(qp->sq.w_list);
 981         kfree(qp->sq.wrid);
 982         kfree(qp->sq.wr_data);
 983         kfree(qp->rq.wrid);
 984         mlx5_buf_free(dev->mdev, &qp->buf);
 985         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 986 }
 987
 988 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 989 {
 990         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 991             (attr->qp_type == IB_QPT_XRC_INI))
 992                 return MLX5_SRQ_RQ;
 993         else if (!qp->has_rq)
 994                 return MLX5_ZERO_LEN_RQ;
 995         else
 996                 return MLX5_NON_ZERO_RQ;
 997 }
 998
 999 static int is_connected(enum ib_qp_type qp_type)
1000 {
1001         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1002                 return 1;
1003
1004         return 0;
1005 }
1006
1007 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1008                                     struct mlx5_ib_sq *sq, u32 tdn)
1009 {
1010         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1011         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1012
1013         memset(in, 0, sizeof(in));
1014
1015         MLX5_SET(tisc, tisc, transport_domain, tdn);
1016
1017         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1018 }
1019
1020 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1021                                       struct mlx5_ib_sq *sq)
1022 {
1023         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1024 }
1025
1026 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1027                                    struct mlx5_ib_sq *sq, void *qpin,
1028                                    struct ib_pd *pd)
1029 {
1030         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1031         __be64 *pas;
1032         void *in;
1033         void *sqc;
1034         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1035         void *wq;
1036         int inlen;
1037         int err;
1038         int page_shift = 0;
1039         int npages;
1040         int ncont = 0;
1041         u32 offset = 0;
1042
1043         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1044                                &sq->ubuffer.umem, &npages, &page_shift,
1045                                &ncont, &offset);
1046         if (err)
1047                 return err;
1048
1049         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1050         in = mlx5_vzalloc(inlen);
1051         if (!in) {
1052                 err = -ENOMEM;
1053                 goto err_umem;
1054         }
1055
1056         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1057         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1058         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1059         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1060         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1061         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1062         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1063
1064         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1065         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1066         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1067         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1068         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1069         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1070         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1071         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1072         MLX5_SET(wq, wq, page_offset, offset);
1073
1074         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1075         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1076
1077         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1078
1079         kvfree(in);
1080
1081         if (err)
1082                 goto err_umem;
1083
1084         return 0;
1085
1086 err_umem:
1087         ib_umem_release(sq->ubuffer.umem);
1088         sq->ubuffer.umem = NULL;
1089
1090         return err;
1091 }
1092
1093 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1094                                      struct mlx5_ib_sq *sq)
1095 {
1096         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1097         ib_umem_release(sq->ubuffer.umem);
1098 }
1099
1100 static int get_rq_pas_size(void *qpc)
1101 {
1102         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1103         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1104         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1105         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1106         u32 po_quanta     = 1 << (log_page_size - 6);
1107         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1108         u32 page_size     = 1 << log_page_size;
1109         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1110         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1111
1112         return rq_num_pas * sizeof(u64);
1113 }
1114
1115 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1116                                    struct mlx5_ib_rq *rq, void *qpin)
1117 {
1118         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1119         __be64 *pas;
1120         __be64 *qp_pas;
1121         void *in;
1122         void *rqc;
1123         void *wq;
1124         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1125         int inlen;
1126         int err;
1127         u32 rq_pas_size = get_rq_pas_size(qpc);
1128
1129         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1130         in = mlx5_vzalloc(inlen);
1131         if (!in)
1132                 return -ENOMEM;
1133
1134         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1135         MLX5_SET(rqc, rqc, vsd, 1);
1136         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1137         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1138         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1139         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1140         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1141
1142         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1143                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1144
1145         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1146         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1147         MLX5_SET(wq, wq, end_padding_mode,
1148                  MLX5_GET(qpc, qpc, end_padding_mode));
1149         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1150         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1151         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1152         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1153         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1154         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1155
1156         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1157         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1158         memcpy(pas, qp_pas, rq_pas_size);
1159
1160         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1161
1162         kvfree(in);
1163
1164         return err;
1165 }
1166
1167 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1168                                      struct mlx5_ib_rq *rq)
1169 {
1170         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1171 }
1172
1173 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1174                                     struct mlx5_ib_rq *rq, u32 tdn)
1175 {
1176         u32 *in;
1177         void *tirc;
1178         int inlen;
1179         int err;
1180
1181         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1182         in = mlx5_vzalloc(inlen);
1183         if (!in)
1184                 return -ENOMEM;
1185
1186         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1187         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1188         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1189         MLX5_SET(tirc, tirc, transport_domain, tdn);
1190
1191         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1192
1193         kvfree(in);
1194
1195         return err;
1196 }
1197
1198 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1199                                       struct mlx5_ib_rq *rq)
1200 {
1201         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1202 }
1203
1204 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1205                                 u32 *in,
1206                                 struct ib_pd *pd)
1207 {
1208         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1209         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1210         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1211         struct ib_uobject *uobj = pd->uobject;
1212         struct ib_ucontext *ucontext = uobj->context;
1213         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1214         int err;
1215         u32 tdn = mucontext->tdn;
1216
1217         if (qp->sq.wqe_cnt) {
1218                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1219                 if (err)
1220                         return err;
1221
1222                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1223                 if (err)
1224                         goto err_destroy_tis;
1225
1226                 sq->base.container_mibqp = qp;
1227         }
1228
1229         if (qp->rq.wqe_cnt) {
1230                 rq->base.container_mibqp = qp;
1231
1232                 err = create_raw_packet_qp_rq(dev, rq, in);
1233                 if (err)
1234                         goto err_destroy_sq;
1235
1236
1237                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1238                 if (err)
1239                         goto err_destroy_rq;
1240         }
1241
1242         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1243                                                      rq->base.mqp.qpn;
1244
1245         return 0;
1246
1247 err_destroy_rq:
1248         destroy_raw_packet_qp_rq(dev, rq);
1249 err_destroy_sq:
1250         if (!qp->sq.wqe_cnt)
1251                 return err;
1252         destroy_raw_packet_qp_sq(dev, sq);
1253 err_destroy_tis:
1254         destroy_raw_packet_qp_tis(dev, sq);
1255
1256         return err;
1257 }
1258
1259 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1260                                   struct mlx5_ib_qp *qp)
1261 {
1262         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1263         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1264         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1265
1266         if (qp->rq.wqe_cnt) {
1267                 destroy_raw_packet_qp_tir(dev, rq);
1268                 destroy_raw_packet_qp_rq(dev, rq);
1269         }
1270
1271         if (qp->sq.wqe_cnt) {
1272                 destroy_raw_packet_qp_sq(dev, sq);
1273                 destroy_raw_packet_qp_tis(dev, sq);
1274         }
1275 }
1276
1277 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1278                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1279 {
1280         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1281         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1282
1283         sq->sq = &qp->sq;
1284         rq->rq = &qp->rq;
1285         sq->doorbell = &qp->db;
1286         rq->doorbell = &qp->db;
1287 }
1288
1289 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1290 {
1291         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1292 }
1293
1294 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1295                                  struct ib_pd *pd,
1296                                  struct ib_qp_init_attr *init_attr,
1297                                  struct ib_udata *udata)
1298 {
1299         struct ib_uobject *uobj = pd->uobject;
1300         struct ib_ucontext *ucontext = uobj->context;
1301         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1302         struct mlx5_ib_create_qp_resp resp = {};
1303         int inlen;
1304         int err;
1305         u32 *in;
1306         void *tirc;
1307         void *hfso;
1308         u32 selected_fields = 0;
1309         size_t min_resp_len;
1310         u32 tdn = mucontext->tdn;
1311         struct mlx5_ib_create_qp_rss ucmd = {};
1312         size_t required_cmd_sz;
1313
1314         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1315                 return -EOPNOTSUPP;
1316
1317         if (init_attr->create_flags || init_attr->send_cq)
1318                 return -EINVAL;
1319
1320         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1321         if (udata->outlen < min_resp_len)
1322                 return -EINVAL;
1323
1324         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1325         if (udata->inlen < required_cmd_sz) {
1326                 mlx5_ib_dbg(dev, "invalid inlen\n");
1327                 return -EINVAL;
1328         }
1329
1330         if (udata->inlen > sizeof(ucmd) &&
1331             !ib_is_udata_cleared(udata, sizeof(ucmd),
1332                                  udata->inlen - sizeof(ucmd))) {
1333                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1334                 return -EOPNOTSUPP;
1335         }
1336
1337         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1338                 mlx5_ib_dbg(dev, "copy failed\n");
1339                 return -EFAULT;
1340         }
1341
1342         if (ucmd.comp_mask) {
1343                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1344                 return -EOPNOTSUPP;
1345         }
1346
1347         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1348                 mlx5_ib_dbg(dev, "invalid reserved\n");
1349                 return -EOPNOTSUPP;
1350         }
1351
1352         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1353         if (err) {
1354                 mlx5_ib_dbg(dev, "copy failed\n");
1355                 return -EINVAL;
1356         }
1357
1358         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1359         in = mlx5_vzalloc(inlen);
1360         if (!in)
1361                 return -ENOMEM;
1362
1363         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1364         MLX5_SET(tirc, tirc, disp_type,
1365                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1366         MLX5_SET(tirc, tirc, indirect_table,
1367                  init_attr->rwq_ind_tbl->ind_tbl_num);
1368         MLX5_SET(tirc, tirc, transport_domain, tdn);
1369
1370         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1371         switch (ucmd.rx_hash_function) {
1372         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1373         {
1374                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1375                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1376
1377                 if (len != ucmd.rx_key_len) {
1378                         err = -EINVAL;
1379                         goto err;
1380                 }
1381
1382                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1383                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1384                 memcpy(rss_key, ucmd.rx_hash_key, len);
1385                 break;
1386         }
1387         default:
1388                 err = -EOPNOTSUPP;
1389                 goto err;
1390         }
1391
1392         if (!ucmd.rx_hash_fields_mask) {
1393                 /* special case when this TIR serves as steering entry without hashing */
1394                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1395                         goto create_tir;
1396                 err = -EINVAL;
1397                 goto err;
1398         }
1399
1400         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1401              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1402              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1403              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1404                 err = -EINVAL;
1405                 goto err;
1406         }
1407
1408         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1409         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1410             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1411                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1412                          MLX5_L3_PROT_TYPE_IPV4);
1413         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1414                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1415                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1416                          MLX5_L3_PROT_TYPE_IPV6);
1417
1418         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1419              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1420              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1421              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1422                 err = -EINVAL;
1423                 goto err;
1424         }
1425
1426         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1427         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1428             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1429                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1430                          MLX5_L4_PROT_TYPE_TCP);
1431         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1432                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1433                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1434                          MLX5_L4_PROT_TYPE_UDP);
1435
1436         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1437             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1438                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1439
1440         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1441             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1442                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1443
1444         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1445             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1446                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1447
1448         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1449             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1450                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1451
1452         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1453
1454 create_tir:
1455         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1456
1457         if (err)
1458                 goto err;
1459
1460         kvfree(in);
1461         /* qpn is reserved for that QP */
1462         qp->trans_qp.base.mqp.qpn = 0;
1463         return 0;
1464
1465 err:
1466         kvfree(in);
1467         return err;
1468 }
1469
1470 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1471                             struct ib_qp_init_attr *init_attr,
1472                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1473 {
1474         struct mlx5_ib_resources *devr = &dev->devr;
1475         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1476         struct mlx5_core_dev *mdev = dev->mdev;
1477         struct mlx5_ib_create_qp_resp resp;
1478         struct mlx5_ib_cq *send_cq;
1479         struct mlx5_ib_cq *recv_cq;
1480         unsigned long flags;
1481         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1482         struct mlx5_ib_create_qp ucmd;
1483         struct mlx5_ib_qp_base *base;
1484         void *qpc;
1485         u32 *in;
1486         int err;
1487
1488         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1489                &qp->raw_packet_qp.rq.base :
1490                &qp->trans_qp.base;
1491
1492         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1493                 mlx5_ib_odp_create_qp(qp);
1494
1495         mutex_init(&qp->mutex);
1496         spin_lock_init(&qp->sq.lock);
1497         spin_lock_init(&qp->rq.lock);
1498
1499         if (init_attr->rwq_ind_tbl) {
1500                 if (!udata)
1501                         return -ENOSYS;
1502
1503                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1504                 return err;
1505         }
1506
1507         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1508                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1509                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1510                         return -EINVAL;
1511                 } else {
1512                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1513                 }
1514         }
1515
1516         if (init_attr->create_flags &
1517                         (IB_QP_CREATE_CROSS_CHANNEL |
1518                          IB_QP_CREATE_MANAGED_SEND |
1519                          IB_QP_CREATE_MANAGED_RECV)) {
1520                 if (!MLX5_CAP_GEN(mdev, cd)) {
1521                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1522                         return -EINVAL;
1523                 }
1524                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1525                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1526                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1527                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1528                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1529                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1530         }
1531
1532         if (init_attr->qp_type == IB_QPT_UD &&
1533             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1534                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1535                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1536                         return -EOPNOTSUPP;
1537                 }
1538
1539         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1540                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1541                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1542                         return -EOPNOTSUPP;
1543                 }
1544                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1545                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1546                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1547                         return -EOPNOTSUPP;
1548                 }
1549                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1550         }
1551
1552         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1553                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1554
1555         if (pd && pd->uobject) {
1556                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1557                         mlx5_ib_dbg(dev, "copy failed\n");
1558                         return -EFAULT;
1559                 }
1560
1561                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1562                                         &ucmd, udata->inlen, &uidx);
1563                 if (err)
1564                         return err;
1565
1566                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1567                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1568         } else {
1569                 qp->wq_sig = !!wq_signature;
1570         }
1571
1572         qp->has_rq = qp_has_rq(init_attr);
1573         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1574                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1575         if (err) {
1576                 mlx5_ib_dbg(dev, "err %d\n", err);
1577                 return err;
1578         }
1579
1580         if (pd) {
1581                 if (pd->uobject) {
1582                         __u32 max_wqes =
1583                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1584                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1585                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1586                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1587                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1588                                 return -EINVAL;
1589                         }
1590                         if (ucmd.sq_wqe_count > max_wqes) {
1591                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1592                                             ucmd.sq_wqe_count, max_wqes);
1593                                 return -EINVAL;
1594                         }
1595                         if (init_attr->create_flags &
1596                             mlx5_ib_create_qp_sqpn_qp1()) {
1597                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1598                                 return -EINVAL;
1599                         }
1600                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1601                                              &resp, &inlen, base);
1602                         if (err)
1603                                 mlx5_ib_dbg(dev, "err %d\n", err);
1604                 } else {
1605                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1606                                                base);
1607                         if (err)
1608                                 mlx5_ib_dbg(dev, "err %d\n", err);
1609                 }
1610
1611                 if (err)
1612                         return err;
1613         } else {
1614                 in = mlx5_vzalloc(inlen);
1615                 if (!in)
1616                         return -ENOMEM;
1617
1618                 qp->create_type = MLX5_QP_EMPTY;
1619         }
1620
1621         if (is_sqp(init_attr->qp_type))
1622                 qp->port = init_attr->port_num;
1623
1624         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1625
1626         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1627         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1628
1629         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1630                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1631         else
1632                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1633
1634
1635         if (qp->wq_sig)
1636                 MLX5_SET(qpc, qpc, wq_signature, 1);
1637
1638         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1639                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1640
1641         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1642                 MLX5_SET(qpc, qpc, cd_master, 1);
1643         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1644                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1645         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1646                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1647
1648         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1649                 int rcqe_sz;
1650                 int scqe_sz;
1651
1652                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1653                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1654
1655                 if (rcqe_sz == 128)
1656                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1657                 else
1658                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1659
1660                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1661                         if (scqe_sz == 128)
1662                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1663                         else
1664                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1665                 }
1666         }
1667
1668         if (qp->rq.wqe_cnt) {
1669                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1670                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1671         }
1672
1673         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1674
1675         if (qp->sq.wqe_cnt)
1676                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1677         else
1678                 MLX5_SET(qpc, qpc, no_sq, 1);
1679
1680         /* Set default resources */
1681         switch (init_attr->qp_type) {
1682         case IB_QPT_XRC_TGT:
1683                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1684                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1685                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1686                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1687                 break;
1688         case IB_QPT_XRC_INI:
1689                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1690                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1691                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1692                 break;
1693         default:
1694                 if (init_attr->srq) {
1695                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1696                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1697                 } else {
1698                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1699                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1700                 }
1701         }
1702
1703         if (init_attr->send_cq)
1704                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1705
1706         if (init_attr->recv_cq)
1707                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1708
1709         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1710
1711         /* 0xffffff means we ask to work with cqe version 0 */
1712         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1713                 MLX5_SET(qpc, qpc, user_index, uidx);
1714
1715         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1716         if (init_attr->qp_type == IB_QPT_UD &&
1717             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1718                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1719                 qp->flags |= MLX5_IB_QP_LSO;
1720         }
1721
1722         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1723                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1724                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1725                 err = create_raw_packet_qp(dev, qp, in, pd);
1726         } else {
1727                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1728         }
1729
1730         if (err) {
1731                 mlx5_ib_dbg(dev, "create qp failed\n");
1732                 goto err_create;
1733         }
1734
1735         kvfree(in);
1736
1737         base->container_mibqp = qp;
1738         base->mqp.event = mlx5_ib_qp_event;
1739
1740         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1741                 &send_cq, &recv_cq);
1742         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1743         mlx5_ib_lock_cqs(send_cq, recv_cq);
1744         /* Maintain device to QPs access, needed for further handling via reset
1745          * flow
1746          */
1747         list_add_tail(&qp->qps_list, &dev->qp_list);
1748         /* Maintain CQ to QPs access, needed for further handling via reset flow
1749          */
1750         if (send_cq)
1751                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1752         if (recv_cq)
1753                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1754         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1755         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1756
1757         return 0;
1758
1759 err_create:
1760         if (qp->create_type == MLX5_QP_USER)
1761                 destroy_qp_user(pd, qp, base);
1762         else if (qp->create_type == MLX5_QP_KERNEL)
1763                 destroy_qp_kernel(dev, qp);
1764
1765         kvfree(in);
1766         return err;
1767 }
1768
1769 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1770         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1771 {
1772         if (send_cq) {
1773                 if (recv_cq) {
1774                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1775                                 spin_lock(&send_cq->lock);
1776                                 spin_lock_nested(&recv_cq->lock,
1777                                                  SINGLE_DEPTH_NESTING);
1778                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1779                                 spin_lock(&send_cq->lock);
1780                                 __acquire(&recv_cq->lock);
1781                         } else {
1782                                 spin_lock(&recv_cq->lock);
1783                                 spin_lock_nested(&send_cq->lock,
1784                                                  SINGLE_DEPTH_NESTING);
1785                         }
1786                 } else {
1787                         spin_lock(&send_cq->lock);
1788                         __acquire(&recv_cq->lock);
1789                 }
1790         } else if (recv_cq) {
1791                 spin_lock(&recv_cq->lock);
1792                 __acquire(&send_cq->lock);
1793         } else {
1794                 __acquire(&send_cq->lock);
1795                 __acquire(&recv_cq->lock);
1796         }
1797 }
1798
1799 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1800         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1801 {
1802         if (send_cq) {
1803                 if (recv_cq) {
1804                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1805                                 spin_unlock(&recv_cq->lock);
1806                                 spin_unlock(&send_cq->lock);
1807                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1808                                 __release(&recv_cq->lock);
1809                                 spin_unlock(&send_cq->lock);
1810                         } else {
1811                                 spin_unlock(&send_cq->lock);
1812                                 spin_unlock(&recv_cq->lock);
1813                         }
1814                 } else {
1815                         __release(&recv_cq->lock);
1816                         spin_unlock(&send_cq->lock);
1817                 }
1818         } else if (recv_cq) {
1819                 __release(&send_cq->lock);
1820                 spin_unlock(&recv_cq->lock);
1821         } else {
1822                 __release(&recv_cq->lock);
1823                 __release(&send_cq->lock);
1824         }
1825 }
1826
1827 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1828 {
1829         return to_mpd(qp->ibqp.pd);
1830 }
1831
1832 static void get_cqs(enum ib_qp_type qp_type,
1833                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1834                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1835 {
1836         switch (qp_type) {
1837         case IB_QPT_XRC_TGT:
1838                 *send_cq = NULL;
1839                 *recv_cq = NULL;
1840                 break;
1841         case MLX5_IB_QPT_REG_UMR:
1842         case IB_QPT_XRC_INI:
1843                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1844                 *recv_cq = NULL;
1845                 break;
1846
1847         case IB_QPT_SMI:
1848         case MLX5_IB_QPT_HW_GSI:
1849         case IB_QPT_RC:
1850         case IB_QPT_UC:
1851         case IB_QPT_UD:
1852         case IB_QPT_RAW_IPV6:
1853         case IB_QPT_RAW_ETHERTYPE:
1854         case IB_QPT_RAW_PACKET:
1855                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1856                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1857                 break;
1858
1859         case IB_QPT_MAX:
1860         default:
1861                 *send_cq = NULL;
1862                 *recv_cq = NULL;
1863                 break;
1864         }
1865 }
1866
1867 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1868                                 u16 operation);
1869
1870 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1871 {
1872         struct mlx5_ib_cq *send_cq, *recv_cq;
1873         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1874         unsigned long flags;
1875         int err;
1876
1877         if (qp->ibqp.rwq_ind_tbl) {
1878                 destroy_rss_raw_qp_tir(dev, qp);
1879                 return;
1880         }
1881
1882         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1883                &qp->raw_packet_qp.rq.base :
1884                &qp->trans_qp.base;
1885
1886         if (qp->state != IB_QPS_RESET) {
1887                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1888                         mlx5_ib_qp_disable_pagefaults(qp);
1889                         err = mlx5_core_qp_modify(dev->mdev,
1890                                                   MLX5_CMD_OP_2RST_QP, 0,
1891                                                   NULL, &base->mqp);
1892                 } else {
1893                         err = modify_raw_packet_qp(dev, qp,
1894                                                    MLX5_CMD_OP_2RST_QP);
1895                 }
1896                 if (err)
1897                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1898                                      base->mqp.qpn);
1899         }
1900
1901         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1902                 &send_cq, &recv_cq);
1903
1904         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1905         mlx5_ib_lock_cqs(send_cq, recv_cq);
1906         /* del from lists under both locks above to protect reset flow paths */
1907         list_del(&qp->qps_list);
1908         if (send_cq)
1909                 list_del(&qp->cq_send_list);
1910
1911         if (recv_cq)
1912                 list_del(&qp->cq_recv_list);
1913
1914         if (qp->create_type == MLX5_QP_KERNEL) {
1915                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1916                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1917                 if (send_cq != recv_cq)
1918                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1919                                            NULL);
1920         }
1921         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1922         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1923
1924         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1925                 destroy_raw_packet_qp(dev, qp);
1926         } else {
1927                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1928                 if (err)
1929                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1930                                      base->mqp.qpn);
1931         }
1932
1933         if (qp->create_type == MLX5_QP_KERNEL)
1934                 destroy_qp_kernel(dev, qp);
1935         else if (qp->create_type == MLX5_QP_USER)
1936                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1937 }
1938
1939 static const char *ib_qp_type_str(enum ib_qp_type type)
1940 {
1941         switch (type) {
1942         case IB_QPT_SMI:
1943                 return "IB_QPT_SMI";
1944         case IB_QPT_GSI:
1945                 return "IB_QPT_GSI";
1946         case IB_QPT_RC:
1947                 return "IB_QPT_RC";
1948         case IB_QPT_UC:
1949                 return "IB_QPT_UC";
1950         case IB_QPT_UD:
1951                 return "IB_QPT_UD";
1952         case IB_QPT_RAW_IPV6:
1953                 return "IB_QPT_RAW_IPV6";
1954         case IB_QPT_RAW_ETHERTYPE:
1955                 return "IB_QPT_RAW_ETHERTYPE";
1956         case IB_QPT_XRC_INI:
1957                 return "IB_QPT_XRC_INI";
1958         case IB_QPT_XRC_TGT:
1959                 return "IB_QPT_XRC_TGT";
1960         case IB_QPT_RAW_PACKET:
1961                 return "IB_QPT_RAW_PACKET";
1962         case MLX5_IB_QPT_REG_UMR:
1963                 return "MLX5_IB_QPT_REG_UMR";
1964         case IB_QPT_MAX:
1965         default:
1966                 return "Invalid QP type";
1967         }
1968 }
1969
1970 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1971                                 struct ib_qp_init_attr *init_attr,
1972                                 struct ib_udata *udata)
1973 {
1974         struct mlx5_ib_dev *dev;
1975         struct mlx5_ib_qp *qp;
1976         u16 xrcdn = 0;
1977         int err;
1978
1979         if (pd) {
1980                 dev = to_mdev(pd->device);
1981
1982                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1983                         if (!pd->uobject) {
1984                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1985                                 return ERR_PTR(-EINVAL);
1986                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1987                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1988                                 return ERR_PTR(-EINVAL);
1989                         }
1990                 }
1991         } else {
1992                 /* being cautious here */
1993                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1994                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1995                         pr_warn("%s: no PD for transport %s\n", __func__,
1996                                 ib_qp_type_str(init_attr->qp_type));
1997                         return ERR_PTR(-EINVAL);
1998                 }
1999                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2000         }
2001
2002         switch (init_attr->qp_type) {
2003         case IB_QPT_XRC_TGT:
2004         case IB_QPT_XRC_INI:
2005                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2006                         mlx5_ib_dbg(dev, "XRC not supported\n");
2007                         return ERR_PTR(-ENOSYS);
2008                 }
2009                 init_attr->recv_cq = NULL;
2010                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2011                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2012                         init_attr->send_cq = NULL;
2013                 }
2014
2015                 /* fall through */
2016         case IB_QPT_RAW_PACKET:
2017         case IB_QPT_RC:
2018         case IB_QPT_UC:
2019         case IB_QPT_UD:
2020         case IB_QPT_SMI:
2021         case MLX5_IB_QPT_HW_GSI:
2022         case MLX5_IB_QPT_REG_UMR:
2023                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2024                 if (!qp)
2025                         return ERR_PTR(-ENOMEM);
2026
2027                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2028                 if (err) {
2029                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2030                         kfree(qp);
2031                         return ERR_PTR(err);
2032                 }
2033
2034                 if (is_qp0(init_attr->qp_type))
2035                         qp->ibqp.qp_num = 0;
2036                 else if (is_qp1(init_attr->qp_type))
2037                         qp->ibqp.qp_num = 1;
2038                 else
2039                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2040
2041                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2042                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2043                             to_mcq(init_attr->recv_cq)->mcq.cqn,
2044                             to_mcq(init_attr->send_cq)->mcq.cqn);
2045
2046                 qp->trans_qp.xrcdn = xrcdn;
2047
2048                 break;
2049
2050         case IB_QPT_GSI:
2051                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2052
2053         case IB_QPT_RAW_IPV6:
2054         case IB_QPT_RAW_ETHERTYPE:
2055         case IB_QPT_MAX:
2056         default:
2057                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2058                             init_attr->qp_type);
2059                 /* Don't support raw QPs */
2060                 return ERR_PTR(-EINVAL);
2061         }
2062
2063         return &qp->ibqp;
2064 }
2065
2066 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2067 {
2068         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2069         struct mlx5_ib_qp *mqp = to_mqp(qp);
2070
2071         if (unlikely(qp->qp_type == IB_QPT_GSI))
2072                 return mlx5_ib_gsi_destroy_qp(qp);
2073
2074         destroy_qp_common(dev, mqp);
2075
2076         kfree(mqp);
2077
2078         return 0;
2079 }
2080
2081 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2082                                    int attr_mask)
2083 {
2084         u32 hw_access_flags = 0;
2085         u8 dest_rd_atomic;
2086         u32 access_flags;
2087
2088         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2089                 dest_rd_atomic = attr->max_dest_rd_atomic;
2090         else
2091                 dest_rd_atomic = qp->trans_qp.resp_depth;
2092
2093         if (attr_mask & IB_QP_ACCESS_FLAGS)
2094                 access_flags = attr->qp_access_flags;
2095         else
2096                 access_flags = qp->trans_qp.atomic_rd_en;
2097
2098         if (!dest_rd_atomic)
2099                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2100
2101         if (access_flags & IB_ACCESS_REMOTE_READ)
2102                 hw_access_flags |= MLX5_QP_BIT_RRE;
2103         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2104                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2105         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2106                 hw_access_flags |= MLX5_QP_BIT_RWE;
2107
2108         return cpu_to_be32(hw_access_flags);
2109 }
2110
2111 enum {
2112         MLX5_PATH_FLAG_FL       = 1 << 0,
2113         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2114         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2115 };
2116
2117 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2118 {
2119         if (rate == IB_RATE_PORT_CURRENT) {
2120                 return 0;
2121         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2122                 return -EINVAL;
2123         } else {
2124                 while (rate != IB_RATE_2_5_GBPS &&
2125                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2126                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2127                         --rate;
2128         }
2129
2130         return rate + MLX5_STAT_RATE_OFFSET;
2131 }
2132
2133 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2134                                       struct mlx5_ib_sq *sq, u8 sl)
2135 {
2136         void *in;
2137         void *tisc;
2138         int inlen;
2139         int err;
2140
2141         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2142         in = mlx5_vzalloc(inlen);
2143         if (!in)
2144                 return -ENOMEM;
2145
2146         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2147
2148         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2149         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2150
2151         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2152
2153         kvfree(in);
2154
2155         return err;
2156 }
2157
2158 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2159                          const struct ib_ah_attr *ah,
2160                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2161                          u32 path_flags, const struct ib_qp_attr *attr,
2162                          bool alt)
2163 {
2164         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2165         int err;
2166
2167         if (attr_mask & IB_QP_PKEY_INDEX)
2168                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2169                                                      attr->pkey_index);
2170
2171         if (ah->ah_flags & IB_AH_GRH) {
2172                 if (ah->grh.sgid_index >=
2173                     dev->mdev->port_caps[port - 1].gid_table_len) {
2174                         pr_err("sgid_index (%u) too large. max is %d\n",
2175                                ah->grh.sgid_index,
2176                                dev->mdev->port_caps[port - 1].gid_table_len);
2177                         return -EINVAL;
2178                 }
2179         }
2180
2181         if (ll == IB_LINK_LAYER_ETHERNET) {
2182                 if (!(ah->ah_flags & IB_AH_GRH))
2183                         return -EINVAL;
2184                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2185                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2186                                                           ah->grh.sgid_index);
2187                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2188         } else {
2189                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2190                 path->fl_free_ar |=
2191                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2192                 path->rlid = cpu_to_be16(ah->dlid);
2193                 path->grh_mlid = ah->src_path_bits & 0x7f;
2194                 if (ah->ah_flags & IB_AH_GRH)
2195                         path->grh_mlid  |= 1 << 7;
2196                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2197         }
2198
2199         if (ah->ah_flags & IB_AH_GRH) {
2200                 path->mgid_index = ah->grh.sgid_index;
2201                 path->hop_limit  = ah->grh.hop_limit;
2202                 path->tclass_flowlabel =
2203                         cpu_to_be32((ah->grh.traffic_class << 20) |
2204                                     (ah->grh.flow_label));
2205                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2206         }
2207
2208         err = ib_rate_to_mlx5(dev, ah->static_rate);
2209         if (err < 0)
2210                 return err;
2211         path->static_rate = err;
2212         path->port = port;
2213
2214         if (attr_mask & IB_QP_TIMEOUT)
2215                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2216
2217         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2218                 return modify_raw_packet_eth_prio(dev->mdev,
2219                                                   &qp->raw_packet_qp.sq,
2220                                                   ah->sl & 0xf);
2221
2222         return 0;
2223 }
2224
2225 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2226         [MLX5_QP_STATE_INIT] = {
2227                 [MLX5_QP_STATE_INIT] = {
2228                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2229                                           MLX5_QP_OPTPAR_RAE            |
2230                                           MLX5_QP_OPTPAR_RWE            |
2231                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2232                                           MLX5_QP_OPTPAR_PRI_PORT,
2233                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2234                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2235                                           MLX5_QP_OPTPAR_PRI_PORT,
2236                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2237                                           MLX5_QP_OPTPAR_Q_KEY          |
2238                                           MLX5_QP_OPTPAR_PRI_PORT,
2239                 },
2240                 [MLX5_QP_STATE_RTR] = {
2241                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2242                                           MLX5_QP_OPTPAR_RRE            |
2243                                           MLX5_QP_OPTPAR_RAE            |
2244                                           MLX5_QP_OPTPAR_RWE            |
2245                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2246                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2247                                           MLX5_QP_OPTPAR_RWE            |
2248                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2249                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2250                                           MLX5_QP_OPTPAR_Q_KEY,
2251                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2252                                            MLX5_QP_OPTPAR_Q_KEY,
2253                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2254                                           MLX5_QP_OPTPAR_RRE            |
2255                                           MLX5_QP_OPTPAR_RAE            |
2256                                           MLX5_QP_OPTPAR_RWE            |
2257                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2258                 },
2259         },
2260         [MLX5_QP_STATE_RTR] = {
2261                 [MLX5_QP_STATE_RTS] = {
2262                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2263                                           MLX5_QP_OPTPAR_RRE            |
2264                                           MLX5_QP_OPTPAR_RAE            |
2265                                           MLX5_QP_OPTPAR_RWE            |
2266                                           MLX5_QP_OPTPAR_PM_STATE       |
2267                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2268                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2269                                           MLX5_QP_OPTPAR_RWE            |
2270                                           MLX5_QP_OPTPAR_PM_STATE,
2271                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2272                 },
2273         },
2274         [MLX5_QP_STATE_RTS] = {
2275                 [MLX5_QP_STATE_RTS] = {
2276                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2277                                           MLX5_QP_OPTPAR_RAE            |
2278                                           MLX5_QP_OPTPAR_RWE            |
2279                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2280                                           MLX5_QP_OPTPAR_PM_STATE       |
2281                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2282                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2283                                           MLX5_QP_OPTPAR_PM_STATE       |
2284                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2285                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2286                                           MLX5_QP_OPTPAR_SRQN           |
2287                                           MLX5_QP_OPTPAR_CQN_RCV,
2288                 },
2289         },
2290         [MLX5_QP_STATE_SQER] = {
2291                 [MLX5_QP_STATE_RTS] = {
2292                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2293                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2294                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2295                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2296                                            MLX5_QP_OPTPAR_RWE           |
2297                                            MLX5_QP_OPTPAR_RAE           |
2298                                            MLX5_QP_OPTPAR_RRE,
2299                 },
2300         },
2301 };
2302
2303 static int ib_nr_to_mlx5_nr(int ib_mask)
2304 {
2305         switch (ib_mask) {
2306         case IB_QP_STATE:
2307                 return 0;
2308         case IB_QP_CUR_STATE:
2309                 return 0;
2310         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2311                 return 0;
2312         case IB_QP_ACCESS_FLAGS:
2313                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2314                         MLX5_QP_OPTPAR_RAE;
2315         case IB_QP_PKEY_INDEX:
2316                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2317         case IB_QP_PORT:
2318                 return MLX5_QP_OPTPAR_PRI_PORT;
2319         case IB_QP_QKEY:
2320                 return MLX5_QP_OPTPAR_Q_KEY;
2321         case IB_QP_AV:
2322                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2323                         MLX5_QP_OPTPAR_PRI_PORT;
2324         case IB_QP_PATH_MTU:
2325                 return 0;
2326         case IB_QP_TIMEOUT:
2327                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2328         case IB_QP_RETRY_CNT:
2329                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2330         case IB_QP_RNR_RETRY:
2331                 return MLX5_QP_OPTPAR_RNR_RETRY;
2332         case IB_QP_RQ_PSN:
2333                 return 0;
2334         case IB_QP_MAX_QP_RD_ATOMIC:
2335                 return MLX5_QP_OPTPAR_SRA_MAX;
2336         case IB_QP_ALT_PATH:
2337                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2338         case IB_QP_MIN_RNR_TIMER:
2339                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2340         case IB_QP_SQ_PSN:
2341                 return 0;
2342         case IB_QP_MAX_DEST_RD_ATOMIC:
2343                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2344                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2345         case IB_QP_PATH_MIG_STATE:
2346                 return MLX5_QP_OPTPAR_PM_STATE;
2347         case IB_QP_CAP:
2348                 return 0;
2349         case IB_QP_DEST_QPN:
2350                 return 0;
2351         }
2352         return 0;
2353 }
2354
2355 static int ib_mask_to_mlx5_opt(int ib_mask)
2356 {
2357         int result = 0;
2358         int i;
2359
2360         for (i = 0; i < 8 * sizeof(int); i++) {
2361                 if ((1 << i) & ib_mask)
2362                         result |= ib_nr_to_mlx5_nr(1 << i);
2363         }
2364
2365         return result;
2366 }
2367
2368 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2369                                    struct mlx5_ib_rq *rq, int new_state)
2370 {
2371         void *in;
2372         void *rqc;
2373         int inlen;
2374         int err;
2375
2376         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2377         in = mlx5_vzalloc(inlen);
2378         if (!in)
2379                 return -ENOMEM;
2380
2381         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2382
2383         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2384         MLX5_SET(rqc, rqc, state, new_state);
2385
2386         err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2387         if (err)
2388                 goto out;
2389
2390         rq->state = new_state;
2391
2392 out:
2393         kvfree(in);
2394         return err;
2395 }
2396
2397 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2398                                    struct mlx5_ib_sq *sq, int new_state)
2399 {
2400         void *in;
2401         void *sqc;
2402         int inlen;
2403         int err;
2404
2405         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2406         in = mlx5_vzalloc(inlen);
2407         if (!in)
2408                 return -ENOMEM;
2409
2410         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2411
2412         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2413         MLX5_SET(sqc, sqc, state, new_state);
2414
2415         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2416         if (err)
2417                 goto out;
2418
2419         sq->state = new_state;
2420
2421 out:
2422         kvfree(in);
2423         return err;
2424 }
2425
2426 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2427                                 u16 operation)
2428 {
2429         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2430         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2431         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2432         int rq_state;
2433         int sq_state;
2434         int err;
2435
2436         switch (operation) {
2437         case MLX5_CMD_OP_RST2INIT_QP:
2438                 rq_state = MLX5_RQC_STATE_RDY;
2439                 sq_state = MLX5_SQC_STATE_RDY;
2440                 break;
2441         case MLX5_CMD_OP_2ERR_QP:
2442                 rq_state = MLX5_RQC_STATE_ERR;
2443                 sq_state = MLX5_SQC_STATE_ERR;
2444                 break;
2445         case MLX5_CMD_OP_2RST_QP:
2446                 rq_state = MLX5_RQC_STATE_RST;
2447                 sq_state = MLX5_SQC_STATE_RST;
2448                 break;
2449         case MLX5_CMD_OP_INIT2INIT_QP:
2450         case MLX5_CMD_OP_INIT2RTR_QP:
2451         case MLX5_CMD_OP_RTR2RTS_QP:
2452         case MLX5_CMD_OP_RTS2RTS_QP:
2453                 /* Nothing to do here... */
2454                 return 0;
2455         default:
2456                 WARN_ON(1);
2457                 return -EINVAL;
2458         }
2459
2460         if (qp->rq.wqe_cnt) {
2461                 err =  modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2462                 if (err)
2463                         return err;
2464         }
2465
2466         if (qp->sq.wqe_cnt)
2467                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2468
2469         return 0;
2470 }
2471
2472 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2473                                const struct ib_qp_attr *attr, int attr_mask,
2474                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2475 {
2476         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2477                 [MLX5_QP_STATE_RST] = {
2478                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2479                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2480                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2481                 },
2482                 [MLX5_QP_STATE_INIT]  = {
2483                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2484                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2485                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2486                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2487                 },
2488                 [MLX5_QP_STATE_RTR]   = {
2489                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2490                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2491                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2492                 },
2493                 [MLX5_QP_STATE_RTS]   = {
2494                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2495                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2496                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2497                 },
2498                 [MLX5_QP_STATE_SQD] = {
2499                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2500                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2501                 },
2502                 [MLX5_QP_STATE_SQER] = {
2503                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2504                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2505                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2506                 },
2507                 [MLX5_QP_STATE_ERR] = {
2508                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2509                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2510                 }
2511         };
2512
2513         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2514         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2515         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2516         struct mlx5_ib_cq *send_cq, *recv_cq;
2517         struct mlx5_qp_context *context;
2518         struct mlx5_ib_pd *pd;
2519         enum mlx5_qp_state mlx5_cur, mlx5_new;
2520         enum mlx5_qp_optpar optpar;
2521         int sqd_event;
2522         int mlx5_st;
2523         int err;
2524         u16 op;
2525
2526         context = kzalloc(sizeof(*context), GFP_KERNEL);
2527         if (!context)
2528                 return -ENOMEM;
2529
2530         err = to_mlx5_st(ibqp->qp_type);
2531         if (err < 0) {
2532                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2533                 goto out;
2534         }
2535
2536         context->flags = cpu_to_be32(err << 16);
2537
2538         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2539                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2540         } else {
2541                 switch (attr->path_mig_state) {
2542                 case IB_MIG_MIGRATED:
2543                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2544                         break;
2545                 case IB_MIG_REARM:
2546                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2547                         break;
2548                 case IB_MIG_ARMED:
2549                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2550                         break;
2551                 }
2552         }
2553
2554         if (is_sqp(ibqp->qp_type)) {
2555                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2556         } else if (ibqp->qp_type == IB_QPT_UD ||
2557                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2558                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2559         } else if (attr_mask & IB_QP_PATH_MTU) {
2560                 if (attr->path_mtu < IB_MTU_256 ||
2561                     attr->path_mtu > IB_MTU_4096) {
2562                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2563                         err = -EINVAL;
2564                         goto out;
2565                 }
2566                 context->mtu_msgmax = (attr->path_mtu << 5) |
2567                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2568         }
2569
2570         if (attr_mask & IB_QP_DEST_QPN)
2571                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2572
2573         if (attr_mask & IB_QP_PKEY_INDEX)
2574                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2575
2576         /* todo implement counter_index functionality */
2577
2578         if (is_sqp(ibqp->qp_type))
2579                 context->pri_path.port = qp->port;
2580
2581         if (attr_mask & IB_QP_PORT)
2582                 context->pri_path.port = attr->port_num;
2583
2584         if (attr_mask & IB_QP_AV) {
2585                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2586                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2587                                     attr_mask, 0, attr, false);
2588                 if (err)
2589                         goto out;
2590         }
2591
2592         if (attr_mask & IB_QP_TIMEOUT)
2593                 context->pri_path.ackto_lt |= attr->timeout << 3;
2594
2595         if (attr_mask & IB_QP_ALT_PATH) {
2596                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2597                                     &context->alt_path,
2598                                     attr->alt_port_num,
2599                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2600                                     0, attr, true);
2601                 if (err)
2602                         goto out;
2603         }
2604
2605         pd = get_pd(qp);
2606         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2607                 &send_cq, &recv_cq);
2608
2609         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2610         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2611         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2612         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2613
2614         if (attr_mask & IB_QP_RNR_RETRY)
2615                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2616
2617         if (attr_mask & IB_QP_RETRY_CNT)
2618                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2619
2620         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2621                 if (attr->max_rd_atomic)
2622                         context->params1 |=
2623                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2624         }
2625
2626         if (attr_mask & IB_QP_SQ_PSN)
2627                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2628
2629         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2630                 if (attr->max_dest_rd_atomic)
2631                         context->params2 |=
2632                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2633         }
2634
2635         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2636                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2637
2638         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2639                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2640
2641         if (attr_mask & IB_QP_RQ_PSN)
2642                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2643
2644         if (attr_mask & IB_QP_QKEY)
2645                 context->qkey = cpu_to_be32(attr->qkey);
2646
2647         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2648                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2649
2650         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2651             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2652                 sqd_event = 1;
2653         else
2654                 sqd_event = 0;
2655
2656         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2657                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2658                                qp->port) - 1;
2659                 struct mlx5_ib_port *mibport = &dev->port[port_num];
2660
2661                 context->qp_counter_set_usr_page |=
2662                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2663         }
2664
2665         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2666                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2667
2668         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2669                 context->deth_sqpn = cpu_to_be32(1);
2670
2671         mlx5_cur = to_mlx5_state(cur_state);
2672         mlx5_new = to_mlx5_state(new_state);
2673         mlx5_st = to_mlx5_st(ibqp->qp_type);
2674         if (mlx5_st < 0)
2675                 goto out;
2676
2677         /* If moving to a reset or error state, we must disable page faults on
2678          * this QP and flush all current page faults. Otherwise a stale page
2679          * fault may attempt to work on this QP after it is reset and moved
2680          * again to RTS, and may cause the driver and the device to get out of
2681          * sync. */
2682         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2683             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2684             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2685                 mlx5_ib_qp_disable_pagefaults(qp);
2686
2687         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2688             !optab[mlx5_cur][mlx5_new])
2689                 goto out;
2690
2691         op = optab[mlx5_cur][mlx5_new];
2692         optpar = ib_mask_to_mlx5_opt(attr_mask);
2693         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2694
2695         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2696                 err = modify_raw_packet_qp(dev, qp, op);
2697         else
2698                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2699                                           &base->mqp);
2700         if (err)
2701                 goto out;
2702
2703         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2704             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2705                 mlx5_ib_qp_enable_pagefaults(qp);
2706
2707         qp->state = new_state;
2708
2709         if (attr_mask & IB_QP_ACCESS_FLAGS)
2710                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2711         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2712                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2713         if (attr_mask & IB_QP_PORT)
2714                 qp->port = attr->port_num;
2715         if (attr_mask & IB_QP_ALT_PATH)
2716                 qp->trans_qp.alt_port = attr->alt_port_num;
2717
2718         /*
2719          * If we moved a kernel QP to RESET, clean up all old CQ
2720          * entries and reinitialize the QP.
2721          */
2722         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2723                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2724                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2725                 if (send_cq != recv_cq)
2726                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2727
2728                 qp->rq.head = 0;
2729                 qp->rq.tail = 0;
2730                 qp->sq.head = 0;
2731                 qp->sq.tail = 0;
2732                 qp->sq.cur_post = 0;
2733                 qp->sq.last_poll = 0;
2734                 qp->db.db[MLX5_RCV_DBR] = 0;
2735                 qp->db.db[MLX5_SND_DBR] = 0;
2736         }
2737
2738 out:
2739         kfree(context);
2740         return err;
2741 }
2742
2743 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2744                       int attr_mask, struct ib_udata *udata)
2745 {
2746         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2747         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2748         enum ib_qp_type qp_type;
2749         enum ib_qp_state cur_state, new_state;
2750         int err = -EINVAL;
2751         int port;
2752         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2753
2754         if (ibqp->rwq_ind_tbl)
2755                 return -ENOSYS;
2756
2757         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2758                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2759
2760         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2761                 IB_QPT_GSI : ibqp->qp_type;
2762
2763         mutex_lock(&qp->mutex);
2764
2765         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2766         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2767
2768         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2769                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2770                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2771         }
2772
2773         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2774             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2775                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2776                             cur_state, new_state, ibqp->qp_type, attr_mask);
2777                 goto out;
2778         }
2779
2780         if ((attr_mask & IB_QP_PORT) &&
2781             (attr->port_num == 0 ||
2782              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2783                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2784                             attr->port_num, dev->num_ports);
2785                 goto out;
2786         }
2787
2788         if (attr_mask & IB_QP_PKEY_INDEX) {
2789                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2790                 if (attr->pkey_index >=
2791                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2792                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2793                                     attr->pkey_index);
2794                         goto out;
2795                 }
2796         }
2797
2798         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2799             attr->max_rd_atomic >
2800             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2801                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2802                             attr->max_rd_atomic);
2803                 goto out;
2804         }
2805
2806         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2807             attr->max_dest_rd_atomic >
2808             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2809                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2810                             attr->max_dest_rd_atomic);
2811                 goto out;
2812         }
2813
2814         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2815                 err = 0;
2816                 goto out;
2817         }
2818
2819         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2820
2821 out:
2822         mutex_unlock(&qp->mutex);
2823         return err;
2824 }
2825
2826 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2827 {
2828         struct mlx5_ib_cq *cq;
2829         unsigned cur;
2830
2831         cur = wq->head - wq->tail;
2832         if (likely(cur + nreq < wq->max_post))
2833                 return 0;
2834
2835         cq = to_mcq(ib_cq);
2836         spin_lock(&cq->lock);
2837         cur = wq->head - wq->tail;
2838         spin_unlock(&cq->lock);
2839
2840         return cur + nreq >= wq->max_post;
2841 }
2842
2843 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2844                                           u64 remote_addr, u32 rkey)
2845 {
2846         rseg->raddr    = cpu_to_be64(remote_addr);
2847         rseg->rkey     = cpu_to_be32(rkey);
2848         rseg->reserved = 0;
2849 }
2850
2851 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2852                          struct ib_send_wr *wr, void *qend,
2853                          struct mlx5_ib_qp *qp, int *size)
2854 {
2855         void *seg = eseg;
2856
2857         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2858
2859         if (wr->send_flags & IB_SEND_IP_CSUM)
2860                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2861                                  MLX5_ETH_WQE_L4_CSUM;
2862
2863         seg += sizeof(struct mlx5_wqe_eth_seg);
2864         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2865
2866         if (wr->opcode == IB_WR_LSO) {
2867                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2868                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2869                 u64 left, leftlen, copysz;
2870                 void *pdata = ud_wr->header;
2871
2872                 left = ud_wr->hlen;
2873                 eseg->mss = cpu_to_be16(ud_wr->mss);
2874                 eseg->inline_hdr_sz = cpu_to_be16(left);
2875
2876                 /*
2877                  * check if there is space till the end of queue, if yes,
2878                  * copy all in one shot, otherwise copy till the end of queue,
2879                  * rollback and than the copy the left
2880                  */
2881                 leftlen = qend - (void *)eseg->inline_hdr_start;
2882                 copysz = min_t(u64, leftlen, left);
2883
2884                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2885
2886                 if (likely(copysz > size_of_inl_hdr_start)) {
2887                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2888                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2889                 }
2890
2891                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2892                         seg = mlx5_get_send_wqe(qp, 0);
2893                         left -= copysz;
2894                         pdata += copysz;
2895                         memcpy(seg, pdata, left);
2896                         seg += ALIGN(left, 16);
2897                         *size += ALIGN(left, 16) / 16;
2898                 }
2899         }
2900
2901         return seg;
2902 }
2903
2904 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2905                              struct ib_send_wr *wr)
2906 {
2907         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2908         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2909         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2910 }
2911
2912 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2913 {
2914         dseg->byte_count = cpu_to_be32(sg->length);
2915         dseg->lkey       = cpu_to_be32(sg->lkey);
2916         dseg->addr       = cpu_to_be64(sg->addr);
2917 }
2918
2919 static __be16 get_klm_octo(int npages)
2920 {
2921         return cpu_to_be16(ALIGN(npages, 8) / 2);
2922 }
2923
2924 static __be64 frwr_mkey_mask(void)
2925 {
2926         u64 result;
2927
2928         result = MLX5_MKEY_MASK_LEN             |
2929                 MLX5_MKEY_MASK_PAGE_SIZE        |
2930                 MLX5_MKEY_MASK_START_ADDR       |
2931                 MLX5_MKEY_MASK_EN_RINVAL        |
2932                 MLX5_MKEY_MASK_KEY              |
2933                 MLX5_MKEY_MASK_LR               |
2934                 MLX5_MKEY_MASK_LW               |
2935                 MLX5_MKEY_MASK_RR               |
2936                 MLX5_MKEY_MASK_RW               |
2937                 MLX5_MKEY_MASK_A                |
2938                 MLX5_MKEY_MASK_SMALL_FENCE      |
2939                 MLX5_MKEY_MASK_FREE;
2940
2941         return cpu_to_be64(result);
2942 }
2943
2944 static __be64 sig_mkey_mask(void)
2945 {
2946         u64 result;
2947
2948         result = MLX5_MKEY_MASK_LEN             |
2949                 MLX5_MKEY_MASK_PAGE_SIZE        |
2950                 MLX5_MKEY_MASK_START_ADDR       |
2951                 MLX5_MKEY_MASK_EN_SIGERR        |
2952                 MLX5_MKEY_MASK_EN_RINVAL        |
2953                 MLX5_MKEY_MASK_KEY              |
2954                 MLX5_MKEY_MASK_LR               |
2955                 MLX5_MKEY_MASK_LW               |
2956                 MLX5_MKEY_MASK_RR               |
2957                 MLX5_MKEY_MASK_RW               |
2958                 MLX5_MKEY_MASK_SMALL_FENCE      |
2959                 MLX5_MKEY_MASK_FREE             |
2960                 MLX5_MKEY_MASK_BSF_EN;
2961
2962         return cpu_to_be64(result);
2963 }
2964
2965 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2966                                 struct mlx5_ib_mr *mr)
2967 {
2968         int ndescs = mr->ndescs;
2969
2970         memset(umr, 0, sizeof(*umr));
2971
2972         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
2973                 /* KLMs take twice the size of MTTs */
2974                 ndescs *= 2;
2975
2976         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2977         umr->klm_octowords = get_klm_octo(ndescs);
2978         umr->mkey_mask = frwr_mkey_mask();
2979 }
2980
2981 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2982 {
2983         memset(umr, 0, sizeof(*umr));
2984         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2985         umr->flags = 1 << 7;
2986 }
2987
2988 static __be64 get_umr_reg_mr_mask(void)
2989 {
2990         u64 result;
2991
2992         result = MLX5_MKEY_MASK_LEN             |
2993                  MLX5_MKEY_MASK_PAGE_SIZE       |
2994                  MLX5_MKEY_MASK_START_ADDR      |
2995                  MLX5_MKEY_MASK_PD              |
2996                  MLX5_MKEY_MASK_LR              |
2997                  MLX5_MKEY_MASK_LW              |
2998                  MLX5_MKEY_MASK_KEY             |
2999                  MLX5_MKEY_MASK_RR              |
3000                  MLX5_MKEY_MASK_RW              |
3001                  MLX5_MKEY_MASK_A               |
3002                  MLX5_MKEY_MASK_FREE;
3003
3004         return cpu_to_be64(result);
3005 }
3006
3007 static __be64 get_umr_unreg_mr_mask(void)
3008 {
3009         u64 result;
3010
3011         result = MLX5_MKEY_MASK_FREE;
3012
3013         return cpu_to_be64(result);
3014 }
3015
3016 static __be64 get_umr_update_mtt_mask(void)
3017 {
3018         u64 result;
3019
3020         result = MLX5_MKEY_MASK_FREE;
3021
3022         return cpu_to_be64(result);
3023 }
3024
3025 static __be64 get_umr_update_translation_mask(void)
3026 {
3027         u64 result;
3028
3029         result = MLX5_MKEY_MASK_LEN |
3030                  MLX5_MKEY_MASK_PAGE_SIZE |
3031                  MLX5_MKEY_MASK_START_ADDR |
3032                  MLX5_MKEY_MASK_KEY |
3033                  MLX5_MKEY_MASK_FREE;
3034
3035         return cpu_to_be64(result);
3036 }
3037
3038 static __be64 get_umr_update_access_mask(void)
3039 {
3040         u64 result;
3041
3042         result = MLX5_MKEY_MASK_LW |
3043                  MLX5_MKEY_MASK_RR |
3044                  MLX5_MKEY_MASK_RW |
3045                  MLX5_MKEY_MASK_A |
3046                  MLX5_MKEY_MASK_KEY |
3047                  MLX5_MKEY_MASK_FREE;
3048
3049         return cpu_to_be64(result);
3050 }
3051
3052 static __be64 get_umr_update_pd_mask(void)
3053 {
3054         u64 result;
3055
3056         result = MLX5_MKEY_MASK_PD |
3057                  MLX5_MKEY_MASK_KEY |
3058                  MLX5_MKEY_MASK_FREE;
3059
3060         return cpu_to_be64(result);
3061 }
3062
3063 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3064                                 struct ib_send_wr *wr)
3065 {
3066         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3067
3068         memset(umr, 0, sizeof(*umr));
3069
3070         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3071                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3072         else
3073                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3074
3075         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3076                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3077                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3078                         umr->mkey_mask = get_umr_update_mtt_mask();
3079                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3080                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3081                 }
3082                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3083                         umr->mkey_mask |= get_umr_update_translation_mask();
3084                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3085                         umr->mkey_mask |= get_umr_update_access_mask();
3086                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3087                         umr->mkey_mask |= get_umr_update_pd_mask();
3088                 if (!umr->mkey_mask)
3089                         umr->mkey_mask = get_umr_reg_mr_mask();
3090         } else {
3091                 umr->mkey_mask = get_umr_unreg_mr_mask();
3092         }
3093
3094         if (!wr->num_sge)
3095                 umr->flags |= MLX5_UMR_INLINE;
3096 }
3097
3098 static u8 get_umr_flags(int acc)
3099 {
3100         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3101                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3102                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3103                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3104                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3105 }
3106
3107 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3108                              struct mlx5_ib_mr *mr,
3109                              u32 key, int access)
3110 {
3111         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3112
3113         memset(seg, 0, sizeof(*seg));
3114
3115         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3116                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3117         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3118                 /* KLMs take twice the size of MTTs */
3119                 ndescs *= 2;
3120
3121         seg->flags = get_umr_flags(access) | mr->access_mode;
3122         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3123         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3124         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3125         seg->len = cpu_to_be64(mr->ibmr.length);
3126         seg->xlt_oct_size = cpu_to_be32(ndescs);
3127 }
3128
3129 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3130 {
3131         memset(seg, 0, sizeof(*seg));
3132         seg->status = MLX5_MKEY_STATUS_FREE;
3133 }
3134
3135 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3136 {
3137         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3138
3139         memset(seg, 0, sizeof(*seg));
3140         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3141                 seg->status = MLX5_MKEY_STATUS_FREE;
3142                 return;
3143         }
3144
3145         seg->flags = convert_access(umrwr->access_flags);
3146         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3147                 if (umrwr->pd)
3148                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3149                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3150         }
3151         seg->len = cpu_to_be64(umrwr->length);
3152         seg->log2_page_size = umrwr->page_shift;
3153         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3154                                        mlx5_mkey_variant(umrwr->mkey));
3155 }
3156
3157 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3158                              struct mlx5_ib_mr *mr,
3159                              struct mlx5_ib_pd *pd)
3160 {
3161         int bcount = mr->desc_size * mr->ndescs;
3162
3163         dseg->addr = cpu_to_be64(mr->desc_map);
3164         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3165         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3166 }
3167
3168 static __be32 send_ieth(struct ib_send_wr *wr)
3169 {
3170         switch (wr->opcode) {
3171         case IB_WR_SEND_WITH_IMM:
3172         case IB_WR_RDMA_WRITE_WITH_IMM:
3173                 return wr->ex.imm_data;
3174
3175         case IB_WR_SEND_WITH_INV:
3176                 return cpu_to_be32(wr->ex.invalidate_rkey);
3177
3178         default:
3179                 return 0;
3180         }
3181 }
3182
3183 static u8 calc_sig(void *wqe, int size)
3184 {
3185         u8 *p = wqe;
3186         u8 res = 0;
3187         int i;
3188
3189         for (i = 0; i < size; i++)
3190                 res ^= p[i];
3191
3192         return ~res;
3193 }
3194
3195 static u8 wq_sig(void *wqe)
3196 {
3197         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3198 }
3199
3200 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3201                             void *wqe, int *sz)
3202 {
3203         struct mlx5_wqe_inline_seg *seg;
3204         void *qend = qp->sq.qend;
3205         void *addr;
3206         int inl = 0;
3207         int copy;
3208         int len;
3209         int i;
3210
3211         seg = wqe;
3212         wqe += sizeof(*seg);
3213         for (i = 0; i < wr->num_sge; i++) {
3214                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3215                 len  = wr->sg_list[i].length;
3216                 inl += len;
3217
3218                 if (unlikely(inl > qp->max_inline_data))
3219                         return -ENOMEM;
3220
3221                 if (unlikely(wqe + len > qend)) {
3222                         copy = qend - wqe;
3223                         memcpy(wqe, addr, copy);
3224                         addr += copy;
3225                         len -= copy;
3226                         wqe = mlx5_get_send_wqe(qp, 0);
3227                 }
3228                 memcpy(wqe, addr, len);
3229                 wqe += len;
3230         }
3231
3232         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3233
3234         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3235
3236         return 0;
3237 }
3238
3239 static u16 prot_field_size(enum ib_signature_type type)
3240 {
3241         switch (type) {
3242         case IB_SIG_TYPE_T10_DIF:
3243                 return MLX5_DIF_SIZE;
3244         default:
3245                 return 0;
3246         }
3247 }
3248
3249 static u8 bs_selector(int block_size)
3250 {
3251         switch (block_size) {
3252         case 512:           return 0x1;
3253         case 520:           return 0x2;
3254         case 4096:          return 0x3;
3255         case 4160:          return 0x4;
3256         case 1073741824:    return 0x5;
3257         default:            return 0;
3258         }
3259 }
3260
3261 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3262                               struct mlx5_bsf_inl *inl)
3263 {
3264         /* Valid inline section and allow BSF refresh */
3265         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3266                                        MLX5_BSF_REFRESH_DIF);
3267         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3268         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3269         /* repeating block */
3270         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3271         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3272                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3273
3274         if (domain->sig.dif.ref_remap)
3275                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3276
3277         if (domain->sig.dif.app_escape) {
3278                 if (domain->sig.dif.ref_escape)
3279                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3280                 else
3281                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3282         }
3283
3284         inl->dif_app_bitmask_check =
3285                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3286 }
3287
3288 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3289                         struct ib_sig_attrs *sig_attrs,
3290                         struct mlx5_bsf *bsf, u32 data_size)
3291 {
3292         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3293         struct mlx5_bsf_basic *basic = &bsf->basic;
3294         struct ib_sig_domain *mem = &sig_attrs->mem;
3295         struct ib_sig_domain *wire = &sig_attrs->wire;
3296
3297         memset(bsf, 0, sizeof(*bsf));
3298
3299         /* Basic + Extended + Inline */
3300         basic->bsf_size_sbs = 1 << 7;
3301         /* Input domain check byte mask */
3302         basic->check_byte_mask = sig_attrs->check_mask;
3303         basic->raw_data_size = cpu_to_be32(data_size);
3304
3305         /* Memory domain */
3306         switch (sig_attrs->mem.sig_type) {
3307         case IB_SIG_TYPE_NONE:
3308                 break;
3309         case IB_SIG_TYPE_T10_DIF:
3310                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3311                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3312                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3313                 break;
3314         default:
3315                 return -EINVAL;
3316         }
3317
3318         /* Wire domain */
3319         switch (sig_attrs->wire.sig_type) {
3320         case IB_SIG_TYPE_NONE:
3321                 break;
3322         case IB_SIG_TYPE_T10_DIF:
3323                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3324                     mem->sig_type == wire->sig_type) {
3325                         /* Same block structure */
3326                         basic->bsf_size_sbs |= 1 << 4;
3327                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3328                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3329                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3330                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3331                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3332                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3333                 } else
3334                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3335
3336                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3337                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3338                 break;
3339         default:
3340                 return -EINVAL;
3341         }
3342
3343         return 0;
3344 }
3345
3346 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3347                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3348 {
3349         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3350         struct ib_mr *sig_mr = wr->sig_mr;
3351         struct mlx5_bsf *bsf;
3352         u32 data_len = wr->wr.sg_list->length;
3353         u32 data_key = wr->wr.sg_list->lkey;
3354         u64 data_va = wr->wr.sg_list->addr;
3355         int ret;
3356         int wqe_size;
3357
3358         if (!wr->prot ||
3359             (data_key == wr->prot->lkey &&
3360              data_va == wr->prot->addr &&
3361              data_len == wr->prot->length)) {
3362                 /**
3363                  * Source domain doesn't contain signature information
3364                  * or data and protection are interleaved in memory.
3365                  * So need construct:
3366                  *                  ------------------
3367                  *                 |     data_klm     |
3368                  *                  ------------------
3369                  *                 |       BSF        |
3370                  *                  ------------------
3371                  **/
3372                 struct mlx5_klm *data_klm = *seg;
3373
3374                 data_klm->bcount = cpu_to_be32(data_len);
3375                 data_klm->key = cpu_to_be32(data_key);
3376                 data_klm->va = cpu_to_be64(data_va);
3377                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3378         } else {
3379                 /**
3380                  * Source domain contains signature information
3381                  * So need construct a strided block format:
3382                  *               ---------------------------
3383                  *              |     stride_block_ctrl     |
3384                  *               ---------------------------
3385                  *              |          data_klm         |
3386                  *               ---------------------------
3387                  *              |          prot_klm         |
3388                  *               ---------------------------
3389                  *              |             BSF           |
3390                  *               ---------------------------
3391                  **/
3392                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3393                 struct mlx5_stride_block_entry *data_sentry;
3394                 struct mlx5_stride_block_entry *prot_sentry;
3395                 u32 prot_key = wr->prot->lkey;
3396                 u64 prot_va = wr->prot->addr;
3397                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3398                 int prot_size;
3399
3400                 sblock_ctrl = *seg;
3401                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3402                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3403
3404                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3405                 if (!prot_size) {
3406                         pr_err("Bad block size given: %u\n", block_size);
3407                         return -EINVAL;
3408                 }
3409                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3410                                                             prot_size);
3411                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3412                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3413                 sblock_ctrl->num_entries = cpu_to_be16(2);
3414
3415                 data_sentry->bcount = cpu_to_be16(block_size);
3416                 data_sentry->key = cpu_to_be32(data_key);
3417                 data_sentry->va = cpu_to_be64(data_va);
3418                 data_sentry->stride = cpu_to_be16(block_size);
3419
3420                 prot_sentry->bcount = cpu_to_be16(prot_size);
3421                 prot_sentry->key = cpu_to_be32(prot_key);
3422                 prot_sentry->va = cpu_to_be64(prot_va);
3423                 prot_sentry->stride = cpu_to_be16(prot_size);
3424
3425                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3426                                  sizeof(*prot_sentry), 64);
3427         }
3428
3429         *seg += wqe_size;
3430         *size += wqe_size / 16;
3431         if (unlikely((*seg == qp->sq.qend)))
3432                 *seg = mlx5_get_send_wqe(qp, 0);
3433
3434         bsf = *seg;
3435         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3436         if (ret)
3437                 return -EINVAL;
3438
3439         *seg += sizeof(*bsf);
3440         *size += sizeof(*bsf) / 16;
3441         if (unlikely((*seg == qp->sq.qend)))
3442                 *seg = mlx5_get_send_wqe(qp, 0);
3443
3444         return 0;
3445 }
3446
3447 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3448                                  struct ib_sig_handover_wr *wr, u32 nelements,
3449                                  u32 length, u32 pdn)
3450 {
3451         struct ib_mr *sig_mr = wr->sig_mr;
3452         u32 sig_key = sig_mr->rkey;
3453         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3454
3455         memset(seg, 0, sizeof(*seg));
3456
3457         seg->flags = get_umr_flags(wr->access_flags) |
3458                                    MLX5_MKC_ACCESS_MODE_KLMS;
3459         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3460         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3461                                     MLX5_MKEY_BSF_EN | pdn);
3462         seg->len = cpu_to_be64(length);
3463         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3464         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3465 }
3466
3467 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3468                                 u32 nelements)
3469 {
3470         memset(umr, 0, sizeof(*umr));
3471
3472         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3473         umr->klm_octowords = get_klm_octo(nelements);
3474         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3475         umr->mkey_mask = sig_mkey_mask();
3476 }
3477
3478
3479 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3480                           void **seg, int *size)
3481 {
3482         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3483         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3484         u32 pdn = get_pd(qp)->pdn;
3485         u32 klm_oct_size;
3486         int region_len, ret;
3487
3488         if (unlikely(wr->wr.num_sge != 1) ||
3489             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3490             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3491             unlikely(!sig_mr->sig->sig_status_checked))
3492                 return -EINVAL;
3493
3494         /* length of the protected region, data + protection */
3495         region_len = wr->wr.sg_list->length;
3496         if (wr->prot &&
3497             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3498              wr->prot->addr != wr->wr.sg_list->addr  ||
3499              wr->prot->length != wr->wr.sg_list->length))
3500                 region_len += wr->prot->length;
3501
3502         /**
3503          * KLM octoword size - if protection was provided
3504          * then we use strided block format (3 octowords),
3505          * else we use single KLM (1 octoword)
3506          **/
3507         klm_oct_size = wr->prot ? 3 : 1;
3508
3509         set_sig_umr_segment(*seg, klm_oct_size);
3510         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3511         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3512         if (unlikely((*seg == qp->sq.qend)))
3513                 *seg = mlx5_get_send_wqe(qp, 0);
3514
3515         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3516         *seg += sizeof(struct mlx5_mkey_seg);
3517         *size += sizeof(struct mlx5_mkey_seg) / 16;
3518         if (unlikely((*seg == qp->sq.qend)))
3519                 *seg = mlx5_get_send_wqe(qp, 0);
3520
3521         ret = set_sig_data_segment(wr, qp, seg, size);
3522         if (ret)
3523                 return ret;
3524
3525         sig_mr->sig->sig_status_checked = false;
3526         return 0;
3527 }
3528
3529 static int set_psv_wr(struct ib_sig_domain *domain,
3530                       u32 psv_idx, void **seg, int *size)
3531 {
3532         struct mlx5_seg_set_psv *psv_seg = *seg;
3533
3534         memset(psv_seg, 0, sizeof(*psv_seg));
3535         psv_seg->psv_num = cpu_to_be32(psv_idx);
3536         switch (domain->sig_type) {
3537         case IB_SIG_TYPE_NONE:
3538                 break;
3539         case IB_SIG_TYPE_T10_DIF:
3540                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3541                                                      domain->sig.dif.app_tag);
3542                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3543                 break;
3544         default:
3545                 pr_err("Bad signature type given.\n");
3546                 return 1;
3547         }
3548
3549         *seg += sizeof(*psv_seg);
3550         *size += sizeof(*psv_seg) / 16;
3551
3552         return 0;
3553 }
3554
3555 static int set_reg_wr(struct mlx5_ib_qp *qp,
3556                       struct ib_reg_wr *wr,
3557                       void **seg, int *size)
3558 {
3559         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3560         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3561
3562         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3563                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3564                              "Invalid IB_SEND_INLINE send flag\n");
3565                 return -EINVAL;
3566         }
3567
3568         set_reg_umr_seg(*seg, mr);
3569         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3570         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3571         if (unlikely((*seg == qp->sq.qend)))
3572                 *seg = mlx5_get_send_wqe(qp, 0);
3573
3574         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3575         *seg += sizeof(struct mlx5_mkey_seg);
3576         *size += sizeof(struct mlx5_mkey_seg) / 16;
3577         if (unlikely((*seg == qp->sq.qend)))
3578                 *seg = mlx5_get_send_wqe(qp, 0);
3579
3580         set_reg_data_seg(*seg, mr, pd);
3581         *seg += sizeof(struct mlx5_wqe_data_seg);
3582         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3583
3584         return 0;
3585 }
3586
3587 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3588 {
3589         set_linv_umr_seg(*seg);
3590         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3591         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3592         if (unlikely((*seg == qp->sq.qend)))
3593                 *seg = mlx5_get_send_wqe(qp, 0);
3594         set_linv_mkey_seg(*seg);
3595         *seg += sizeof(struct mlx5_mkey_seg);
3596         *size += sizeof(struct mlx5_mkey_seg) / 16;
3597         if (unlikely((*seg == qp->sq.qend)))
3598                 *seg = mlx5_get_send_wqe(qp, 0);
3599 }
3600
3601 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3602 {
3603         __be32 *p = NULL;
3604         int tidx = idx;
3605         int i, j;
3606
3607         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3608         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3609                 if ((i & 0xf) == 0) {
3610                         void *buf = mlx5_get_send_wqe(qp, tidx);
3611                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3612                         p = buf;
3613                         j = 0;
3614                 }
3615                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3616                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3617                          be32_to_cpu(p[j + 3]));
3618         }
3619 }
3620
3621 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3622                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3623 {
3624         while (bytecnt > 0) {
3625                 __iowrite64_copy(dst++, src++, 8);
3626                 __iowrite64_copy(dst++, src++, 8);
3627                 __iowrite64_copy(dst++, src++, 8);
3628                 __iowrite64_copy(dst++, src++, 8);
3629                 __iowrite64_copy(dst++, src++, 8);
3630                 __iowrite64_copy(dst++, src++, 8);
3631                 __iowrite64_copy(dst++, src++, 8);
3632                 __iowrite64_copy(dst++, src++, 8);
3633                 bytecnt -= 64;
3634                 if (unlikely(src == qp->sq.qend))
3635                         src = mlx5_get_send_wqe(qp, 0);
3636         }
3637 }
3638
3639 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3640 {
3641         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3642                      wr->send_flags & IB_SEND_FENCE))
3643                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3644
3645         if (unlikely(fence)) {
3646                 if (wr->send_flags & IB_SEND_FENCE)
3647                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3648                 else
3649                         return fence;
3650         } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3651                 return MLX5_FENCE_MODE_FENCE;
3652         }
3653
3654         return 0;
3655 }
3656
3657 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3658                      struct mlx5_wqe_ctrl_seg **ctrl,
3659                      struct ib_send_wr *wr, unsigned *idx,
3660                      int *size, int nreq)
3661 {
3662         int err = 0;
3663
3664         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3665                 err = -ENOMEM;
3666                 return err;
3667         }
3668
3669         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3670         *seg = mlx5_get_send_wqe(qp, *idx);
3671         *ctrl = *seg;
3672         *(uint32_t *)(*seg + 8) = 0;
3673         (*ctrl)->imm = send_ieth(wr);
3674         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3675                 (wr->send_flags & IB_SEND_SIGNALED ?
3676                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3677                 (wr->send_flags & IB_SEND_SOLICITED ?
3678                  MLX5_WQE_CTRL_SOLICITED : 0);
3679
3680         *seg += sizeof(**ctrl);
3681         *size = sizeof(**ctrl) / 16;
3682
3683         return err;
3684 }
3685
3686 static void finish_wqe(struct mlx5_ib_qp *qp,
3687                        struct mlx5_wqe_ctrl_seg *ctrl,
3688                        u8 size, unsigned idx, u64 wr_id,
3689                        int nreq, u8 fence, u8 next_fence,
3690                        u32 mlx5_opcode)
3691 {
3692         u8 opmod = 0;
3693
3694         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3695                                              mlx5_opcode | ((u32)opmod << 24));
3696         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3697         ctrl->fm_ce_se |= fence;
3698         qp->fm_cache = next_fence;
3699         if (unlikely(qp->wq_sig))
3700                 ctrl->signature = wq_sig(ctrl);
3701
3702         qp->sq.wrid[idx] = wr_id;
3703         qp->sq.w_list[idx].opcode = mlx5_opcode;
3704         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3705         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3706         qp->sq.w_list[idx].next = qp->sq.cur_post;
3707 }
3708
3709
3710 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3711                       struct ib_send_wr **bad_wr)
3712 {
3713         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3714         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3715         struct mlx5_core_dev *mdev = dev->mdev;
3716         struct mlx5_ib_qp *qp;
3717         struct mlx5_ib_mr *mr;
3718         struct mlx5_wqe_data_seg *dpseg;
3719         struct mlx5_wqe_xrc_seg *xrc;
3720         struct mlx5_bf *bf;
3721         int uninitialized_var(size);
3722         void *qend;
3723         unsigned long flags;
3724         unsigned idx;
3725         int err = 0;
3726         int inl = 0;
3727         int num_sge;
3728         void *seg;
3729         int nreq;
3730         int i;
3731         u8 next_fence = 0;
3732         u8 fence;
3733
3734         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3735                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3736
3737         qp = to_mqp(ibqp);
3738         bf = qp->bf;
3739         qend = qp->sq.qend;
3740
3741         spin_lock_irqsave(&qp->sq.lock, flags);
3742
3743         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3744                 err = -EIO;
3745                 *bad_wr = wr;
3746                 nreq = 0;
3747                 goto out;
3748         }
3749
3750         for (nreq = 0; wr; nreq++, wr = wr->next) {
3751                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3752                         mlx5_ib_warn(dev, "\n");
3753                         err = -EINVAL;
3754                         *bad_wr = wr;
3755                         goto out;
3756                 }
3757
3758                 fence = qp->fm_cache;
3759                 num_sge = wr->num_sge;
3760                 if (unlikely(num_sge > qp->sq.max_gs)) {
3761                         mlx5_ib_warn(dev, "\n");
3762                         err = -ENOMEM;
3763                         *bad_wr = wr;
3764                         goto out;
3765                 }
3766
3767                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3768                 if (err) {
3769                         mlx5_ib_warn(dev, "\n");
3770                         err = -ENOMEM;
3771                         *bad_wr = wr;
3772                         goto out;
3773                 }
3774
3775                 switch (ibqp->qp_type) {
3776                 case IB_QPT_XRC_INI:
3777                         xrc = seg;
3778                         seg += sizeof(*xrc);
3779                         size += sizeof(*xrc) / 16;
3780                         /* fall through */
3781                 case IB_QPT_RC:
3782                         switch (wr->opcode) {
3783                         case IB_WR_RDMA_READ:
3784                         case IB_WR_RDMA_WRITE:
3785                         case IB_WR_RDMA_WRITE_WITH_IMM:
3786                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3787                                               rdma_wr(wr)->rkey);
3788                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3789                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3790                                 break;
3791
3792                         case IB_WR_ATOMIC_CMP_AND_SWP:
3793                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3794                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3795                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3796                                 err = -ENOSYS;
3797                                 *bad_wr = wr;
3798                                 goto out;
3799
3800                         case IB_WR_LOCAL_INV:
3801                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3802                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3803                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3804                                 set_linv_wr(qp, &seg, &size);
3805                                 num_sge = 0;
3806                                 break;
3807
3808                         case IB_WR_REG_MR:
3809                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3810                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3811                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3812                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3813                                 if (err) {
3814                                         *bad_wr = wr;
3815                                         goto out;
3816                                 }
3817                                 num_sge = 0;
3818                                 break;
3819
3820                         case IB_WR_REG_SIG_MR:
3821                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3822                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3823
3824                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3825                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3826                                 if (err) {
3827                                         mlx5_ib_warn(dev, "\n");
3828                                         *bad_wr = wr;
3829                                         goto out;
3830                                 }
3831
3832                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3833                                            nreq, get_fence(fence, wr),
3834                                            next_fence, MLX5_OPCODE_UMR);
3835                                 /*
3836                                  * SET_PSV WQEs are not signaled and solicited
3837                                  * on error
3838                                  */
3839                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3840                                 wr->send_flags |= IB_SEND_SOLICITED;
3841                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3842                                                 &idx, &size, nreq);
3843                                 if (err) {
3844                                         mlx5_ib_warn(dev, "\n");
3845                                         err = -ENOMEM;
3846                                         *bad_wr = wr;
3847                                         goto out;
3848                                 }
3849
3850                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3851                                                  mr->sig->psv_memory.psv_idx, &seg,
3852                                                  &size);
3853                                 if (err) {
3854                                         mlx5_ib_warn(dev, "\n");
3855                                         *bad_wr = wr;
3856                                         goto out;
3857                                 }
3858
3859                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3860                                            nreq, get_fence(fence, wr),
3861                                            next_fence, MLX5_OPCODE_SET_PSV);
3862                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3863                                                 &idx, &size, nreq);
3864                                 if (err) {
3865                                         mlx5_ib_warn(dev, "\n");
3866                                         err = -ENOMEM;
3867                                         *bad_wr = wr;
3868                                         goto out;
3869                                 }
3870
3871                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3872                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3873                                                  mr->sig->psv_wire.psv_idx, &seg,
3874                                                  &size);
3875                                 if (err) {
3876                                         mlx5_ib_warn(dev, "\n");
3877                                         *bad_wr = wr;
3878                                         goto out;
3879                                 }
3880
3881                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3882                                            nreq, get_fence(fence, wr),
3883                                            next_fence, MLX5_OPCODE_SET_PSV);
3884                                 num_sge = 0;
3885                                 goto skip_psv;
3886
3887                         default:
3888                                 break;
3889                         }
3890                         break;
3891
3892                 case IB_QPT_UC:
3893                         switch (wr->opcode) {
3894                         case IB_WR_RDMA_WRITE:
3895                         case IB_WR_RDMA_WRITE_WITH_IMM:
3896                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3897                                               rdma_wr(wr)->rkey);
3898                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3899                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3900                                 break;
3901
3902                         default:
3903                                 break;
3904                         }
3905                         break;
3906
3907                 case IB_QPT_SMI:
3908                 case MLX5_IB_QPT_HW_GSI:
3909                         set_datagram_seg(seg, wr);
3910                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3911                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3912                         if (unlikely((seg == qend)))
3913                                 seg = mlx5_get_send_wqe(qp, 0);
3914                         break;
3915                 case IB_QPT_UD:
3916                         set_datagram_seg(seg, wr);
3917                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3918                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3919
3920                         if (unlikely((seg == qend)))
3921                                 seg = mlx5_get_send_wqe(qp, 0);
3922
3923                         /* handle qp that supports ud offload */
3924                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3925                                 struct mlx5_wqe_eth_pad *pad;
3926
3927                                 pad = seg;
3928                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3929                                 seg += sizeof(struct mlx5_wqe_eth_pad);
3930                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3931
3932                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
3933
3934                                 if (unlikely((seg == qend)))
3935                                         seg = mlx5_get_send_wqe(qp, 0);
3936                         }
3937                         break;
3938                 case MLX5_IB_QPT_REG_UMR:
3939                         if (wr->opcode != MLX5_IB_WR_UMR) {
3940                                 err = -EINVAL;
3941                                 mlx5_ib_warn(dev, "bad opcode\n");
3942                                 goto out;
3943                         }
3944                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3945                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3946                         set_reg_umr_segment(seg, wr);
3947                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3948                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3949                         if (unlikely((seg == qend)))
3950                                 seg = mlx5_get_send_wqe(qp, 0);
3951                         set_reg_mkey_segment(seg, wr);
3952                         seg += sizeof(struct mlx5_mkey_seg);
3953                         size += sizeof(struct mlx5_mkey_seg) / 16;
3954                         if (unlikely((seg == qend)))
3955                                 seg = mlx5_get_send_wqe(qp, 0);
3956                         break;
3957
3958                 default:
3959                         break;
3960                 }
3961
3962                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3963                         int uninitialized_var(sz);
3964
3965                         err = set_data_inl_seg(qp, wr, seg, &sz);
3966                         if (unlikely(err)) {
3967                                 mlx5_ib_warn(dev, "\n");
3968                                 *bad_wr = wr;
3969                                 goto out;
3970                         }
3971                         inl = 1;
3972                         size += sz;
3973                 } else {
3974                         dpseg = seg;
3975                         for (i = 0; i < num_sge; i++) {
3976                                 if (unlikely(dpseg == qend)) {
3977                                         seg = mlx5_get_send_wqe(qp, 0);
3978                                         dpseg = seg;
3979                                 }
3980                                 if (likely(wr->sg_list[i].length)) {
3981                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
3982                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
3983                                         dpseg++;
3984                                 }
3985                         }
3986                 }
3987
3988                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3989                            get_fence(fence, wr), next_fence,
3990                            mlx5_ib_opcode[wr->opcode]);
3991 skip_psv:
3992                 if (0)
3993                         dump_wqe(qp, idx, size);
3994         }
3995
3996 out:
3997         if (likely(nreq)) {
3998                 qp->sq.head += nreq;
3999
4000                 /* Make sure that descriptors are written before
4001                  * updating doorbell record and ringing the doorbell
4002                  */
4003                 wmb();
4004
4005                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4006
4007                 /* Make sure doorbell record is visible to the HCA before
4008                  * we hit doorbell */
4009                 wmb();
4010
4011                 if (bf->need_lock)
4012                         spin_lock(&bf->lock);
4013                 else
4014                         __acquire(&bf->lock);
4015
4016                 /* TBD enable WC */
4017                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4018                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4019                         /* wc_wmb(); */
4020                 } else {
4021                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4022                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4023                         /* Make sure doorbells don't leak out of SQ spinlock
4024                          * and reach the HCA out of order.
4025                          */
4026                         mmiowb();
4027                 }
4028                 bf->offset ^= bf->buf_size;
4029                 if (bf->need_lock)
4030                         spin_unlock(&bf->lock);
4031                 else
4032                         __release(&bf->lock);
4033         }
4034
4035         spin_unlock_irqrestore(&qp->sq.lock, flags);
4036
4037         return err;
4038 }
4039
4040 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4041 {
4042         sig->signature = calc_sig(sig, size);
4043 }
4044
4045 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4046                       struct ib_recv_wr **bad_wr)
4047 {
4048         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4049         struct mlx5_wqe_data_seg *scat;
4050         struct mlx5_rwqe_sig *sig;
4051         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4052         struct mlx5_core_dev *mdev = dev->mdev;
4053         unsigned long flags;
4054         int err = 0;
4055         int nreq;
4056         int ind;
4057         int i;
4058
4059         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4060                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4061
4062         spin_lock_irqsave(&qp->rq.lock, flags);
4063
4064         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4065                 err = -EIO;
4066                 *bad_wr = wr;
4067                 nreq = 0;
4068                 goto out;
4069         }
4070
4071         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4072
4073         for (nreq = 0; wr; nreq++, wr = wr->next) {
4074                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4075                         err = -ENOMEM;
4076                         *bad_wr = wr;
4077                         goto out;
4078                 }
4079
4080                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4081                         err = -EINVAL;
4082                         *bad_wr = wr;
4083                         goto out;
4084                 }
4085
4086                 scat = get_recv_wqe(qp, ind);
4087                 if (qp->wq_sig)
4088                         scat++;
4089
4090                 for (i = 0; i < wr->num_sge; i++)
4091                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4092
4093                 if (i < qp->rq.max_gs) {
4094                         scat[i].byte_count = 0;
4095                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4096                         scat[i].addr       = 0;
4097                 }
4098
4099                 if (qp->wq_sig) {
4100                         sig = (struct mlx5_rwqe_sig *)scat;
4101                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4102                 }
4103
4104                 qp->rq.wrid[ind] = wr->wr_id;
4105
4106                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4107         }
4108
4109 out:
4110         if (likely(nreq)) {
4111                 qp->rq.head += nreq;
4112
4113                 /* Make sure that descriptors are written before
4114                  * doorbell record.
4115                  */
4116                 wmb();
4117
4118                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4119         }
4120
4121         spin_unlock_irqrestore(&qp->rq.lock, flags);
4122
4123         return err;
4124 }
4125
4126 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4127 {
4128         switch (mlx5_state) {
4129         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4130         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4131         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4132         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4133         case MLX5_QP_STATE_SQ_DRAINING:
4134         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4135         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4136         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4137         default:                     return -1;
4138         }
4139 }
4140
4141 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4142 {
4143         switch (mlx5_mig_state) {
4144         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4145         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4146         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4147         default: return -1;
4148         }
4149 }
4150
4151 static int to_ib_qp_access_flags(int mlx5_flags)
4152 {
4153         int ib_flags = 0;
4154
4155         if (mlx5_flags & MLX5_QP_BIT_RRE)
4156                 ib_flags |= IB_ACCESS_REMOTE_READ;
4157         if (mlx5_flags & MLX5_QP_BIT_RWE)
4158                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4159         if (mlx5_flags & MLX5_QP_BIT_RAE)
4160                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4161
4162         return ib_flags;
4163 }
4164
4165 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4166                                 struct mlx5_qp_path *path)
4167 {
4168         struct mlx5_core_dev *dev = ibdev->mdev;
4169
4170         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4171         ib_ah_attr->port_num      = path->port;
4172
4173         if (ib_ah_attr->port_num == 0 ||
4174             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4175                 return;
4176
4177         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4178
4179         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4180         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4181         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4182         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4183         if (ib_ah_attr->ah_flags) {
4184                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4185                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4186                 ib_ah_attr->grh.traffic_class =
4187                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4188                 ib_ah_attr->grh.flow_label =
4189                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4190                 memcpy(ib_ah_attr->grh.dgid.raw,
4191                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4192         }
4193 }
4194
4195 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4196                                         struct mlx5_ib_sq *sq,
4197                                         u8 *sq_state)
4198 {
4199         void *out;
4200         void *sqc;
4201         int inlen;
4202         int err;
4203
4204         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4205         out = mlx5_vzalloc(inlen);
4206         if (!out)
4207                 return -ENOMEM;
4208
4209         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4210         if (err)
4211                 goto out;
4212
4213         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4214         *sq_state = MLX5_GET(sqc, sqc, state);
4215         sq->state = *sq_state;
4216
4217 out:
4218         kvfree(out);
4219         return err;
4220 }
4221
4222 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4223                                         struct mlx5_ib_rq *rq,
4224                                         u8 *rq_state)
4225 {
4226         void *out;
4227         void *rqc;
4228         int inlen;
4229         int err;
4230
4231         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4232         out = mlx5_vzalloc(inlen);
4233         if (!out)
4234                 return -ENOMEM;
4235
4236         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4237         if (err)
4238                 goto out;
4239
4240         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4241         *rq_state = MLX5_GET(rqc, rqc, state);
4242         rq->state = *rq_state;
4243
4244 out:
4245         kvfree(out);
4246         return err;
4247 }
4248
4249 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4250                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4251 {
4252         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4253                 [MLX5_RQC_STATE_RST] = {
4254                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4255                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4256                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4257                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4258                 },
4259                 [MLX5_RQC_STATE_RDY] = {
4260                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4261                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4262                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4263                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4264                 },
4265                 [MLX5_RQC_STATE_ERR] = {
4266                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4267                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4268                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4269                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4270                 },
4271                 [MLX5_RQ_STATE_NA] = {
4272                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4273                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4274                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4275                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4276                 },
4277         };
4278
4279         *qp_state = sqrq_trans[rq_state][sq_state];
4280
4281         if (*qp_state == MLX5_QP_STATE_BAD) {
4282                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4283                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4284                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4285                 return -EINVAL;
4286         }
4287
4288         if (*qp_state == MLX5_QP_STATE)
4289                 *qp_state = qp->state;
4290
4291         return 0;
4292 }
4293
4294 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4295                                      struct mlx5_ib_qp *qp,
4296                                      u8 *raw_packet_qp_state)
4297 {
4298         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4299         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4300         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4301         int err;
4302         u8 sq_state = MLX5_SQ_STATE_NA;
4303         u8 rq_state = MLX5_RQ_STATE_NA;
4304
4305         if (qp->sq.wqe_cnt) {
4306                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4307                 if (err)
4308                         return err;
4309         }
4310
4311         if (qp->rq.wqe_cnt) {
4312                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4313                 if (err)
4314                         return err;
4315         }
4316
4317         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4318                                       raw_packet_qp_state);
4319 }
4320
4321 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4322                          struct ib_qp_attr *qp_attr)
4323 {
4324         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4325         struct mlx5_qp_context *context;
4326         int mlx5_state;
4327         u32 *outb;
4328         int err = 0;
4329
4330         outb = kzalloc(outlen, GFP_KERNEL);
4331         if (!outb)
4332                 return -ENOMEM;
4333
4334         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4335                                  outlen);
4336         if (err)
4337                 goto out;
4338
4339         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4340         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4341
4342         mlx5_state = be32_to_cpu(context->flags) >> 28;
4343
4344         qp->state                    = to_ib_qp_state(mlx5_state);
4345         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4346         qp_attr->path_mig_state      =
4347                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4348         qp_attr->qkey                = be32_to_cpu(context->qkey);
4349         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4350         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4351         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4352         qp_attr->qp_access_flags     =
4353                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4354
4355         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4356                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4357                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4358                 qp_attr->alt_pkey_index =
4359                         be16_to_cpu(context->alt_path.pkey_index);
4360                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4361         }
4362
4363         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4364         qp_attr->port_num = context->pri_path.port;
4365
4366         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4367         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4368
4369         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4370
4371         qp_attr->max_dest_rd_atomic =
4372                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4373         qp_attr->min_rnr_timer      =
4374                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4375         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4376         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4377         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4378         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4379
4380 out:
4381         kfree(outb);
4382         return err;
4383 }
4384
4385 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4386                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4387 {
4388         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4389         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4390         int err = 0;
4391         u8 raw_packet_qp_state;
4392
4393         if (ibqp->rwq_ind_tbl)
4394                 return -ENOSYS;
4395
4396         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4397                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4398                                             qp_init_attr);
4399
4400 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4401         /*
4402          * Wait for any outstanding page faults, in case the user frees memory
4403          * based upon this query's result.
4404          */
4405         flush_workqueue(mlx5_ib_page_fault_wq);
4406 #endif
4407
4408         mutex_lock(&qp->mutex);
4409
4410         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4411                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4412                 if (err)
4413                         goto out;
4414                 qp->state = raw_packet_qp_state;
4415                 qp_attr->port_num = 1;
4416         } else {
4417                 err = query_qp_attr(dev, qp, qp_attr);
4418                 if (err)
4419                         goto out;
4420         }
4421
4422         qp_attr->qp_state            = qp->state;
4423         qp_attr->cur_qp_state        = qp_attr->qp_state;
4424         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4425         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4426
4427         if (!ibqp->uobject) {
4428                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4429                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4430                 qp_init_attr->qp_context = ibqp->qp_context;
4431         } else {
4432                 qp_attr->cap.max_send_wr  = 0;
4433                 qp_attr->cap.max_send_sge = 0;
4434         }
4435
4436         qp_init_attr->qp_type = ibqp->qp_type;
4437         qp_init_attr->recv_cq = ibqp->recv_cq;
4438         qp_init_attr->send_cq = ibqp->send_cq;
4439         qp_init_attr->srq = ibqp->srq;
4440         qp_attr->cap.max_inline_data = qp->max_inline_data;
4441
4442         qp_init_attr->cap            = qp_attr->cap;
4443
4444         qp_init_attr->create_flags = 0;
4445         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4446                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4447
4448         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4449                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4450         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4451                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4452         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4453                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4454         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4455                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4456
4457         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4458                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4459
4460 out:
4461         mutex_unlock(&qp->mutex);
4462         return err;
4463 }
4464
4465 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4466                                           struct ib_ucontext *context,
4467                                           struct ib_udata *udata)
4468 {
4469         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4470         struct mlx5_ib_xrcd *xrcd;
4471         int err;
4472
4473         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4474                 return ERR_PTR(-ENOSYS);
4475
4476         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4477         if (!xrcd)
4478                 return ERR_PTR(-ENOMEM);
4479
4480         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4481         if (err) {
4482                 kfree(xrcd);
4483                 return ERR_PTR(-ENOMEM);
4484         }
4485
4486         return &xrcd->ibxrcd;
4487 }
4488
4489 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4490 {
4491         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4492         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4493         int err;
4494
4495         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4496         if (err) {
4497                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4498                 return err;
4499         }
4500
4501         kfree(xrcd);
4502
4503         return 0;
4504 }
4505
4506 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4507                       struct ib_wq_init_attr *init_attr)
4508 {
4509         struct mlx5_ib_dev *dev;
4510         __be64 *rq_pas0;
4511         void *in;
4512         void *rqc;
4513         void *wq;
4514         int inlen;
4515         int err;
4516
4517         dev = to_mdev(pd->device);
4518
4519         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4520         in = mlx5_vzalloc(inlen);
4521         if (!in)
4522                 return -ENOMEM;
4523
4524         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4525         MLX5_SET(rqc,  rqc, mem_rq_type,
4526                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4527         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4528         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4529         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4530         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4531         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4532         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4533         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4534         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4535         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4536         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4537         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4538         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4539         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4540         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4541         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4542         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4543         err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4544         kvfree(in);
4545         return err;
4546 }
4547
4548 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4549                             struct ib_wq_init_attr *wq_init_attr,
4550                             struct mlx5_ib_create_wq *ucmd,
4551                             struct mlx5_ib_rwq *rwq)
4552 {
4553         /* Sanity check RQ size before proceeding */
4554         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4555                 return -EINVAL;
4556
4557         if (!ucmd->rq_wqe_count)
4558                 return -EINVAL;
4559
4560         rwq->wqe_count = ucmd->rq_wqe_count;
4561         rwq->wqe_shift = ucmd->rq_wqe_shift;
4562         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4563         rwq->log_rq_stride = rwq->wqe_shift;
4564         rwq->log_rq_size = ilog2(rwq->wqe_count);
4565         return 0;
4566 }
4567
4568 static int prepare_user_rq(struct ib_pd *pd,
4569                            struct ib_wq_init_attr *init_attr,
4570                            struct ib_udata *udata,
4571                            struct mlx5_ib_rwq *rwq)
4572 {
4573         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4574         struct mlx5_ib_create_wq ucmd = {};
4575         int err;
4576         size_t required_cmd_sz;
4577
4578         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4579         if (udata->inlen < required_cmd_sz) {
4580                 mlx5_ib_dbg(dev, "invalid inlen\n");
4581                 return -EINVAL;
4582         }
4583
4584         if (udata->inlen > sizeof(ucmd) &&
4585             !ib_is_udata_cleared(udata, sizeof(ucmd),
4586                                  udata->inlen - sizeof(ucmd))) {
4587                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4588                 return -EOPNOTSUPP;
4589         }
4590
4591         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4592                 mlx5_ib_dbg(dev, "copy failed\n");
4593                 return -EFAULT;
4594         }
4595
4596         if (ucmd.comp_mask) {
4597                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4598                 return -EOPNOTSUPP;
4599         }
4600
4601         if (ucmd.reserved) {
4602                 mlx5_ib_dbg(dev, "invalid reserved\n");
4603                 return -EOPNOTSUPP;
4604         }
4605
4606         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4607         if (err) {
4608                 mlx5_ib_dbg(dev, "err %d\n", err);
4609                 return err;
4610         }
4611
4612         err = create_user_rq(dev, pd, rwq, &ucmd);
4613         if (err) {
4614                 mlx5_ib_dbg(dev, "err %d\n", err);
4615                 if (err)
4616                         return err;
4617         }
4618
4619         rwq->user_index = ucmd.user_index;
4620         return 0;
4621 }
4622
4623 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4624                                 struct ib_wq_init_attr *init_attr,
4625                                 struct ib_udata *udata)
4626 {
4627         struct mlx5_ib_dev *dev;
4628         struct mlx5_ib_rwq *rwq;
4629         struct mlx5_ib_create_wq_resp resp = {};
4630         size_t min_resp_len;
4631         int err;
4632
4633         if (!udata)
4634                 return ERR_PTR(-ENOSYS);
4635
4636         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4637         if (udata->outlen && udata->outlen < min_resp_len)
4638                 return ERR_PTR(-EINVAL);
4639
4640         dev = to_mdev(pd->device);
4641         switch (init_attr->wq_type) {
4642         case IB_WQT_RQ:
4643                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4644                 if (!rwq)
4645                         return ERR_PTR(-ENOMEM);
4646                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4647                 if (err)
4648                         goto err;
4649                 err = create_rq(rwq, pd, init_attr);
4650                 if (err)
4651                         goto err_user_rq;
4652                 break;
4653         default:
4654                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4655                             init_attr->wq_type);
4656                 return ERR_PTR(-EINVAL);
4657         }
4658
4659         rwq->ibwq.wq_num = rwq->rqn;
4660         rwq->ibwq.state = IB_WQS_RESET;
4661         if (udata->outlen) {
4662                 resp.response_length = offsetof(typeof(resp), response_length) +
4663                                 sizeof(resp.response_length);
4664                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4665                 if (err)
4666                         goto err_copy;
4667         }
4668
4669         return &rwq->ibwq;
4670
4671 err_copy:
4672         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4673 err_user_rq:
4674         destroy_user_rq(pd, rwq);
4675 err:
4676         kfree(rwq);
4677         return ERR_PTR(err);
4678 }
4679
4680 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4681 {
4682         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4683         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4684
4685         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4686         destroy_user_rq(wq->pd, rwq);
4687         kfree(rwq);
4688
4689         return 0;
4690 }
4691
4692 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4693                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4694                                                       struct ib_udata *udata)
4695 {
4696         struct mlx5_ib_dev *dev = to_mdev(device);
4697         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4698         int sz = 1 << init_attr->log_ind_tbl_size;
4699         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4700         size_t min_resp_len;
4701         int inlen;
4702         int err;
4703         int i;
4704         u32 *in;
4705         void *rqtc;
4706
4707         if (udata->inlen > 0 &&
4708             !ib_is_udata_cleared(udata, 0,
4709                                  udata->inlen))
4710                 return ERR_PTR(-EOPNOTSUPP);
4711
4712         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4713         if (udata->outlen && udata->outlen < min_resp_len)
4714                 return ERR_PTR(-EINVAL);
4715
4716         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4717         if (!rwq_ind_tbl)
4718                 return ERR_PTR(-ENOMEM);
4719
4720         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4721         in = mlx5_vzalloc(inlen);
4722         if (!in) {
4723                 err = -ENOMEM;
4724                 goto err;
4725         }
4726
4727         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4728
4729         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4730         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4731
4732         for (i = 0; i < sz; i++)
4733                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4734
4735         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4736         kvfree(in);
4737
4738         if (err)
4739                 goto err;
4740
4741         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4742         if (udata->outlen) {
4743                 resp.response_length = offsetof(typeof(resp), response_length) +
4744                                         sizeof(resp.response_length);
4745                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4746                 if (err)
4747                         goto err_copy;
4748         }
4749
4750         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4751
4752 err_copy:
4753         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4754 err:
4755         kfree(rwq_ind_tbl);
4756         return ERR_PTR(err);
4757 }
4758
4759 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4760 {
4761         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4762         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4763
4764         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4765
4766         kfree(rwq_ind_tbl);
4767         return 0;
4768 }
4769
4770 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4771                       u32 wq_attr_mask, struct ib_udata *udata)
4772 {
4773         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4774         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4775         struct mlx5_ib_modify_wq ucmd = {};
4776         size_t required_cmd_sz;
4777         int curr_wq_state;
4778         int wq_state;
4779         int inlen;
4780         int err;
4781         void *rqc;
4782         void *in;
4783
4784         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4785         if (udata->inlen < required_cmd_sz)
4786                 return -EINVAL;
4787
4788         if (udata->inlen > sizeof(ucmd) &&
4789             !ib_is_udata_cleared(udata, sizeof(ucmd),
4790                                  udata->inlen - sizeof(ucmd)))
4791                 return -EOPNOTSUPP;
4792
4793         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4794                 return -EFAULT;
4795
4796         if (ucmd.comp_mask || ucmd.reserved)
4797                 return -EOPNOTSUPP;
4798
4799         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4800         in = mlx5_vzalloc(inlen);
4801         if (!in)
4802                 return -ENOMEM;
4803
4804         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4805
4806         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4807                 wq_attr->curr_wq_state : wq->state;
4808         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4809                 wq_attr->wq_state : curr_wq_state;
4810         if (curr_wq_state == IB_WQS_ERR)
4811                 curr_wq_state = MLX5_RQC_STATE_ERR;
4812         if (wq_state == IB_WQS_ERR)
4813                 wq_state = MLX5_RQC_STATE_ERR;
4814         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4815         MLX5_SET(rqc, rqc, state, wq_state);
4816
4817         err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4818         kvfree(in);
4819         if (!err)
4820                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4821
4822         return err;
4823 }